Searched refs:msr (Results 1 - 200 of 364) sorted by relevance

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/linux-4.1.27/arch/x86/lib/
H A D	msr-reg-export.c	2 #include <asm/msr.h>
H A D	msr.c	3 #include <asm/msr.h> 5 struct msr *msrs_alloc(void) msrs_alloc() 7 struct msr *msrs = NULL; msrs_alloc() 9 msrs = alloc_percpu(struct msr); msrs_alloc() 19 void msrs_free(struct msr *msrs) msrs_free() 28 * @msr: MSR to read 35 int msr_read(u32 msr, struct msr *m) msr_read() argument 40 err = rdmsrl_safe(msr, &val); msr_read() 50 * @msr: MSR to write 53 int msr_write(u32 msr, struct msr *m) msr_write() argument 55 return wrmsrl_safe(msr, m->q); msr_write() 58 static inline int __flip_bit(u32 msr, u8 bit, bool set) __flip_bit() argument 60 struct msr m, m1; __flip_bit() 66 err = msr_read(msr, &m); __flip_bit() 79 err = msr_write(msr, &m1); __flip_bit() 87 * Set @bit in a MSR @msr. 94 int msr_set_bit(u32 msr, u8 bit) msr_set_bit() argument 96 return __flip_bit(msr, bit, true); msr_set_bit() 100 * Clear @bit in a MSR @msr. 107 int msr_clear_bit(u32 msr, u8 bit) msr_clear_bit() argument 109 return __flip_bit(msr, bit, false); msr_clear_bit()
H A D	Makefile	17 obj-$(CONFIG_SMP) += msr-smp.o cache-smp.o 26 obj-y += msr.o msr-reg.o msr-reg-export.o
H A D	msr-smp.c	4 #include <asm/msr.h> 9 struct msr *reg; __rdmsr_on_cpu() 23 struct msr *reg; __wrmsr_on_cpu() 98 struct msr *msrs, __rwmsr_on_cpus() 125 void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs) rdmsr_on_cpus() 139 void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs) wrmsr_on_cpus()
H A D	msr-reg.S	5 #include <asm/msr.h>
/linux-4.1.27/arch/x86/kernel/cpu/
H A D	perfctr-watchdog.c	43 /* converts an msr to an appropriate reservation bit */ nmi_perfctr_msr_to_bit() 44 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr) nmi_perfctr_msr_to_bit() argument 49 if (msr >= MSR_F15H_PERF_CTR) nmi_perfctr_msr_to_bit() 50 return (msr - MSR_F15H_PERF_CTR) >> 1; nmi_perfctr_msr_to_bit() 51 return msr - MSR_K7_PERFCTR0; nmi_perfctr_msr_to_bit() 54 return msr - MSR_ARCH_PERFMON_PERFCTR0; nmi_perfctr_msr_to_bit() 58 return msr - MSR_P6_PERFCTR0; nmi_perfctr_msr_to_bit() 60 return msr - MSR_KNC_PERFCTR0; nmi_perfctr_msr_to_bit() 62 return msr - MSR_P4_BPU_PERFCTR0; nmi_perfctr_msr_to_bit() 69 * converts an msr to an appropriate reservation bit 72 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr) nmi_evntsel_msr_to_bit() argument 77 if (msr >= MSR_F15H_PERF_CTL) nmi_evntsel_msr_to_bit() 78 return (msr - MSR_F15H_PERF_CTL) >> 1; nmi_evntsel_msr_to_bit() 79 return msr - MSR_K7_EVNTSEL0; nmi_evntsel_msr_to_bit() 82 return msr - MSR_ARCH_PERFMON_EVENTSEL0; nmi_evntsel_msr_to_bit() 86 return msr - MSR_P6_EVNTSEL0; nmi_evntsel_msr_to_bit() 88 return msr - MSR_KNC_EVNTSEL0; nmi_evntsel_msr_to_bit() 90 return msr - MSR_P4_BSU_ESCR0; nmi_evntsel_msr_to_bit() 106 int reserve_perfctr_nmi(unsigned int msr) reserve_perfctr_nmi() argument 110 counter = nmi_perfctr_msr_to_bit(msr); reserve_perfctr_nmi() 121 void release_perfctr_nmi(unsigned int msr) release_perfctr_nmi() argument 125 counter = nmi_perfctr_msr_to_bit(msr); release_perfctr_nmi() 134 int reserve_evntsel_nmi(unsigned int msr) reserve_evntsel_nmi() argument 138 counter = nmi_evntsel_msr_to_bit(msr); reserve_evntsel_nmi() 149 void release_evntsel_nmi(unsigned int msr) release_evntsel_nmi() argument 153 counter = nmi_evntsel_msr_to_bit(msr); release_evntsel_nmi()
H A D	perf_event_intel_uncore_snbep.c	100 .msr = SNBEP_C0_MSR_PMON_BOX_FILTER, \ 325 unsigned msr; snbep_uncore_msr_disable_box() local 327 msr = uncore_msr_box_ctl(box); snbep_uncore_msr_disable_box() 328 if (msr) { snbep_uncore_msr_disable_box() 329 rdmsrl(msr, config); snbep_uncore_msr_disable_box() 331 wrmsrl(msr, config); snbep_uncore_msr_disable_box() 338 unsigned msr; snbep_uncore_msr_enable_box() local 340 msr = uncore_msr_box_ctl(box); snbep_uncore_msr_enable_box() 341 if (msr) { snbep_uncore_msr_enable_box() 342 rdmsrl(msr, config); snbep_uncore_msr_enable_box() 344 wrmsrl(msr, config); snbep_uncore_msr_enable_box() 369 unsigned msr = uncore_msr_box_ctl(box); snbep_uncore_msr_init_box() local 371 if (msr) snbep_uncore_msr_init_box() 372 wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT); snbep_uncore_msr_init_box() 731 for (er = snbep_uncore_cbox_extra_regs; er->msr; er++) { snbep_cbox_hw_config() 1154 unsigned msr = uncore_msr_box_ctl(box); ivbep_uncore_msr_init_box() local 1155 if (msr) ivbep_uncore_msr_init_box() 1156 wrmsrl(msr, IVBEP_PMON_BOX_CTL_INT); ivbep_uncore_msr_init_box() 1385 for (er = ivbep_uncore_cbox_extra_regs; er->msr; er++) { ivbep_cbox_hw_config() 1871 for (er = hswep_uncore_cbox_extra_regs; er->msr; er++) { hswep_cbox_hw_config() 1934 unsigned msr = uncore_msr_box_ctl(box); hswep_uncore_sbox_msr_init_box() local 1936 if (msr) { hswep_uncore_sbox_msr_init_box() 1943 wrmsrl(msr, flags); hswep_uncore_sbox_msr_init_box()
H A D	bugs.c	16 #include <asm/msr.h>
H A D	transmeta.c	4 #include <asm/msr.h>
H A D	perf_event_intel_uncore_nhmex.c	206 unsigned msr = uncore_msr_box_ctl(box); nhmex_uncore_msr_disable_box() local 209 if (msr) { nhmex_uncore_msr_disable_box() 210 rdmsrl(msr, config); nhmex_uncore_msr_disable_box() 215 wrmsrl(msr, config); nhmex_uncore_msr_disable_box() 221 unsigned msr = uncore_msr_box_ctl(box); nhmex_uncore_msr_enable_box() local 224 if (msr) { nhmex_uncore_msr_enable_box() 225 rdmsrl(msr, config); nhmex_uncore_msr_enable_box() 230 wrmsrl(msr, config); nhmex_uncore_msr_enable_box() 301 /* msr offset for each instance of cbox */ 764 unsigned msr; nhmex_mbox_hw_config() local 771 for (er = nhmex_uncore_mbox_extra_regs; er->msr; er++) { nhmex_mbox_hw_config() 777 msr = er->msr + type->msr_offset * box->pmu->pmu_idx; nhmex_mbox_hw_config() 778 if (WARN_ON_ONCE(msr >= 0xffff || er->idx >= 0xff)) nhmex_mbox_hw_config() 790 reg1->reg |= msr << (reg_idx * 16); nhmex_mbox_hw_config()
H A D	perf_event_amd_ibs.c	46 unsigned int msr; member in struct:perf_ibs 284 hwc->config_base = perf_ibs->msr; perf_ibs_init() 479 .msr = MSR_AMD64_IBSFETCHCTL, 503 .msr = MSR_AMD64_IBSOPCTL, 526 unsigned int msr; perf_ibs_handle_irq() local 539 msr = hwc->config_base; perf_ibs_handle_irq() 541 rdmsrl(msr, *buf); perf_ibs_handle_irq() 562 rdmsrl(msr + offset, *buf++); perf_ibs_handle_irq() 795 * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
H A D	perf_event.h	19 #define wrmsrl(msr, val) \ 21 unsigned int _msr = (msr); \ 407 unsigned int msr; member in struct:extra_reg 416 .msr = (ms), \ 423 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ 424 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) 426 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ 427 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
H A D	perf_event_intel_rapl.c	334 int bit, msr, ret = 0; rapl_pmu_event_init() local 350 msr = MSR_PP0_ENERGY_STATUS; rapl_pmu_event_init() 354 msr = MSR_PKG_ENERGY_STATUS; rapl_pmu_event_init() 358 msr = MSR_DRAM_ENERGY_STATUS; rapl_pmu_event_init() 362 msr = MSR_PP1_ENERGY_STATUS; rapl_pmu_event_init() 382 event->hw.event_base = msr; rapl_pmu_event_init()
H A D	amd.c	22 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) rdmsrl_amd_safe() argument 30 gprs[1] = msr; rdmsrl_amd_safe() 40 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) wrmsrl_amd_safe() argument 48 gprs[1] = msr; wrmsrl_amd_safe() 577 * bit 6 of msr C001_0015 init_amd_k8()
H A D	centaur.c	7 #include <asm/msr.h>
/linux-4.1.27/arch/arm64/include/asm/
H A D	irqflags.h	31 "msr daifset, #2" arch_local_irq_save() 41 "msr daifclr, #2 // arch_local_irq_enable" arch_local_irq_enable() 50 "msr daifset, #2 // arch_local_irq_disable" arch_local_irq_disable() 56 #define local_fiq_enable() asm("msr daifclr, #1" : : : "memory") 57 #define local_fiq_disable() asm("msr daifset, #1" : : : "memory") 59 #define local_async_enable() asm("msr daifclr, #4" : : : "memory") 60 #define local_async_disable() asm("msr daifset, #4" : : : "memory") 82 "msr daif, %0 // arch_local_irq_restore" arch_local_irq_restore() 101 "msr daifset, #8" \ 109 "msr daif, %0 // local_dbg_restore\n" \ 113 #define local_dbg_enable() asm("msr daifclr, #8" : : : "memory") 114 #define local_dbg_disable() asm("msr daifset, #8" : : : "memory")
H A D	assembler.h	45 msr daifset, #2 49 msr daifclr, #2 61 msr daif, \olddaif 68 msr daifset, #8 72 msr daifclr, #8 79 msr mdscr_el1, \tmp 89 msr mdscr_el1, \tmp 99 msr daifclr, #(8 | 2)
H A D	arch_timer.h	41 asm volatile("msr cntp_ctl_el0, %0" : : "r" (val)); arch_timer_reg_write_cp15() 44 asm volatile("msr cntp_tval_el0, %0" : : "r" (val)); arch_timer_reg_write_cp15() 50 asm volatile("msr cntv_ctl_el0, %0" : : "r" (val)); arch_timer_reg_write_cp15() 53 asm volatile("msr cntv_tval_el0, %0" : : "r" (val)); arch_timer_reg_write_cp15() 105 asm volatile("msr cntkctl_el1, %0" : : "r" (cntkctl)); arch_timer_set_cntkctl()
H A D	fpsimdmacros.h	51 msr fpcr, \state 74 msr fpsr, x\tmpnr 109 msr fpsr, x\tmpnr1
H A D	mmu_context.h	42 " msr contextidr_el1, %0\n" contextidr_thread_switch() 61 " msr ttbr0_el1, %0 // set TTBR0\n" cpu_set_reserved_ttbr0() 88 " msr tcr_el1, %0 ;" __cpu_set_tcr_t0sz()
H A D	hw_breakpoint.h	101 asm volatile("msr dbg" REG #N "_el1, %0" :: "r" (VAL));\
/linux-4.1.27/arch/x86/include/asm/
H A D	msr.h	4 #include <uapi/asm/msr.h> 12 struct msr { struct 24 struct msr reg; 25 struct msr *msrs; 60 static inline unsigned long long native_read_msr(unsigned int msr) native_read_msr() argument 64 asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); native_read_msr() 68 static inline unsigned long long native_read_msr_safe(unsigned int msr, native_read_msr_safe() argument 80 : "c" (msr), [fault] "i" (-EIO)); native_read_msr_safe() 84 static inline void native_write_msr(unsigned int msr, native_write_msr() argument 87 asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); native_write_msr() 91 notrace static inline int native_write_msr_safe(unsigned int msr, native_write_msr_safe() argument 102 : "c" (msr), "0" (low), "d" (high), native_write_msr_safe() 140 #define rdmsr(msr, low, high) \ 142 u64 __val = native_read_msr((msr)); \ 147 static inline void wrmsr(unsigned msr, unsigned low, unsigned high) wrmsr() argument 149 native_write_msr(msr, low, high); wrmsr() 152 #define rdmsrl(msr, val) \ 153 ((val) = native_read_msr((msr))) 155 #define wrmsrl(msr, val) \ 156 native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32)) 159 static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) wrmsr_safe() argument 161 return native_write_msr_safe(msr, low, high); wrmsr_safe() 165 #define rdmsr_safe(msr, low, high) \ 168 u64 __val = native_read_msr_safe((msr), &__err); \ 174 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) rdmsrl_safe() argument 178 *p = native_read_msr_safe(msr, &err); rdmsrl_safe() 208 #define wrmsrl_safe(msr, val) wrmsr_safe((msr), (u32)(val), \ 215 struct msr *msrs_alloc(void); 216 void msrs_free(struct msr *msrs); 217 int msr_set_bit(u32 msr, u8 bit); 218 int msr_clear_bit(u32 msr, u8 bit); 225 void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); 226 void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); 255 struct msr *msrs) rdmsr_on_cpus() 260 struct msr *msrs) wrmsr_on_cpus()
H A D	microcode.h	4 #define native_rdmsr(msr, val1, val2) \ 6 u64 __val = native_read_msr((msr)); \ 11 #define native_wrmsr(msr, low, high) \ 12 native_write_msr(msr, low, high) 14 #define native_wrmsrl(msr, val) \ 15 native_write_msr((msr), \
H A D	paravirt.h	126 static inline u64 paravirt_read_msr(unsigned msr, int *err) paravirt_read_msr() argument 128 return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err); paravirt_read_msr() 131 static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high) paravirt_write_msr() argument 133 return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high); paravirt_write_msr() 137 #define rdmsr(msr, val1, val2) \ 140 u64 _l = paravirt_read_msr(msr, &_err); \ 145 #define wrmsr(msr, val1, val2) \ 147 paravirt_write_msr(msr, val1, val2); \ 150 #define rdmsrl(msr, val) \ 153 val = paravirt_read_msr(msr, &_err); \ 156 #define wrmsrl(msr, val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32) 157 #define wrmsr_safe(msr, a, b) paravirt_write_msr(msr, a, b) 160 #define rdmsr_safe(msr, a, b) \ 163 u64 _l = paravirt_read_msr(msr, &_err); \ 169 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) rdmsrl_safe() argument 173 *p = paravirt_read_msr(msr, &err); rdmsrl_safe()
H A D	apic.h	14 #include <asm/msr.h> 111 u64 msr; apic_is_x2apic_enabled() local 113 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) apic_is_x2apic_enabled() 115 return msr & X2APIC_ENABLE; apic_is_x2apic_enabled() 145 u64 msr; native_apic_msr_read() local 150 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); native_apic_msr_read() 151 return (u32)msr; native_apic_msr_read()
H A D	kvm_host.h	31 #include <asm/msr-index.h> 722 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 942 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); 970 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); 971 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1062 static inline unsigned long read_msr(unsigned long msr) read_msr() argument 1066 rdmsrl(msr, value); read_msr() 1154 void kvm_define_shared_msr(unsigned index, u32 msr); 1177 bool kvm_pmu_msr(struct kvm_vcpu *vcpu, u32 msr); 1178 int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
H A D	perf_event.h	158 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr. 265 unsigned msr; member in struct:perf_guest_switch_msr
/linux-4.1.27/arch/powerpc/include/asm/
H A D	runlatch.h	21 unsigned long msr = mfmsr(); \ 24 if (msr & MSR_EE) \ 33 unsigned long msr = mfmsr(); \ 36 if (msr & MSR_EE) \
H A D	kgdb.h	42 * 32 gpr, 32 fpr, nip, msr, link, ctr 55 /* 32 GPRs (8 bytes), nip, msr, ccr, link, ctr, xer, acc (8 bytes), spefscr*/
H A D	perf_event.h	38 asm volatile("mfmsr %0" : "=r" ((regs)->msr)); \
H A D	probes.h	50 regs->msr |= MSR_SINGLESTEP; enable_single_step() 57 regs->msr &= ~MSR_CE; enable_single_step()
H A D	hw_irq.h	176 unsigned long msr = mfmsr(); arch_local_irq_enable() 177 SET_MSR_EE(msr | MSR_EE); arch_local_irq_enable() 195 return !(regs->msr & MSR_EE); arch_irq_disabled_regs()
H A D	ptrace.h	105 #define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1) 107 #define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
/linux-4.1.27/arch/arm64/kvm/
H A D	hyp.S	76 msr sp_el1, x22 77 msr elr_el1, x23 78 msr spsr_el1, x24 84 msr sp_el0, x19 85 msr elr_el2, x20 // EL1 PC 86 msr spsr_el2, x21 // EL1 pstate 444 msr vmpidr_el2, x4 445 msr csselr_el1, x5 446 msr sctlr_el1, x6 447 msr actlr_el1, x7 448 msr cpacr_el1, x8 449 msr ttbr0_el1, x9 450 msr ttbr1_el1, x10 451 msr tcr_el1, x11 452 msr esr_el1, x12 453 msr afsr0_el1, x13 454 msr afsr1_el1, x14 455 msr far_el1, x15 456 msr mair_el1, x16 457 msr vbar_el1, x17 458 msr contextidr_el1, x18 459 msr tpidr_el0, x19 460 msr tpidrro_el0, x20 461 msr tpidr_el1, x21 462 msr amair_el1, x22 463 msr cntkctl_el1, x23 464 msr par_el1, x24 465 msr mdscr_el1, x25 506 msr dbgbcr15_el1, x20 507 msr dbgbcr14_el1, x19 508 msr dbgbcr13_el1, x18 509 msr dbgbcr12_el1, x17 510 msr dbgbcr11_el1, x16 511 msr dbgbcr10_el1, x15 512 msr dbgbcr9_el1, x14 513 msr dbgbcr8_el1, x13 514 msr dbgbcr7_el1, x12 515 msr dbgbcr6_el1, x11 516 msr dbgbcr5_el1, x10 517 msr dbgbcr4_el1, x9 518 msr dbgbcr3_el1, x8 519 msr dbgbcr2_el1, x7 520 msr dbgbcr1_el1, x6 521 msr dbgbcr0_el1, x5 550 msr dbgbvr15_el1, x20 551 msr dbgbvr14_el1, x19 552 msr dbgbvr13_el1, x18 553 msr dbgbvr12_el1, x17 554 msr dbgbvr11_el1, x16 555 msr dbgbvr10_el1, x15 556 msr dbgbvr9_el1, x14 557 msr dbgbvr8_el1, x13 558 msr dbgbvr7_el1, x12 559 msr dbgbvr6_el1, x11 560 msr dbgbvr5_el1, x10 561 msr dbgbvr4_el1, x9 562 msr dbgbvr3_el1, x8 563 msr dbgbvr2_el1, x7 564 msr dbgbvr1_el1, x6 565 msr dbgbvr0_el1, x5 594 msr dbgwcr15_el1, x20 595 msr dbgwcr14_el1, x19 596 msr dbgwcr13_el1, x18 597 msr dbgwcr12_el1, x17 598 msr dbgwcr11_el1, x16 599 msr dbgwcr10_el1, x15 600 msr dbgwcr9_el1, x14 601 msr dbgwcr8_el1, x13 602 msr dbgwcr7_el1, x12 603 msr dbgwcr6_el1, x11 604 msr dbgwcr5_el1, x10 605 msr dbgwcr4_el1, x9 606 msr dbgwcr3_el1, x8 607 msr dbgwcr2_el1, x7 608 msr dbgwcr1_el1, x6 609 msr dbgwcr0_el1, x5 638 msr dbgwvr15_el1, x20 639 msr dbgwvr14_el1, x19 640 msr dbgwvr13_el1, x18 641 msr dbgwvr12_el1, x17 642 msr dbgwvr11_el1, x16 643 msr dbgwvr10_el1, x15 644 msr dbgwvr9_el1, x14 645 msr dbgwvr8_el1, x13 646 msr dbgwvr7_el1, x12 647 msr dbgwvr6_el1, x11 648 msr dbgwvr5_el1, x10 649 msr dbgwvr4_el1, x9 650 msr dbgwvr3_el1, x8 651 msr dbgwvr2_el1, x7 652 msr dbgwvr1_el1, x6 653 msr dbgwvr0_el1, x5 656 msr mdccint_el1, x21 737 msr spsr_abt, x4 738 msr spsr_und, x5 739 msr spsr_irq, x6 740 msr spsr_fiq, x7 745 msr dacr32_el2, x4 746 msr ifsr32_el2, x5 747 msr fpexc32_el2, x6 751 msr dbgvcr32_el2, x7 757 msr teecr32_el1, x4 758 msr teehbr32_el1, x5 764 msr hcr_el2, x2 766 msr cptr_el2, x2 769 msr hstr_el2, x2 782 msr mdcr_el2, x2 787 msr hcr_el2, x2 788 msr cptr_el2, xzr 789 msr hstr_el2, xzr 793 msr mdcr_el2, x2 800 msr vttbr_el2, x2 804 msr vttbr_el2, xzr 819 msr hcr_el2, x24 830 msr hcr_el2, x24 855 msr cntv_ctl_el0, xzr 860 msr cnthctl_el2, x2 863 msr cntvoff_el2, xzr 873 msr cnthctl_el2, x2 881 msr cntvoff_el2, x3 883 msr cntv_cval_el0, x2 888 msr cntv_ctl_el0, x2 929 msr tpidr_el2, x0 // Save the vcpu register 1013 msr vttbr_el2, x2 1034 msr vttbr_el2, xzr 1049 msr vttbr_el2, x2 1056 msr vttbr_el2, xzr 1106 msr spsr_el2, lr 1108 msr elr_el2, lr 1241 msr par_el1, x0
H A D	hyp-init.S	62 msr ttbr0_el2, x0 88 msr tcr_el2, x4 97 msr vtcr_el2, x4 100 msr mair_el2, x4 111 msr sctlr_el2, x4 125 msr ttbr0_el2, x1 137 msr vbar_el2, x3
/linux-4.1.27/arch/microblaze/kernel/
H A D	process.c	43 pr_info(" msr=%08lX, ear=%08lX, esr=%08lX, fsr=%08lX\n", show_regs() 44 regs->msr, regs->ear, regs->esr, regs->fsr); show_regs() 69 local_save_flags(childregs->msr); copy_thread() 71 ti->cpu_context.msr = childregs->msr & ~MSR_IE; copy_thread() 83 ti->cpu_context.msr = (unsigned long)childregs->msr; copy_thread() 85 childregs->msr |= MSR_UMS; copy_thread() 97 childregs->msr &= ~MSR_EIP; copy_thread() 98 childregs->msr |= MSR_IE; copy_thread() 99 childregs->msr &= ~MSR_VM; copy_thread() 100 childregs->msr |= MSR_VMS; copy_thread() 101 childregs->msr |= MSR_EE; /* exceptions will be enabled*/ copy_thread() 103 ti->cpu_context.msr = (childregs->msr|MSR_VM); copy_thread() 104 ti->cpu_context.msr &= ~MSR_UMS; /* switch_to to kernel mode */ copy_thread() 105 ti->cpu_context.msr &= ~MSR_IE; copy_thread() 149 regs->msr |= MSR_UMS; start_thread() 150 regs->msr &= ~MSR_VM; start_thread()
H A D	setup.c	100 unsigned int fdt, unsigned int msr, unsigned int tlb0, machine_early_init() 167 if (msr) { machine_early_init() 169 pr_cont("CPU don't have it %x\n", msr); machine_early_init() 172 if (!msr) { machine_early_init() 174 pr_cont("CPU have it %x\n", msr); machine_early_init() 99 machine_early_init(const char *cmdline, unsigned int ram, unsigned int fdt, unsigned int msr, unsigned int tlb0, unsigned int tlb1) machine_early_init() argument
H A D	kgdb.c	43 /* registers r0 - r31, pc, msr, ear, esr, fsr + do not save pt_mode */ pt_regs_to_gdb_regs() 99 /* registers r0 - r31, pc, msr, ear, esr, fsr + do not save pt_mode */ sleeping_thread_to_gdb_regs()
H A D	asm-offsets.c	25 DEFINE(PT_MSR, offsetof(struct pt_regs, msr)); main() 121 DEFINE(CC_MSR, offsetof(struct cpu_context, msr)); main()
H A D	head.S	75 * r8 == 0 - msr instructions are implemented 76 * r8 != 0 - msr instructions are not implemented 79 msrclr r8, 0 /* clear nothing - just read msr for test */ 80 cmpu r8, r8, r1 /* r1 must contain msr reg content */
/linux-4.1.27/arch/x86/include/uapi/asm/
H A D	msr.h	4 #include <asm/msr-index.h>
H A D	svm.h	116 { SVM_EXIT_MSR, "msr" }, \
H A D	processor-flags.h	130 * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
/linux-4.1.27/arch/x86/kernel/
H A D	trace_clock.c	6 #include <asm/msr.h>
H A D	msr.c	21 * This driver uses /dev/cpu/%d/msr where %d is the minor number, and on 44 #include <asm/msr.h> 210 "msr%d", cpu); msr_device_create() 244 return kasprintf(GFP_KERNEL, "cpu/%u/msr", MINOR(dev->devt)); msr_devnode() 252 if (__register_chrdev(MSR_MAJOR, 0, NR_CPUS, "cpu/msr", &msr_fops)) { msr_init() 253 pr_err("unable to get major %d for msr\n", MSR_MAJOR); msr_init() 257 msr_class = class_create(THIS_MODULE, "msr"); msr_init() 283 __unregister_chrdev(MSR_MAJOR, 0, NR_CPUS, "cpu/msr"); 296 __unregister_chrdev(MSR_MAJOR, 0, NR_CPUS, "cpu/msr"); msr_exit()
H A D	amd_nb.c	143 u64 base, msr; amd_get_mmconfig_range() local 154 rdmsrl(address, msr); amd_get_mmconfig_range() 157 if (!(msr & FAM10H_MMIO_CONF_ENABLE)) amd_get_mmconfig_range() 160 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); amd_get_mmconfig_range() 162 segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & amd_get_mmconfig_range()
H A D	reboot_fixups_32.c	14 #include <asm/msr.h>
H A D	kvmclock.c	22 #include <asm/msr.h> 168 printk(KERN_INFO "kvm-clock: cpu %d, msr %x:%x, %s\n", kvm_register_clock() 200 * that does not have the 'enable' bit set in the msr
H A D	Makefile	58 obj-$(CONFIG_X86_MSR) += msr.o
H A D	cpuid.c	45 #include <asm/msr.h>
H A D	mmconf-fam10h_64.c	15 #include <asm/msr.h>
H A D	verify_cpu.S	34 #include <asm/msr-index.h>
/linux-4.1.27/tools/power/cpupower/debug/i386/
H A D	centrino-decode.c	29 static int rdmsr(unsigned int cpu, unsigned int msr, rdmsr() argument 42 sprintf(file, "/dev/cpu/%d/msr", cpu); rdmsr() 48 if (lseek(fd, msr, SEEK_CUR) == -1) rdmsr() 64 static void decode (unsigned int msr) decode() argument 69 multiplier = ((msr >> 8) & 0xFF); decode() 71 mv = (((msr & 0xFF) * 16) + 700); decode() 73 printf("0x%x means multiplier %d @ %d mV\n", msr, multiplier, mv); decode() 86 printf("or you are not root, or the msr driver is not present\n"); decode_live()
H A D	powernow-k8-decode.c	31 uint64_t msr = 0; get_fidvid() local 38 sprintf(file, "/dev/cpu/%d/msr", cpu); get_fidvid() 44 if (read(fd, &msr, 8) != 8) get_fidvid() 47 *fid = ((uint32_t )(msr & 0xffffffffull)) & MSR_S_LO_CURRENT_FID; get_fidvid() 48 *vid = ((uint32_t )(msr>>32 & 0xffffffffull)) & MSR_S_HI_CURRENT_VID; get_fidvid() 85 printf("or you are not root, or the msr driver is not present\n"); main()
/linux-4.1.27/tools/power/x86/turbostat/
H A D	turbostat.c	261 int get_msr(int cpu, off_t offset, unsigned long long *msr) get_msr() argument 267 sprintf(pathname, "/dev/cpu/%d/msr", cpu); get_msr() 270 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); get_msr() 272 retval = pread(fd, msr, sizeof *msr, offset); get_msr() 275 if (retval != sizeof *msr) get_msr() 525 /* msr */ format_counters() 973 unsigned long long msr; get_counters() local 990 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) get_counters() 992 t->smi_count = msr & 0xFFFFFFFF; get_counters() 995 if (get_msr(cpu, extra_delta_offset32, &msr)) get_counters() 997 t->extra_delta32 = msr & 0xFFFFFFFF; get_counters() 1005 if (get_msr(cpu, extra_msr_offset32, &msr)) get_counters() 1007 t->extra_msr32 = msr & 0xFFFFFFFF; get_counters() 1041 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) get_counters() 1043 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); get_counters() 1082 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) get_counters() 1084 p->energy_pkg = msr & 0xFFFFFFFF; get_counters() 1087 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) get_counters() 1089 p->energy_cores = msr & 0xFFFFFFFF; get_counters() 1092 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) get_counters() 1094 p->energy_dram = msr & 0xFFFFFFFF; get_counters() 1097 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) get_counters() 1099 p->energy_gfx = msr & 0xFFFFFFFF; get_counters() 1102 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) get_counters() 1104 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; get_counters() 1107 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) get_counters() 1109 p->rapl_dram_perf_status = msr & 0xFFFFFFFF; get_counters() 1112 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) get_counters() 1114 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); get_counters() 1155 unsigned long long msr; dump_nhm_platform_info() local 1158 get_msr(base_cpu, MSR_NHM_PLATFORM_INFO, &msr); dump_nhm_platform_info() 1160 fprintf(stderr, "cpu0: MSR_NHM_PLATFORM_INFO: 0x%08llx\n", msr); dump_nhm_platform_info() 1162 ratio = (msr >> 40) & 0xFF; dump_nhm_platform_info() 1166 ratio = (msr >> 8) & 0xFF; dump_nhm_platform_info() 1170 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); dump_nhm_platform_info() 1172 msr, msr & 0x2 ? "EN" : "DIS"); dump_nhm_platform_info() 1180 unsigned long long msr; dump_hsw_turbo_ratio_limits() local 1183 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); dump_hsw_turbo_ratio_limits() 1185 fprintf(stderr, "cpu0: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", msr); dump_hsw_turbo_ratio_limits() 1187 ratio = (msr >> 8) & 0xFF; dump_hsw_turbo_ratio_limits() 1192 ratio = (msr >> 0) & 0xFF; dump_hsw_turbo_ratio_limits() 1202 unsigned long long msr; dump_ivt_turbo_ratio_limits() local 1205 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); dump_ivt_turbo_ratio_limits() 1207 fprintf(stderr, "cpu0: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", msr); dump_ivt_turbo_ratio_limits() 1209 ratio = (msr >> 56) & 0xFF; dump_ivt_turbo_ratio_limits() 1214 ratio = (msr >> 48) & 0xFF; dump_ivt_turbo_ratio_limits() 1219 ratio = (msr >> 40) & 0xFF; dump_ivt_turbo_ratio_limits() 1224 ratio = (msr >> 32) & 0xFF; dump_ivt_turbo_ratio_limits() 1229 ratio = (msr >> 24) & 0xFF; dump_ivt_turbo_ratio_limits() 1234 ratio = (msr >> 16) & 0xFF; dump_ivt_turbo_ratio_limits() 1239 ratio = (msr >> 8) & 0xFF; dump_ivt_turbo_ratio_limits() 1244 ratio = (msr >> 0) & 0xFF; dump_ivt_turbo_ratio_limits() 1254 unsigned long long msr; dump_nhm_turbo_ratio_limits() local 1257 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); dump_nhm_turbo_ratio_limits() 1259 fprintf(stderr, "cpu0: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", msr); dump_nhm_turbo_ratio_limits() 1261 ratio = (msr >> 56) & 0xFF; dump_nhm_turbo_ratio_limits() 1266 ratio = (msr >> 48) & 0xFF; dump_nhm_turbo_ratio_limits() 1271 ratio = (msr >> 40) & 0xFF; dump_nhm_turbo_ratio_limits() 1276 ratio = (msr >> 32) & 0xFF; dump_nhm_turbo_ratio_limits() 1281 ratio = (msr >> 24) & 0xFF; dump_nhm_turbo_ratio_limits() 1286 ratio = (msr >> 16) & 0xFF; dump_nhm_turbo_ratio_limits() 1291 ratio = (msr >> 8) & 0xFF; dump_nhm_turbo_ratio_limits() 1296 ratio = (msr >> 0) & 0xFF; dump_nhm_turbo_ratio_limits() 1308 unsigned long long msr; dump_knl_turbo_ratio_limits() local 1313 get_msr(base_cpu, MSR_NHM_TURBO_RATIO_LIMIT, &msr); dump_knl_turbo_ratio_limits() 1316 msr); dump_knl_turbo_ratio_limits() 1339 cores = msr & 0xFF; dump_knl_turbo_ratio_limits() 1340 ratio = (msr >> 8) && 0xFF; dump_knl_turbo_ratio_limits() 1347 delta_cores = (msr >> i) & 0x1F; dump_knl_turbo_ratio_limits() 1348 delta_ratio = (msr >> (i + 5)) && 0x7; dump_knl_turbo_ratio_limits() 1367 unsigned long long msr; dump_nhm_cst_cfg() local 1369 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); dump_nhm_cst_cfg() 1374 fprintf(stderr, "cpu0: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x%08llx", msr); dump_nhm_cst_cfg() 1377 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", dump_nhm_cst_cfg() 1378 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", dump_nhm_cst_cfg() 1379 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", dump_nhm_cst_cfg() 1380 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", dump_nhm_cst_cfg() 1381 (msr & (1 << 15)) ? "" : "UN", dump_nhm_cst_cfg() 1382 (unsigned int)msr & 7, dump_nhm_cst_cfg() 1700 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); check_dev_msr() 1702 if (system("/sbin/modprobe msr > /dev/null 2>&1")) check_dev_msr() 1703 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); check_dev_msr() 1729 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); check_permissions() 1732 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); check_permissions() 1762 unsigned long long msr; probe_nhm_msrs() local 1812 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); probe_nhm_msrs() 1814 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; probe_nhm_msrs() 1906 unsigned long long msr; print_epb() local 1924 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) print_epb() 1927 switch (msr & 0xF) { print_epb() 1941 fprintf(stderr, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); print_epb() 1951 unsigned long long msr; print_perf_limit() local 1966 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); print_perf_limit() 1967 fprintf(stderr, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); print_perf_limit() 1969 (msr & 1 << 15) ? "bit15, " : "", print_perf_limit() 1970 (msr & 1 << 14) ? "bit14, " : "", print_perf_limit() 1971 (msr & 1 << 13) ? "Transitions, " : "", print_perf_limit() 1972 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", print_perf_limit() 1973 (msr & 1 << 11) ? "PkgPwrL2, " : "", print_perf_limit() 1974 (msr & 1 << 10) ? "PkgPwrL1, " : "", print_perf_limit() 1975 (msr & 1 << 9) ? "CorePwr, " : "", print_perf_limit() 1976 (msr & 1 << 8) ? "Amps, " : "", print_perf_limit() 1977 (msr & 1 << 6) ? "VR-Therm, " : "", print_perf_limit() 1978 (msr & 1 << 5) ? "Auto-HWP, " : "", print_perf_limit() 1979 (msr & 1 << 4) ? "Graphics, " : "", print_perf_limit() 1980 (msr & 1 << 2) ? "bit2, " : "", print_perf_limit() 1981 (msr & 1 << 1) ? "ThermStatus, " : "", print_perf_limit() 1982 (msr & 1 << 0) ? "PROCHOT, " : ""); print_perf_limit() 1984 (msr & 1 << 31) ? "bit31, " : "", print_perf_limit() 1985 (msr & 1 << 30) ? "bit30, " : "", print_perf_limit() 1986 (msr & 1 << 29) ? "Transitions, " : "", print_perf_limit() 1987 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", print_perf_limit() 1988 (msr & 1 << 27) ? "PkgPwrL2, " : "", print_perf_limit() 1989 (msr & 1 << 26) ? "PkgPwrL1, " : "", print_perf_limit() 1990 (msr & 1 << 25) ? "CorePwr, " : "", print_perf_limit() 1991 (msr & 1 << 24) ? "Amps, " : "", print_perf_limit() 1992 (msr & 1 << 22) ? "VR-Therm, " : "", print_perf_limit() 1993 (msr & 1 << 21) ? "Auto-HWP, " : "", print_perf_limit() 1994 (msr & 1 << 20) ? "Graphics, " : "", print_perf_limit() 1995 (msr & 1 << 18) ? "bit18, " : "", print_perf_limit() 1996 (msr & 1 << 17) ? "ThermStatus, " : "", print_perf_limit() 1997 (msr & 1 << 16) ? "PROCHOT, " : ""); print_perf_limit() 2001 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); print_perf_limit() 2002 fprintf(stderr, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); print_perf_limit() 2004 (msr & 1 << 0) ? "PROCHOT, " : "", print_perf_limit() 2005 (msr & 1 << 1) ? "ThermStatus, " : "", print_perf_limit() 2006 (msr & 1 << 4) ? "Graphics, " : "", print_perf_limit() 2007 (msr & 1 << 6) ? "VR-Therm, " : "", print_perf_limit() 2008 (msr & 1 << 8) ? "Amps, " : "", print_perf_limit() 2009 (msr & 1 << 9) ? "GFXPwr, " : "", print_perf_limit() 2010 (msr & 1 << 10) ? "PkgPwrL1, " : "", print_perf_limit() 2011 (msr & 1 << 11) ? "PkgPwrL2, " : ""); print_perf_limit() 2013 (msr & 1 << 16) ? "PROCHOT, " : "", print_perf_limit() 2014 (msr & 1 << 17) ? "ThermStatus, " : "", print_perf_limit() 2015 (msr & 1 << 20) ? "Graphics, " : "", print_perf_limit() 2016 (msr & 1 << 22) ? "VR-Therm, " : "", print_perf_limit() 2017 (msr & 1 << 24) ? "Amps, " : "", print_perf_limit() 2018 (msr & 1 << 25) ? "GFXPwr, " : "", print_perf_limit() 2019 (msr & 1 << 26) ? "PkgPwrL1, " : "", print_perf_limit() 2020 (msr & 1 << 27) ? "PkgPwrL2, " : ""); print_perf_limit() 2023 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); print_perf_limit() 2024 fprintf(stderr, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); print_perf_limit() 2026 (msr & 1 << 0) ? "PROCHOT, " : "", print_perf_limit() 2027 (msr & 1 << 1) ? "ThermStatus, " : "", print_perf_limit() 2028 (msr & 1 << 6) ? "VR-Therm, " : "", print_perf_limit() 2029 (msr & 1 << 8) ? "Amps, " : "", print_perf_limit() 2030 (msr & 1 << 10) ? "PkgPwrL1, " : "", print_perf_limit() 2031 (msr & 1 << 11) ? "PkgPwrL2, " : ""); print_perf_limit() 2033 (msr & 1 << 16) ? "PROCHOT, " : "", print_perf_limit() 2034 (msr & 1 << 17) ? "ThermStatus, " : "", print_perf_limit() 2035 (msr & 1 << 22) ? "VR-Therm, " : "", print_perf_limit() 2036 (msr & 1 << 24) ? "Amps, " : "", print_perf_limit() 2037 (msr & 1 << 26) ? "PkgPwrL1, " : "", print_perf_limit() 2038 (msr & 1 << 27) ? "PkgPwrL2, " : ""); print_perf_limit() 2048 unsigned long long msr; get_tdp() local 2051 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) get_tdp() 2052 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; get_tdp() 2091 unsigned long long msr; rapl_probe() local 2134 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) rapl_probe() 2137 rapl_power_units = 1.0 / (1 << (msr & 0xF)); rapl_probe() 2139 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; rapl_probe() 2141 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); rapl_probe() 2145 time_unit = msr >> 16 & 0xF; rapl_probe() 2183 unsigned long long msr; print_thermal() local 2202 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) print_thermal() 2205 dts = (msr >> 16) & 0x7F; print_thermal() 2207 cpu, msr, tcc_activation_temp - dts); print_thermal() 2210 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) print_thermal() 2213 dts = (msr >> 16) & 0x7F; print_thermal() 2214 dts2 = (msr >> 8) & 0x7F; print_thermal() 2216 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); print_thermal() 2224 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) print_thermal() 2227 dts = (msr >> 16) & 0x7F; print_thermal() 2228 resolution = (msr >> 27) & 0xF; print_thermal() 2230 cpu, msr, tcc_activation_temp - dts, resolution); print_thermal() 2233 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) print_thermal() 2236 dts = (msr >> 16) & 0x7F; print_thermal() 2237 dts2 = (msr >> 8) & 0x7F; print_thermal() 2239 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); print_thermal() 2246 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) print_power_limit_msr() argument 2250 ((msr >> 15) & 1) ? "EN" : "DIS", print_power_limit_msr() 2251 ((msr >> 0) & 0x7FFF) * rapl_power_units, print_power_limit_msr() 2252 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, print_power_limit_msr() 2253 (((msr >> 16) & 1) ? "EN" : "DIS")); print_power_limit_msr() 2260 unsigned long long msr; print_rapl() local 2276 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) print_rapl() 2281 "(%f Watts, %f Joules, %f sec.)\n", cpu, msr, print_rapl() 2286 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) print_rapl() 2291 cpu, msr, print_rapl() 2292 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, print_rapl() 2293 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, print_rapl() 2294 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, print_rapl() 2295 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); print_rapl() 2300 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) print_rapl() 2304 cpu, msr, (msr >> 63) & 1 ? "": "UN"); print_rapl() 2306 print_power_limit_msr(cpu, msr, "PKG Limit #1"); print_rapl() 2309 ((msr >> 47) & 1) ? "EN" : "DIS", print_rapl() 2310 ((msr >> 32) & 0x7FFF) * rapl_power_units, print_rapl() 2311 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, print_rapl() 2312 ((msr >> 48) & 1) ? "EN" : "DIS"); print_rapl() 2316 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) print_rapl() 2320 cpu, msr, print_rapl() 2321 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, print_rapl() 2322 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, print_rapl() 2323 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, print_rapl() 2324 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); print_rapl() 2327 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) print_rapl() 2330 cpu, msr, (msr >> 31) & 1 ? "": "UN"); print_rapl() 2332 print_power_limit_msr(cpu, msr, "DRAM Limit"); print_rapl() 2336 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) print_rapl() 2339 fprintf(stderr, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); print_rapl() 2345 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) print_rapl() 2348 cpu, msr, (msr >> 31) & 1 ? "": "UN"); print_rapl() 2349 print_power_limit_msr(cpu, msr, "Cores Limit"); print_rapl() 2354 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) print_rapl() 2357 fprintf(stderr, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); print_rapl() 2359 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) print_rapl() 2362 cpu, msr, (msr >> 31) & 1 ? "": "UN"); print_rapl() 2363 print_power_limit_msr(cpu, msr, "GFX Limit"); print_rapl() 2475 unsigned long long msr = 3; slm_bclk() local 2479 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) slm_bclk() 2482 i = msr & 0xf; slm_bclk() 2485 msr = 3; slm_bclk() 2518 unsigned long long msr; set_temperature_target() local 2547 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) set_temperature_target() 2550 target_c_local = (msr >> 16) & 0xFF; set_temperature_target() 2554 cpu, msr, target_c_local); set_temperature_target() 2704 "--counter msr print 32-bit counter at address \"msr\"\n" help() 2705 "--Counter msr print 64-bit Counter at address \"msr\"\n" help() 2706 "--msr msr print 32-bit value at address \"msr\"\n" help() 2707 "--MSR msr print 64-bit Value at address \"msr\"\n" help() 3034 {"msr", required_argument, 0, 'm'}, cmdline()
H A D	Makefile	12 CFLAGS += -DMSRHEADER='"../../../../arch/x86/include/uapi/asm/msr-index.h"'
/linux-4.1.27/arch/m68k/bvme6000/
H A D	config.c	164 unsigned char msr = rtc->msr & 0xc0; bvme6000_timer_int() local 166 rtc->msr = msr | 0x20; /* Ack the interrupt */ bvme6000_timer_int() 183 unsigned char msr = rtc->msr & 0xc0; bvme6000_sched_init() local 185 rtc->msr = 0; /* Ensure timer registers accessible */ bvme6000_sched_init() 196 rtc->msr = 0x40; /* Access int.cntrl, etc */ bvme6000_sched_init() 201 rtc->msr = 0; /* Access timer 1 control */ bvme6000_sched_init() 204 rtc->msr = msr; bvme6000_sched_init() 225 unsigned char msr = rtc->msr & 0xc0; bvme6000_gettimeoffset() local 229 rtc->msr = 0; /* Ensure timer registers accessible */ bvme6000_gettimeoffset() 233 t1int = rtc->msr & 0x20; bvme6000_gettimeoffset() 238 } while (t1int != (rtc->msr & 0x20) || bvme6000_gettimeoffset() 249 rtc->msr = msr; bvme6000_gettimeoffset() 272 unsigned char msr = rtc->msr & 0xc0; bvme6000_hwclk() local 274 rtc->msr = 0x40; /* Ensure clock and real-time-mode-register bvme6000_hwclk() 305 rtc->msr = msr; bvme6000_hwclk() 323 unsigned char msr = rtc->msr & 0xc0; bvme6000_set_clock_mmss() local 327 rtc->msr = 0; /* Ensure clock accessible */ bvme6000_set_clock_mmss() 347 rtc->msr = msr; bvme6000_set_clock_mmss()
H A D	rtc.c	41 unsigned char msr; rtc_ioctl() local 51 msr = rtc->msr & 0xc0; rtc_ioctl() 52 rtc->msr = 0x40; rtc_ioctl() 65 rtc->msr = msr; rtc_ioctl() 107 msr = rtc->msr & 0xc0; rtc_ioctl() 108 rtc->msr = 0x40; rtc_ioctl() 122 rtc->msr = msr; rtc_ioctl()
/linux-4.1.27/arch/arm/include/asm/
H A D	irqflags.h	66 " msr cpsr_c, %1" arch_local_irq_save() 82 " msr cpsr_c, %0" arch_local_irq_enable() 97 " msr cpsr_c, %0" arch_local_irq_disable() 112 " msr cpsr_c, %0" \ 127 " msr cpsr_c, %0" \ 153 " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore" arch_local_irq_restore()
H A D	assembler.h	103 msr cpsr_c, #PSR_I_BIT | SVC_MODE 107 msr cpsr_c, #SVC_MODE 168 msr primask, \oldcpsr 170 msr cpsr_c, \oldcpsr 304 msr cpsr_c, \reg 308 msr cpsr_c, #\mode 330 msr spsr_cxsf, \reg 333 1: msr cpsr_c, \reg
/linux-4.1.27/arch/arm64/mm/
H A D	proc.S	56 msr sctlr_el1, x0 74 msr sctlr_el1, x1 // disable the MMU 152 msr tpidr_el0, x2 153 msr tpidrro_el0, x3 154 msr contextidr_el1, x4 155 msr mair_el1, x5 156 msr cpacr_el1, x6 157 msr ttbr0_el1, x1 158 msr ttbr1_el1, x7 160 msr tcr_el1, x8 161 msr vbar_el1, x9 162 msr mdscr_el1, x10 167 msr oslar_el1, x11 186 msr ttbr0_el1, x0 // set TTBR0 205 msr cpacr_el1, x0 // Enable FP/ASIMD 207 msr mdscr_el1, x0 // access to the DCC from EL0 225 msr mair_el1, x5 248 msr tcr_el1, x10
H A D	cache.S	50 msr csselr_el1, x10 // select current cache level in csselr 79 msr csselr_el1, x10 // select current cache level in csselr
/linux-4.1.27/arch/powerpc/kernel/
H A D	signal_64.c	95 unsigned long msr = regs->msr; setup_sigcontext() local 110 msr |= MSR_VEC; setup_sigcontext() 129 msr &= ~MSR_VSX; setup_sigcontext() 143 msr |= MSR_VSX; setup_sigcontext() 149 err |= __put_user(msr, &sc->gp_regs[PT_MSR]); setup_sigcontext() 189 unsigned long msr = regs->msr; setup_tm_sigcontexts() local 192 BUG_ON(!MSR_TM_ACTIVE(regs->msr)); setup_tm_sigcontexts() 199 regs->msr &= ~MSR_TS_MASK; setup_tm_sigcontexts() 216 if (msr & MSR_VEC) setup_tm_sigcontexts() 228 msr |= MSR_VEC; setup_tm_sigcontexts() 236 if (msr & MSR_VEC) setup_tm_sigcontexts() 250 if (msr & MSR_FP) setup_tm_sigcontexts() 268 if (msr & MSR_VSX) setup_tm_sigcontexts() 276 msr |= MSR_VSX; setup_tm_sigcontexts() 286 err |= __put_user(msr, &tm_sc->gp_regs[PT_MSR]); setup_tm_sigcontexts() 287 err |= __put_user(msr, &sc->gp_regs[PT_MSR]); setup_tm_sigcontexts() 309 unsigned long msr; restore_sigcontext() local 322 err |= __get_user(msr, &sc->gp_regs[PT_MSR]); restore_sigcontext() 324 regs->msr = (regs->msr & ~MSR_LE) | (msr & MSR_LE); restore_sigcontext() 355 regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1 | MSR_VEC | MSR_VSX); restore_sigcontext() 364 if (v_regs != NULL && (msr & MSR_VEC) != 0) restore_sigcontext() 386 if ((msr & MSR_VSX) != 0) restore_sigcontext() 408 unsigned long msr; restore_tm_sigcontexts() local 429 err |= __get_user(msr, &sc->gp_regs[PT_MSR]); restore_tm_sigcontexts() 431 if (MSR_TM_RESV(msr)) restore_tm_sigcontexts() 435 regs->msr = (regs->msr & ~MSR_TS_MASK) | (msr & MSR_TS_MASK); restore_tm_sigcontexts() 438 regs->msr = (regs->msr & ~MSR_LE) | (msr & MSR_LE); restore_tm_sigcontexts() 474 regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1 | MSR_VEC | MSR_VSX); restore_tm_sigcontexts() 487 if (v_regs != NULL && tm_v_regs != NULL && (msr & MSR_VEC) != 0) { restore_tm_sigcontexts() 520 if (v_regs && ((msr & MSR_VSX) != 0)) { restore_tm_sigcontexts() 536 tm_recheckpoint(&current->thread, msr); restore_tm_sigcontexts() 539 if (msr & MSR_FP) { restore_tm_sigcontexts() 541 regs->msr |= (MSR_FP | current->thread.fpexc_mode); restore_tm_sigcontexts() 544 if (msr & MSR_VEC) { restore_tm_sigcontexts() 546 regs->msr |= MSR_VEC; restore_tm_sigcontexts() 669 unsigned long msr; sys_rt_sigreturn() local 682 if (__get_user(msr, &uc->uc_mcontext.gp_regs[PT_MSR])) sys_rt_sigreturn() 684 if (MSR_TM_ACTIVE(msr)) { sys_rt_sigreturn() 707 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, sys_rt_sigreturn() 735 if (MSR_TM_ACTIVE(regs->msr)) { handle_rt_signal64() 792 regs->msr &= ~MSR_LE; handle_rt_signal64() 793 regs->msr |= (MSR_KERNEL & MSR_LE); handle_rt_signal64() 811 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, handle_rt_signal64()
H A D	process.c	87 MSR_TM_ACTIVE(tsk->thread.regs->msr) && giveup_fpu_maybe_transactional() 89 tsk->thread.tm_orig_msr = tsk->thread.regs->msr; giveup_fpu_maybe_transactional() 105 MSR_TM_ACTIVE(tsk->thread.regs->msr) && giveup_altivec_maybe_transactional() 107 tsk->thread.tm_orig_msr = tsk->thread.regs->msr; giveup_altivec_maybe_transactional() 129 * another process could get scheduled after the regs->msr flush_fp_to_thread() 136 if (tsk->thread.regs->msr & MSR_FP) { flush_fp_to_thread() 160 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) enable_kernel_fp() 176 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) enable_kernel_altivec() 194 if (tsk->thread.regs->msr & MSR_VEC) { flush_altivec_to_thread() 212 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) enable_kernel_vsx() 234 if (tsk->thread.regs->msr & MSR_VSX) { flush_vsx_to_thread() 253 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) enable_kernel_spe() 267 if (tsk->thread.regs->msr & MSR_SPE) { flush_spe_to_thread() 543 msr_diff = thr->tm_orig_msr & ~thr->regs->msr; tm_reclaim_thread() 572 tm_reclaim(thr, thr->regs->msr, cause); tm_reclaim_thread() 577 * flush_fp_to_thread(), so update thr->regs->msr to tm_reclaim_thread() 580 thr->regs->msr |= msr_diff; tm_reclaim_thread() 606 if (!MSR_TM_ACTIVE(thr->regs->msr)) tm_reclaim_task() 615 thr->tm_orig_msr = thr->regs->msr; tm_reclaim_task() 618 "ccr=%lx, msr=%lx, trap=%lx)\n", tm_reclaim_task() 620 thr->regs->ccr, thr->regs->msr, tm_reclaim_task() 664 unsigned long msr; tm_recheckpoint_new_task() local 680 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ tm_recheckpoint_new_task() 684 msr = new->thread.tm_orig_msr; tm_recheckpoint_new_task() 687 "(new->msr 0x%lx, new->origmsr 0x%lx)\n", tm_recheckpoint_new_task() 688 new->pid, new->thread.regs->msr, msr); tm_recheckpoint_new_task() 691 tm_recheckpoint(&new->thread, msr); tm_recheckpoint_new_task() 694 if (msr & MSR_FP) { tm_recheckpoint_new_task() 696 new->thread.regs->msr |= tm_recheckpoint_new_task() 700 if (msr & MSR_VEC) { tm_recheckpoint_new_task() 702 new->thread.regs->msr |= MSR_VEC; tm_recheckpoint_new_task() 706 if (msr & MSR_VSX) tm_recheckpoint_new_task() 707 new->thread.regs->msr |= MSR_VSX; tm_recheckpoint_new_task() 710 "(kernel msr 0x%lx)\n", tm_recheckpoint_new_task() 741 if (!MSR_TM_ACTIVE(regs->msr)) restore_tm_state() 744 msr_diff = current->thread.tm_orig_msr & ~regs->msr; restore_tm_state() 749 regs->msr |= current->thread.fpexc_mode; restore_tm_state() 755 regs->msr |= msr_diff; restore_tm_state() 796 if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP)) __switch_to() 810 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC)) __switch_to() 814 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX)) __switch_to() 826 if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE))) __switch_to() 836 new->thread.regs->msr |= MSR_VEC; __switch_to() 840 new->thread.regs->msr |= MSR_VSX; __switch_to() 847 new->thread.regs->msr |= MSR_SPE; __switch_to() 935 if (!(regs->msr & MSR_IR)) show_instructions() 1021 printk("MSR: "REG" ", regs->msr); show_regs() 1022 printbits(regs->msr, msr_bits); show_regs() 1037 if (MSR_TM_ACTIVE(regs->msr)) show_regs() 1260 regs->msr = MSR_USER; start_thread() 1302 regs->msr = MSR_USER64; start_thread() 1306 regs->msr = MSR_USER32; start_thread() 1330 regs->msr |= MSR_TM; start_thread() 1384 if (regs != NULL && (regs->msr & MSR_FP) != 0) set_fpexc_mode() 1385 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) set_fpexc_mode() 1433 regs->msr &= ~MSR_LE; set_endian() 1435 regs->msr |= MSR_LE; set_endian() 1454 if (regs->msr & MSR_LE) { get_endian()
H A D	signal_32.c	412 unsigned long msr = regs->msr; save_user_regs() local 430 msr |= MSR_VEC; save_user_regs() 432 /* else assert((regs->msr & MSR_VEC) == 0) */ save_user_regs() 452 msr &= ~MSR_VSX; save_user_regs() 464 msr |= MSR_VSX; save_user_regs() 476 msr |= MSR_SPE; save_user_regs() 478 /* else assert((regs->msr & MSR_SPE) == 0) */ save_user_regs() 485 if (__put_user(msr, &frame->mc_gregs[PT_MSR])) save_user_regs() 519 unsigned long msr = regs->msr; save_tm_user_regs() local 526 regs->msr &= ~MSR_TS_MASK; save_tm_user_regs() 542 if (__put_user((msr >> 32), &tm_frame->mc_gregs[PT_MSR])) save_tm_user_regs() 552 if (msr & MSR_VEC) { save_tm_user_regs() 567 msr |= MSR_VEC; save_tm_user_regs() 580 if (msr & MSR_VEC) { save_tm_user_regs() 593 if (msr & MSR_FP) { save_tm_user_regs() 612 if (msr & MSR_VSX) { save_tm_user_regs() 621 msr |= MSR_VSX; save_tm_user_regs() 635 msr |= MSR_SPE; save_tm_user_regs() 643 if (__put_user(msr, &frame->mc_gregs[PT_MSR])) save_tm_user_regs() 667 unsigned long msr; restore_user_regs() local 680 err |= __get_user(msr, &sr->mc_gregs[PT_MSR]); restore_user_regs() 688 regs->msr = (regs->msr & ~MSR_LE) | (msr & MSR_LE); restore_user_regs() 704 regs->msr &= ~MSR_VEC; restore_user_regs() 705 if (msr & MSR_VEC) { restore_user_regs() 728 regs->msr &= ~MSR_VSX; restore_user_regs() 729 if (msr & MSR_VSX) { restore_user_regs() 744 regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1); restore_user_regs() 749 regs->msr &= ~MSR_SPE; restore_user_regs() 750 if (msr & MSR_SPE) { restore_user_regs() 777 unsigned long msr, msr_hi; restore_tm_user_regs() local 794 err |= __get_user(msr, &sr->mc_gregs[PT_MSR]); restore_tm_user_regs() 799 regs->msr = (regs->msr & ~MSR_LE) | (msr & MSR_LE); restore_tm_user_regs() 811 regs->msr &= ~MSR_VEC; restore_tm_user_regs() 812 if (msr & MSR_VEC) { restore_tm_user_regs() 837 regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1); restore_tm_user_regs() 844 regs->msr &= ~MSR_VSX; restore_tm_user_regs() 845 if (msr & MSR_VSX) { restore_tm_user_regs() 864 regs->msr &= ~MSR_SPE; restore_tm_user_regs() 865 if (msr & MSR_SPE) { restore_tm_user_regs() 886 regs->msr = (regs->msr & ~MSR_TS_MASK) | (msr_hi & MSR_TS_MASK); restore_tm_user_regs() 895 tm_recheckpoint(&current->thread, msr); restore_tm_user_regs() 898 if (msr & MSR_FP) { restore_tm_user_regs() 900 regs->msr |= (MSR_FP | current->thread.fpexc_mode); restore_tm_user_regs() 903 if (msr & MSR_VEC) { restore_tm_user_regs() 905 regs->msr |= MSR_VEC; restore_tm_user_regs() 1026 if (MSR_TM_ACTIVE(regs->msr)) { handle_rt_signal32() 1061 regs->msr &= ~MSR_LE; handle_rt_signal32() 1062 regs->msr |= (MSR_KERNEL & MSR_LE); handle_rt_signal32() 1311 unsigned long new_msr = regs->msr; sys_debug_setcontext() 1361 regs->msr = new_msr; sys_debug_setcontext() 1451 if (MSR_TM_ACTIVE(regs->msr)) { handle_signal32() 1477 regs->msr &= ~MSR_LE; handle_signal32()
H A D	traps.c	255 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, _exception() 283 if (!(regs->msr & MSR_RI)) system_reset_exception() 292 * regs->nip and regs->msr contains srr0 and ssr1. 330 unsigned long msr = regs->msr; check_io_access() local 334 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) check_io_access() 357 regs->msr |= MSR_RI; check_io_access() 387 #define get_reason(regs) ((regs)->msr) 388 #define get_mc_reason(regs) ((regs)->msr) 395 #define single_stepping(regs) ((regs)->msr & MSR_SE) 396 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 692 printk("Unknown values in msr\n"); machine_check_generic() 739 if (!(regs->msr & MSR_RI)) machine_check_exception() 770 regs->nip, regs->msr, regs->trap); unknown_exception() 912 if ((regs->msr & MSR_64BIT) == 0) emulate_string_inst() 990 if (MSR_TM_TRANSACTIONAL(regs->msr)) { tm_abort_check() 1159 if (!(regs->msr & MSR_PR) && /* not user-mode */ program_check_exception() 1194 "at %lx (msr 0x%x)\n", regs->nip, reason); program_check_exception() 1254 regs->msr |= REASON_ILLEGAL; emulation_assist_interrupt() 1309 regs->nip, regs->msr); nonrecoverable_exception() 1410 hv ? "Hypervisor " : "", facility, regs->nip, regs->msr); facility_unavailable_exception() 1428 regs->nip, regs->msr); fp_unavailable_tm() 1441 regs->msr |= (MSR_FP | current->thread.fpexc_mode); fp_unavailable_tm() 1452 if (regs->msr & MSR_VEC) { fp_unavailable_tm() 1455 regs->msr |= MSR_VSX; fp_unavailable_tm() 1467 regs->nip, regs->msr); altivec_unavailable_tm() 1469 regs->msr |= MSR_VEC; altivec_unavailable_tm() 1473 if (regs->msr & MSR_FP) { altivec_unavailable_tm() 1475 regs->msr |= MSR_VSX; altivec_unavailable_tm() 1481 unsigned long orig_msr = regs->msr; vsx_unavailable_tm() 1492 regs->nip, regs->msr); vsx_unavailable_tm() 1498 regs->msr |= MSR_VSX; vsx_unavailable_tm() 1505 regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode | vsx_unavailable_tm() 1511 tm_recheckpoint(&current->thread, regs->msr & ~orig_msr); vsx_unavailable_tm() 1596 regs->msr |= MSR_DE; handle_debug() 1615 regs->msr &= ~MSR_DE; DebugException() 1626 regs->msr |= MSR_DE; DebugException() 1637 regs->msr &= ~MSR_DE; DebugException() 1656 regs->msr |= MSR_DE; DebugException() 1672 regs->nip, regs->msr, regs->trap, print_tainted()); TAUException() 1779 if (regs->msr & MSR_SPE) SPEFloatingPointRoundException()
H A D	ptrace.c	100 REG_OFFSET_NAME(msr), 154 * Set of msr bits that gdb can change on behalf of a process. 173 return task->thread.regs->msr | task->thread.fpexc_mode; get_user_msr() 176 static int set_user_msr(struct task_struct *task, unsigned long msr) set_user_msr() argument 178 task->thread.regs->msr &= ~MSR_DEBUGCHANGE; set_user_msr() 179 task->thread.regs->msr |= msr & MSR_DEBUGCHANGE; set_user_msr() 281 0, offsetof(struct pt_regs, msr)); gpr_get() 283 unsigned long msr = get_user_msr(target); gpr_get() local 284 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr, gpr_get() 285 offsetof(struct pt_regs, msr), gpr_get() 286 offsetof(struct pt_regs, msr) + gpr_get() 287 sizeof(msr)); gpr_get() 291 offsetof(struct pt_regs, msr) + sizeof(long)); gpr_get() 330 offsetof(struct pt_regs, msr) + sizeof(long)); gpr_set() 860 regs->msr |= MSR_DE; user_enable_single_step() 862 regs->msr &= ~MSR_BE; user_enable_single_step() 863 regs->msr |= MSR_SE; user_enable_single_step() 877 regs->msr |= MSR_DE; user_enable_block_step() 879 regs->msr &= ~MSR_SE; user_enable_block_step() 880 regs->msr |= MSR_BE; user_enable_block_step() 908 regs->msr &= ~MSR_DE; user_disable_single_step() 911 regs->msr &= ~(MSR_SE | MSR_BE); user_disable_single_step() 1032 task->thread.regs->msr &= ~MSR_DE; ptrace_set_debugreg() 1054 task->thread.regs->msr |= MSR_DE; ptrace_set_debugreg() 1154 child->thread.regs->msr |= MSR_DE; set_instruction_bp() 1269 child->thread.regs->msr |= MSR_DE; set_dac() 1363 child->thread.regs->msr |= MSR_DE; set_dac_range() 1496 child->thread.regs->msr &= ~MSR_DE; ppc_del_hwdebug()
H A D	kprobes.c	131 kcb->kprobe_saved_msr = regs->msr; set_current_kprobe() 165 regs->msr &= ~MSR_SINGLESTEP; kprobe_handler() 166 regs->msr |= kcb->kprobe_saved_msr; kprobe_handler() 177 kcb->kprobe_saved_msr = regs->msr; kprobe_handler() 382 regs->msr |= kcb->kprobe_saved_msr; post_kprobe_handler() 394 * if somebody else is singlestepping across a probe point, msr post_kprobe_handler() 398 if (regs->msr & MSR_SINGLESTEP) post_kprobe_handler() 421 regs->msr &= ~MSR_SINGLESTEP; /* Turn off 'trace' bits */ kprobe_fault_handler() 422 regs->msr |= kcb->kprobe_saved_msr; kprobe_fault_handler()
H A D	ppc32.h	22 unsigned int msr; member in struct:pt_regs32
H A D	kgdb.c	253 PACK64(ptr, regs->msr); sleeping_thread_to_gdb_regs() 341 { "msr", GDB_SIZEOF_REG, offsetof(struct pt_regs, msr) }, 355 /* pc, msr, ls... registers 64 -> 69 */ dbg_get_reg() 381 /* pc, msr, ls... registers 64 -> 69 */ dbg_set_reg() 431 linux_regs->msr |= MSR_DE; kgdb_arch_handle_exception() 433 linux_regs->msr |= MSR_SE; kgdb_arch_handle_exception()
H A D	mce.c	90 mce->srr1 = regs->msr; save_mce_event() 101 srr1 = regs->msr; save_mce_event()
H A D	mce_power.c	274 srr1 = regs->msr; __machine_check_early_realmode_p7() 343 srr1 = regs->msr; __machine_check_early_realmode_p8()
H A D	signal.c	190 if (MSR_TM_ACTIVE(regs->msr)) { get_tm_stackpointer() 192 if (MSR_TM_TRANSACTIONAL(regs->msr)) get_tm_stackpointer()
H A D	head_booke.h	226 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \ 229 lis r10,msr@h; \ 230 ori r10,r10,msr@l; \
/linux-4.1.27/arch/microblaze/include/asm/
H A D	kgdb.h	12 * 6 32-bit special registers (pc, msr, ear, esr, fsr, btr)
H A D	setup.h	39 unsigned int fdt, unsigned int msr, unsigned int tlb0,
/linux-4.1.27/sound/pci/ctxfi/
H A D	ctsrc.c	186 if (src->rsc.msr > 1) { src_commit_write() 197 for (i = 1; i < src->rsc.msr; i++) { src_commit_write() 232 unsigned int rsr, msr; src_default_config_memrd() local 236 for (rsr = 0, msr = src->rsc.msr; msr > 1; msr >>= 1) src_default_config_memrd() 258 for (msr = 1; msr < src->rsc.msr; msr++) { src_default_config_memrd() 300 unsigned int rsr, msr; src_default_config_arcrw() local 305 for (rsr = 0, msr = src->rsc.msr; msr > 1; msr >>= 1) src_default_config_arcrw() 327 for (msr = 0; msr < src->rsc.msr; msr++) { src_default_config_arcrw() 369 err = rsc_init(&p->rsc, idx + i, SRC, desc->msr, mgr->mgr.hw); src_rsc_init() 496 for (i = 0; i < src->rsc.msr; i++) { src_enable_s() 512 for (i = 0; i < src->rsc.msr; i++) { src_enable() 528 for (i = 0; i < src->rsc.msr; i++) { src_disable() 631 for (i = 0; i < srcimp->rsc.msr; i++) { srcimp_map() 654 for (i = 0; i < srcimp->rsc.msr; i++) { srcimp_unmap() 677 SRCIMP, desc->msr, mgr->mgr.hw); srcimp_rsc_init() 682 srcimp->imappers = kzalloc(sizeof(struct imapper)*desc->msr, srcimp_rsc_init() 735 for (i = 0; i < desc->msr; i++) { get_srcimp_rsc() 773 for (i = 0; i < srcimp->rsc.msr; i++) put_srcimp_rsc()
H A D	ctatc.c	261 desc.msr = atc->msr; atc_pcm_playback_prepare() 268 (atc->rsr * atc->msr)); atc_pcm_playback_prepare() 283 mix_dsc.msr = atc->msr; atc_pcm_playback_prepare() 387 max_cisz = src->multi * src->rsc.msr; atc_pcm_playback_start() 448 max_cisz = src->multi * src->rsc.msr; atc_pcm_playback_position() 456 unsigned int msr:8; member in struct:src_node_conf_t 468 pitch = atc_get_pitch((atc->rsr * atc->msr), setup_src_node_conf() 472 if (1 == atc->msr) { /* FIXME: do we really need SRC here if pitch==1 */ setup_src_node_conf() 475 conf[0].mix_msr = conf[0].imp_msr = conf[0].msr = 1; setup_src_node_conf() 477 } else if (2 <= atc->msr) { setup_src_node_conf() 481 conf[0].pitch = (atc->msr << 24); setup_src_node_conf() 482 conf[0].msr = conf[0].mix_msr = 1; setup_src_node_conf() 483 conf[0].imp_msr = atc->msr; setup_src_node_conf() 487 conf[1].msr = conf[1].mix_msr = conf[1].imp_msr = 1; setup_src_node_conf() 494 conf[0].msr = conf[0].mix_msr setup_src_node_conf() 495 = conf[0].imp_msr = atc->msr; setup_src_node_conf() 529 pitch = atc_get_pitch((atc->rsr * atc->msr), atc_pcm_capture_get_resources() 539 n_amixer += multi * atc->msr; atc_pcm_capture_get_resources() 540 n_srcimp += multi * atc->msr; atc_pcm_capture_get_resources() 567 src_dsc.msr = src_node_conf[i/multi].msr; atc_pcm_capture_get_resources() 585 mix_dsc.msr = atc->msr; atc_pcm_capture_get_resources() 587 mix_dsc.msr = src_node_conf[(i-n_sum*2)/multi].mix_msr; atc_pcm_capture_get_resources() 589 mix_dsc.msr = 1; atc_pcm_capture_get_resources() 600 sum_dsc.msr = atc->msr; atc_pcm_capture_get_resources() 605 pitch = atc_get_pitch((atc->rsr * atc->msr), atc_pcm_capture_get_resources() 610 srcimp_dsc.msr = src_node_conf[i/multi].imp_msr; atc_pcm_capture_get_resources() 612 srcimp_dsc.msr = (pitch <= 0x8000000) ? atc->msr : 1; atc_pcm_capture_get_resources() 614 srcimp_dsc.msr = 1; atc_pcm_capture_get_resources() 626 src_dsc.msr = 1; atc_pcm_capture_get_resources() 692 pitch = atc_get_pitch((atc->rsr * atc->msr), atc_pcm_capture_prepare() 700 for (j = 0; j < atc->msr; j++) { atc_pcm_capture_prepare() 802 desc.msr = 1; spdif_passthru_playback_get_resources() 803 while (apcm->substream->runtime->rate > (rsr * desc.msr)) spdif_passthru_playback_get_resources() 804 desc.msr <<= 1; spdif_passthru_playback_get_resources() 811 pitch = atc_get_pitch(apcm->substream->runtime->rate, (rsr * desc.msr)); spdif_passthru_playback_get_resources() 827 mix_dsc.msr = desc.msr; spdif_passthru_playback_get_resources() 1124 da_dsc.msr = state ? 1 : atc->msr; atc_spdif_out_passthru() 1345 info.msr = atc->msr; atc_create_hw_devs() 1398 da_desc.msr = atc->msr; atc_get_resources() 1415 src_dsc.msr = atc->msr; atc_get_resources() 1427 srcimp_dsc.msr = 8; atc_get_resources() 1438 sum_dsc.msr = atc->msr; atc_get_resources() 1577 info.msr = atc->msr; atc_hw_resume() 1678 unsigned int rsr, unsigned int msr, ct_atc_create() 1700 atc->msr = msr; ct_atc_create() 1677 ct_atc_create(struct snd_card *card, struct pci_dev *pci, unsigned int rsr, unsigned int msr, int chip_type, unsigned int ssid, struct ct_atc **ratc) ct_atc_create() argument
H A D	ctdaio.c	166 entry = kzalloc((sizeof(*entry) * daio->rscl.msr), GFP_KERNEL); dao_set_left_input() 174 for (i = 0; i < daio->rscl.msr; i++, entry++) { dao_set_left_input() 195 entry = kzalloc((sizeof(*entry) * daio->rscr.msr), GFP_KERNEL); dao_set_right_input() 203 for (i = 0; i < daio->rscr.msr; i++, entry++) { dao_set_right_input() 207 dao->imappers[daio->rscl.msr + i] = entry; dao_set_right_input() 230 for (i = 1; i < daio->rscl.msr; i++) { dao_clear_left_input() 248 if (!dao->imappers[daio->rscl.msr]) dao_clear_right_input() 251 entry = dao->imappers[daio->rscl.msr]; dao_clear_right_input() 254 for (i = 1; i < daio->rscr.msr; i++) { dao_clear_right_input() 255 entry = dao->imappers[daio->rscl.msr + i]; dao_clear_right_input() 257 dao->imappers[daio->rscl.msr + i] = NULL; dao_clear_right_input() 260 kfree(dao->imappers[daio->rscl.msr]); dao_clear_right_input() 261 dao->imappers[daio->rscl.msr] = NULL; dao_clear_right_input() 291 static int dai_set_srt_msr(struct dai *dai, unsigned int msr) dai_set_srt_msr() argument 295 for (rsr = 0; msr > 1; msr >>= 1) dai_set_srt_msr() 349 err = rsc_init(&daio->rscl, idx_l, DAIO, desc->msr, hw); daio_rsc_init() 353 err = rsc_init(&daio->rscr, idx_r, DAIO, desc->msr, hw); daio_rsc_init() 401 dao->imappers = kzalloc(sizeof(void *)*desc->msr*2, GFP_KERNEL); dao_rsc_init() 417 conf = (desc->msr & 0x7) | (desc->passthru << 3); dao_rsc_init() 440 if (dao->imappers[dao->daio.rscl.msr]) dao_rsc_uninit() 459 dsc.msr = desc->msr; dao_rsc_reinit() 471 unsigned int rsr, msr; dai_rsc_init() local 483 for (rsr = 0, msr = desc->msr; msr > 1; msr >>= 1) dai_rsc_init()
H A D	ctdaio.h	69 unsigned int msr:4; member in struct:dao_desc 87 int (*set_srt_msr)(struct dai *dai, unsigned int msr); 96 unsigned int msr:4; member in struct:daio_desc
H A D	ctresource.h	39 u32 msr:4; /* The Master Sample Rate a resource working on */ member in struct:rsc 54 rsc_init(struct rsc *rsc, u32 idx, enum RSCTYP type, u32 msr, struct hw *hw);
H A D	ctamixer.c	133 for (i = 0; i < amixer->rsc.msr; i++) { amixer_commit_write() 207 AMIXER, desc->msr, mgr->mgr.hw); amixer_rsc_init() 252 for (i = 0; i < desc->msr; i++) { get_amixer_rsc() 290 for (i = 0; i < amixer->rsc.msr; i++) put_amixer_rsc() 373 err = rsc_init(&sum->rsc, sum->idx[0], SUM, desc->msr, mgr->mgr.hw); sum_rsc_init() 407 for (i = 0; i < desc->msr; i++) { get_sum_rsc() 445 for (i = 0; i < sum->rsc.msr; i++) put_sum_rsc()
H A D	ctresource.c	119 for (i = 0; (i < 8) && (!(rsc->msr & (0x1 << i))); ) rsc_next_conj() 138 rsc_init(struct rsc *rsc, u32 idx, enum RSCTYP type, u32 msr, struct hw *hw) rsc_init() argument 145 rsc->msr = msr; rsc_init() 204 rsc->msr = 0; rsc_uninit()
H A D	ctamixer.h	34 unsigned int msr; member in struct:sum_desc 79 unsigned int msr; member in struct:amixer_desc
H A D	cthw20k2.c	1139 unsigned int msr; /* master sample rate in rsrs */ member in struct:dac_conf 1143 unsigned int msr; /* master sample rate in rsrs */ member in struct:adc_conf 1149 unsigned int msr; /* master sample rate in rsrs */ member in struct:daio_conf 1163 if (1 == info->msr) { hw_daio_init() 1167 } else if (2 == info->msr) { hw_daio_init() 1185 } else if ((4 == info->msr) && (hw->model == CTSB1270)) { hw_daio_init() 1227 if (2 == info->msr) { hw_daio_init() 1230 } else if (4 == info->msr) { hw_daio_init() 1641 if (1 == info->msr) hw_dac_init() 1643 else if (2 == info->msr) hw_dac_init() 1731 if (1 == info->msr) { hw_dac_init() 1736 } else if (2 == info->msr) { hw_dac_init() 1864 if (1 == info->msr) hw_adc_init() 1866 else if (2 == info->msr) hw_adc_init() 1886 if (1 == info->msr) { hw_adc_init() 1890 } else if ((2 == info->msr) || (4 == info->msr)) { hw_adc_init() 1896 "Invalid master sampling rate (msr %d)!!!\n", hw_adc_init() 1897 info->msr); hw_adc_init() 2182 daio_info.msr = info->msr; hw_card_init() 2187 dac_info.msr = info->msr; hw_card_init() 2192 adc_info.msr = info->msr; hw_card_init()
H A D	ctatc.h	81 unsigned int msr; /* master sample rate in rsr */ member in struct:ct_atc 156 unsigned int rsr, unsigned int msr, int chip_type,
H A D	ctsrc.h	82 unsigned char msr; member in struct:src_desc 123 unsigned int msr; member in struct:srcimp_desc
/linux-4.1.27/arch/powerpc/kvm/
H A D	trace_booke.h	46 __field( unsigned long, msr ) 55 __entry->msr = vcpu->arch.shared->msr; 61 " | msr=0x%lx" 67 __entry->msr,
H A D	book3s_pr.c	55 ulong msr); 67 ulong msr = kvmppc_get_msr(vcpu); kvmppc_is_split_real() local 68 return (msr & (MSR_IR|MSR_DR)) == MSR_DR; kvmppc_is_split_real() 73 ulong msr = kvmppc_get_msr(vcpu); kvmppc_fixup_split_real() local 77 if ((msr & (MSR_IR|MSR_DR)) != MSR_DR) kvmppc_fixup_split_real() 337 static void kvmppc_set_msr_pr(struct kvm_vcpu *vcpu, u64 msr) kvmppc_set_msr_pr() argument 342 printk(KERN_INFO "KVM: Set MSR to 0x%llx\n", msr); kvmppc_set_msr_pr() 345 msr &= to_book3s(vcpu)->msr_mask; kvmppc_set_msr_pr() 346 kvmppc_set_msr_fast(vcpu, msr); kvmppc_set_msr_pr() 349 if (msr & MSR_POW) { kvmppc_set_msr_pr() 356 msr &= ~MSR_POW; kvmppc_set_msr_pr() 357 kvmppc_set_msr_fast(vcpu, msr); kvmppc_set_msr_pr() 372 if (!(msr & MSR_PR) && vcpu->arch.magic_page_pa) { kvmppc_set_msr_pr() 375 if (msr & MSR_DR) kvmppc_set_msr_pr() 391 !(old_msr & MSR_PR) && !(old_msr & MSR_SF) && (msr & MSR_SF)) { kvmppc_set_msr_pr() 598 u64 msr = kvmppc_get_msr(vcpu); kvmppc_handle_pagefault() local 601 kvmppc_set_msr_fast(vcpu, msr | (ssrr1 & 0xf8000000ULL)); kvmppc_handle_pagefault() 607 u64 msr = kvmppc_get_msr(vcpu); kvmppc_handle_pagefault() local 611 kvmppc_set_msr_fast(vcpu, msr | (ssrr1 & 0xf8000000ULL)); kvmppc_handle_pagefault() 648 void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr) kvmppc_giveup_ext() argument 656 if (msr & MSR_VSX) kvmppc_giveup_ext() 657 msr |= MSR_FP | MSR_VEC; kvmppc_giveup_ext() 659 msr &= vcpu->arch.guest_owned_ext; kvmppc_giveup_ext() 660 if (!msr) kvmppc_giveup_ext() 664 printk(KERN_INFO "Giving up ext 0x%lx\n", msr); kvmppc_giveup_ext() 667 if (msr & MSR_FP) { kvmppc_giveup_ext() 673 if (t->regs->msr & MSR_FP) kvmppc_giveup_ext() 679 if (msr & MSR_VEC) { kvmppc_giveup_ext() 680 if (current->thread.regs->msr & MSR_VEC) kvmppc_giveup_ext() 686 vcpu->arch.guest_owned_ext &= ~(msr | MSR_VSX); kvmppc_giveup_ext() 711 ulong msr) kvmppc_handle_ext() 719 if (!(kvmppc_get_msr(vcpu) & msr)) { kvmppc_handle_ext() 724 if (msr == MSR_VSX) { kvmppc_handle_ext() 738 msr = MSR_FP | MSR_VEC | MSR_VSX; kvmppc_handle_ext() 742 msr &= ~vcpu->arch.guest_owned_ext; kvmppc_handle_ext() 743 if (!msr) kvmppc_handle_ext() 747 printk(KERN_INFO "Loading up ext 0x%lx\n", msr); kvmppc_handle_ext() 750 if (msr & MSR_FP) { kvmppc_handle_ext() 758 if (msr & MSR_VEC) { kvmppc_handle_ext() 768 t->regs->msr |= msr; kvmppc_handle_ext() 769 vcpu->arch.guest_owned_ext |= msr; kvmppc_handle_ext() 783 lost_ext = vcpu->arch.guest_owned_ext & ~current->thread.regs->msr; kvmppc_handle_lost_ext() 801 current->thread.regs->msr |= lost_ext; kvmppc_handle_lost_ext() 940 u64 msr = kvmppc_get_msr(vcpu); kvmppc_handle_exit_pr() local 941 msr |= shadow_srr1 & 0x58000000; kvmppc_handle_exit_pr() 942 kvmppc_set_msr_fast(vcpu, msr); kvmppc_handle_exit_pr() 1214 printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | msr=0x%lx\n", kvmppc_handle_exit_pr() 1490 if (current->thread.regs->msr & MSR_FP) kvmppc_vcpu_run_pr() 1495 if (current->thread.regs->msr & MSR_VEC) kvmppc_vcpu_run_pr() 1501 if (current->thread.regs->msr & MSR_VSX) kvmppc_vcpu_run_pr() 710 kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, ulong msr) kvmppc_handle_ext() argument
H A D	booke.c	78 printk("pc: %08lx msr: %08llx\n", vcpu->arch.pc, vcpu->arch.shared->msr); kvmppc_dump_vcpu() 115 if (vcpu->arch.shared->msr & MSR_SPE) { kvmppc_vcpu_sync_spe() 140 if (!(current->thread.regs->msr & MSR_FP)) { kvmppc_load_guest_fp() 144 current->thread.regs->msr |= MSR_FP; kvmppc_load_guest_fp() 156 if (current->thread.regs->msr & MSR_FP) kvmppc_save_guest_fp() 168 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_FP; kvmppc_vcpu_sync_fpu() 181 if (!(current->thread.regs->msr & MSR_VEC)) { kvmppc_load_guest_altivec() 185 current->thread.regs->msr |= MSR_VEC; kvmppc_load_guest_altivec() 199 if (current->thread.regs->msr & MSR_VEC) kvmppc_save_guest_altivec() 211 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_DE; kvmppc_vcpu_sync_debug() 221 vcpu->arch.shared->msr |= MSR_DE; kvmppc_vcpu_sync_debug() 224 vcpu->arch.shared->msr &= ~MSR_DE; kvmppc_vcpu_sync_debug() 235 u32 old_msr = vcpu->arch.shared->msr; kvmppc_set_msr() 241 vcpu->arch.shared->msr = new_msr; kvmppc_set_msr() 389 ulong new_msr = vcpu->arch.shared->msr; kvmppc_booke_irqprio_deliver() 392 if (!(vcpu->arch.shared->msr & MSR_SF)) { kvmppc_booke_irqprio_deliver() 400 crit = crit && !(vcpu->arch.shared->msr & MSR_PR); kvmppc_booke_irqprio_deliver() 440 allowed = vcpu->arch.shared->msr & MSR_CE; kvmppc_booke_irqprio_deliver() 446 allowed = vcpu->arch.shared->msr & MSR_ME; kvmppc_booke_irqprio_deliver() 456 allowed = vcpu->arch.shared->msr & MSR_EE; kvmppc_booke_irqprio_deliver() 462 allowed = vcpu->arch.shared->msr & MSR_DE; kvmppc_booke_irqprio_deliver() 477 vcpu->arch.shared->msr); kvmppc_booke_irqprio_deliver() 481 vcpu->arch.shared->msr); kvmppc_booke_irqprio_deliver() 485 vcpu->arch.shared->msr); kvmppc_booke_irqprio_deliver() 489 vcpu->arch.shared->msr); kvmppc_booke_irqprio_deliver() 684 if (vcpu->arch.shared->msr & MSR_WE) { kvmppc_core_prepare_to_enter() 843 if (dbsr && (vcpu->arch.shared->msr & MSR_DE) && kvmppc_handle_debug() 848 if ((dbsr & DBSR_TIE) && !(vcpu->arch.shared->msr & MSR_DE)) kvmppc_handle_debug() 880 ulong r1, ip, msr, lr; kvmppc_fill_pt_regs() local 884 asm("mfmsr %0" : "=r"(msr)); kvmppc_fill_pt_regs() 890 regs->msr = msr; kvmppc_fill_pt_regs() 1092 if (vcpu->arch.shared->msr & (MSR_PR | MSR_GS)) { kvmppc_handle_exit() 1118 if (vcpu->arch.shared->msr & MSR_SPE) kvmppc_handle_exit() 1196 if (!(vcpu->arch.shared->msr & MSR_PR)) { kvmppc_handle_exit() 1210 if (!(vcpu->arch.shared->msr & MSR_PR) && kvmppc_handle_exit() 1231 if (!(vcpu->arch.shared->msr & MSR_PR) && kvmppc_handle_exit() 1383 vcpu->arch.shared->msr = 0; kvm_arch_vcpu_setup() 1428 regs->msr = vcpu->arch.shared->msr; kvm_arch_vcpu_ioctl_get_regs() 1456 kvmppc_set_msr(vcpu, regs->msr); kvm_arch_vcpu_ioctl_set_regs() 1938 if (!(vcpu->arch.shared->msr & MSR_PR) && kvmppc_xlate()
H A D	trace_pr.h	225 __field( unsigned long, msr ) 235 __entry->msr = kvmppc_get_msr(vcpu); 242 " | msr=0x%lx" 249 __entry->msr,
H A D	booke_emulate.c	91 kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr); kvmppc_booke_emulate_op() 101 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE) kvmppc_booke_emulate_op() 107 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE) kvmppc_booke_emulate_op()
H A D	trace_hv.h	254 __field(unsigned long, msr) 263 __entry->msr = vcpu->arch.shregs.msr; 266 TP_printk("VCPU %d: trap=%s pc=0x%lx msr=0x%lx, ceded=%d", 269 __entry->pc, __entry->msr, __entry->ceded
H A D	book3s.c	236 u64 msr = kvmppc_get_msr(vcpu); kvmppc_core_queue_inst_storage() local 237 msr &= ~(SRR1_ISI_NOPT | SRR1_ISI_N_OR_G | SRR1_ISI_PROT); kvmppc_core_queue_inst_storage() 238 msr |= flags & (SRR1_ISI_NOPT | SRR1_ISI_N_OR_G | SRR1_ISI_PROT); kvmppc_core_queue_inst_storage() 239 kvmppc_set_msr_fast(vcpu, msr); kvmppc_core_queue_inst_storage() 475 regs->msr = kvmppc_get_msr(vcpu); kvm_arch_vcpu_ioctl_get_regs() 503 kvmppc_set_msr(vcpu, regs->msr); kvm_arch_vcpu_ioctl_set_regs() 691 void kvmppc_set_msr(struct kvm_vcpu *vcpu, u64 msr) kvmppc_set_msr() argument 693 vcpu->kvm->arch.kvm_ops->set_msr(vcpu, msr); kvmppc_set_msr()
H A D	book3s_32_mmu.c	369 u64 msr = kvmppc_get_msr(vcpu); kvmppc_mmu_book3s_32_esid_to_vsid() local 371 if (msr & (MSR_DR|MSR_IR)) { kvmppc_mmu_book3s_32_esid_to_vsid() 380 switch (msr & (MSR_DR|MSR_IR)) { kvmppc_mmu_book3s_32_esid_to_vsid() 400 if (msr & MSR_PR) kvmppc_mmu_book3s_32_esid_to_vsid()
H A D	e500.h	218 return !!(vcpu->arch.shared->msr & (MSR_IS | MSR_DS)); get_cur_as() 223 return !!(vcpu->arch.shared->msr & MSR_PR); get_cur_pr() 266 if (get_tlb_ts(tlbe) != !!(vcpu->arch.shared->msr & MSR_IS)) tlbe_is_host_safe()
H A D	e500_mmu.c	415 if (!(vcpu->arch.shared->msr & MSR_CM)) kvmppc_e500_emul_tlbwe() 500 unsigned int as = !!(vcpu->arch.shared->msr & MSR_IS); kvmppc_mmu_itlb_index() 507 unsigned int as = !!(vcpu->arch.shared->msr & MSR_DS); kvmppc_mmu_dtlb_index() 514 unsigned int as = !!(vcpu->arch.shared->msr & MSR_IS); kvmppc_mmu_itlb_miss() 521 unsigned int as = !!(vcpu->arch.shared->msr & MSR_DS); kvmppc_mmu_dtlb_miss()
H A D	book3s_64_mmu.c	585 u64 msr = kvmppc_get_msr(vcpu); kvmppc_mmu_book3s_64_esid_to_vsid() local 587 if (msr & (MSR_DR|MSR_IR)) { kvmppc_mmu_book3s_64_esid_to_vsid() 600 switch (msr & (MSR_DR|MSR_IR)) { kvmppc_mmu_book3s_64_esid_to_vsid()
/linux-4.1.27/tools/power/cpupower/utils/idle_monitor/
H A D	nhm_idle.c	75 int msr; nhm_get_count() local 79 msr = MSR_CORE_C3_RESIDENCY; nhm_get_count() 82 msr = MSR_CORE_C6_RESIDENCY; nhm_get_count() 85 msr = MSR_PKG_C3_RESIDENCY; nhm_get_count() 88 msr = MSR_PKG_C6_RESIDENCY; nhm_get_count() 91 msr = MSR_TSC; nhm_get_count() 96 if (read_msr(cpu, msr, val)) nhm_get_count()
H A D	hsw_ext_idle.c	67 int msr; hsw_ext_get_count() local 71 msr = MSR_PKG_C8_RESIDENCY; hsw_ext_get_count() 74 msr = MSR_PKG_C9_RESIDENCY; hsw_ext_get_count() 77 msr = MSR_PKG_C10_RESIDENCY; hsw_ext_get_count() 80 msr = MSR_TSC; hsw_ext_get_count() 85 if (read_msr(cpu, msr, val)) hsw_ext_get_count()
H A D	snb_idle.c	64 int msr; snb_get_count() local 68 msr = MSR_CORE_C7_RESIDENCY; snb_get_count() 71 msr = MSR_PKG_C2_RESIDENCY; snb_get_count() 74 msr = MSR_PKG_C7_RESIDENCY; snb_get_count() 77 msr = MSR_TSC; snb_get_count() 82 if (read_msr(cpu, msr, val)) snb_get_count()
/linux-4.1.27/arch/arm/kvm/
H A D	interrupts_head.S	104 msr SP_\mode, r2 105 msr LR_\mode, r3 106 msr SPSR_\mode, r4 115 msr r8_fiq, r2 116 msr r9_fiq, r3 117 msr r10_fiq, r4 118 msr r11_fiq, r5 119 msr r12_fiq, r6 120 msr SP_fiq, r7 121 msr LR_fiq, r8 122 msr SPSR_fiq, r9 130 msr SP_usr, r2 135 msr ELR_hyp, r2 149 msr SP_\mode, r2 150 msr LR_\mode, r3 151 msr SPSR_\mode, r4 169 msr r8_fiq, r2 170 msr r9_fiq, r3 171 msr r10_fiq, r4 172 msr r11_fiq, r5 173 msr r12_fiq, r6 174 msr SP_fiq, r7 175 msr LR_fiq, r8 176 msr SPSR_fiq, r9 181 msr ELR_hyp, r2 182 msr SPSR_cxsf, r3 187 msr SP_usr, r2
/linux-4.1.27/arch/powerpc/lib/
H A D	sstep.c	51 static unsigned long truncate_if_32bit(unsigned long msr, unsigned long val) truncate_if_32bit() argument 54 if ((msr & MSR_64BIT) == 0) truncate_if_32bit() 104 return truncate_if_32bit(regs->msr, ea); dform_ea() 121 return truncate_if_32bit(regs->msr, ea); dsform_ea() 140 return truncate_if_32bit(regs->msr, ea); xform_ea() 539 if (!(regs->msr & MSR_64BIT)) set_cr0() 560 if (!(regs->msr & MSR_64BIT)) { add_with_carry() 661 regs->nip = truncate_if_32bit(regs->msr, regs->nip); analyse_instr() 665 regs->nip = truncate_if_32bit(regs->msr, imm); analyse_instr() 683 regs->link = truncate_if_32bit(regs->msr, regs->nip + 4); analyse_instr() 684 imm = truncate_if_32bit(regs->msr, imm); analyse_instr() 700 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4); analyse_instr() 701 imm = truncate_if_32bit(regs->msr, imm); analyse_instr() 709 if (regs->msr & MSR_PR) analyse_instr() 944 if (regs->msr & MSR_PR) analyse_instr() 950 if (regs->msr & MSR_PR) analyse_instr() 958 if (regs->msr & MSR_PR) analyse_instr() 1378 if (!(regs->msr & MSR_VEC)) analyse_instr() 1385 if (!(regs->msr & MSR_VEC)) analyse_instr() 1450 op->ea = truncate_if_32bit(regs->msr, analyse_instr() 1457 if (!(regs->msr & MSR_FP)) analyse_instr() 1464 if (!(regs->msr & MSR_FP)) analyse_instr() 1471 if (!(regs->msr & MSR_FP)) analyse_instr() 1478 if (!(regs->msr & MSR_FP)) analyse_instr() 1506 op->ea = truncate_if_32bit(regs->msr, analyse_instr() 1522 if (!(regs->msr & MSR_VSX)) analyse_instr() 1530 if (!(regs->msr & MSR_VSX)) analyse_instr() 1597 if (!(regs->msr & MSR_FP)) analyse_instr() 1605 if (!(regs->msr & MSR_FP)) analyse_instr() 1613 if (!(regs->msr & MSR_FP)) analyse_instr() 1621 if (!(regs->msr & MSR_FP)) analyse_instr() 1670 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4); analyse_instr() 1809 if (regs->msr & MSR_LE) emulate_step() 1832 if (regs->msr & MSR_LE) emulate_step() 1857 if (regs->msr & MSR_LE) emulate_step() 1870 if (regs->msr & MSR_LE) emulate_step() 1880 if (regs->msr & MSR_LE) emulate_step() 1887 if (regs->msr & MSR_LE) emulate_step() 1893 if (regs->msr & MSR_LE) emulate_step() 1911 if (regs->msr & MSR_LE) emulate_step() 1915 !(regs->msr & MSR_PR) && emulate_step() 1925 if (regs->msr & MSR_LE) emulate_step() 1935 if (regs->msr & MSR_LE) emulate_step() 1942 if (regs->msr & MSR_LE) emulate_step() 1948 if (regs->msr & MSR_LE) emulate_step() 1967 regs->gpr[op.reg] = regs->msr & MSR_MASK; emulate_step() 1976 regs->msr = (regs->msr & ~op.val) | (val & op.val); emulate_step() 1988 regs->msr ^= MSR_LE; emulate_step() 1994 regs->gpr[12] = regs->msr & MSR_MASK; emulate_step() 1997 regs->msr = MSR_KERNEL; emulate_step() 2013 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4); emulate_step()
/linux-4.1.27/arch/powerpc/platforms/pasemi/
H A D	idle.c	52 if (regs->msr & SRR1_WAKEMASK) pasemi_system_reset_exception() 55 switch (regs->msr & SRR1_WAKEMASK) { pasemi_system_reset_exception() 71 regs->msr |= MSR_RI; pasemi_system_reset_exception()
/linux-4.1.27/samples/kprobes/
H A D	kprobe_example.c	32 " msr = 0x%lx\n", handler_pre() 33 p->addr, regs->nip, regs->msr); handler_pre() 59 printk(KERN_INFO "post_handler: p->addr = 0x%p, msr = 0x%lx\n", handler_post() 60 p->addr, regs->msr); handler_post()
/linux-4.1.27/drivers/cpufreq/
H A D	acpi-cpufreq.c	45 #include <asm/msr.h> 83 static struct msr __percpu *msrs; 88 u64 msr; boost_state() local 93 msr = lo | ((u64)hi << 32); boost_state() 94 return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); boost_state() 97 msr = lo | ((u64)hi << 32); boost_state() 98 return !(msr & MSR_K7_HWCR_CPB_DIS); boost_state() 125 struct msr *reg = per_cpu_ptr(msrs, cpu); for_each_cpu() 214 static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) extract_msr() argument 220 msr &= AMD_MSR_RANGE; extract_msr() 222 msr &= INTEL_MSR_RANGE; extract_msr() 227 if (msr == perf->states[pos->driver_data].status) extract_msr() 258 struct msr_addr msr; member in union:drv_cmd::__anon3767 273 rdmsr(cmd->addr.msr.reg, cmd->val, h); do_drv_read() 293 rdmsr(cmd->addr.msr.reg, lo, hi); do_drv_write() 295 wrmsr(cmd->addr.msr.reg, lo, hi); do_drv_write() 298 wrmsr(cmd->addr.msr.reg, cmd->val, 0); do_drv_write() 341 cmd.addr.msr.reg = MSR_IA32_PERF_CTL; get_cur_val() 345 cmd.addr.msr.reg = MSR_AMD_PERF_CTL; get_cur_val() 439 cmd.addr.msr.reg = MSR_IA32_PERF_CTL; acpi_cpufreq_target() 444 cmd.addr.msr.reg = MSR_AMD_PERF_CTL; acpi_cpufreq_target()
H A D	speedstep-centrino.c	25 #include <asm/msr.h> 285 static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe) extract_clock() argument 297 msr = (msr >> 8) & 0xff; extract_clock() 298 return msr * 100000; extract_clock() 305 msr &= 0xffff; extract_clock() 310 if (msr == per_cpu(centrino_model, cpu)->op_points[i].driver_data) extract_clock() 423 unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu; centrino_target() local 462 msr = op_points->driver_data; centrino_target() 466 if (msr == (oldmsr & 0xffff)) { centrino_target() 467 pr_debug("no change needed - msr was and needs " centrino_target() 476 msr &= 0xffff; centrino_target() 477 oldmsr |= msr; centrino_target()
H A D	amd_freq_sensitivity.c	21 #include <asm/msr.h> 46 struct msr actual, reference; amd_powersave_bias_target()
H A D	sc520_freq.c	26 #include <asm/msr.h>
H A D	sfi-cpufreq.c	25 #include <asm/msr.h>
H A D	elanfreq.c	27 #include <asm/msr.h>
/linux-4.1.27/tools/power/x86/x86_energy_perf_policy/
H A D	x86_energy_perf_policy.c	189 unsigned long long msr; get_msr() local 194 sprintf(msr_path, "/dev/cpu/%d/msr", cpu); get_msr() 197 printf("Try \"# modprobe msr\"\n"); get_msr() 202 retval = pread(fd, &msr, sizeof msr, offset); get_msr() 204 if (retval != sizeof msr) { get_msr() 209 return msr; get_msr() 219 sprintf(msr_path, "/dev/cpu/%d/msr", cpu); put_msr()
/linux-4.1.27/drivers/video/fbdev/geode/
H A D	suspend_gx.c	12 #include <asm/msr.h> 30 rdmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel); gx_save_regs() 31 rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll); gx_save_regs() 142 wrmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel); gx_restore_video_proc() 179 gx_set_dotpll((uint32_t) (par->msr.dotpll >> 32)); gx_restore_regs()
H A D	lxfb_ops.c	600 rdmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel); lx_save_regs() 601 rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll); lx_save_regs() 602 rdmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg); lx_save_regs() 603 rdmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare); lx_save_regs() 673 wrmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare); lx_restore_display_ctlr() 737 wrmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg); lx_restore_video_proc() 738 wrmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel); lx_restore_video_proc() 772 lx_set_dotpll((u32) (par->msr.dotpll >> 32)); lx_restore_regs()
/linux-4.1.27/arch/powerpc/platforms/52xx/
H A D	mpc52xx_pm.c	115 u32 msr, hid0; mpc52xx_pm_enter() local 143 msr = mfmsr(); mpc52xx_pm_enter() 144 mtmsr(msr & ~MSR_POW); mpc52xx_pm_enter() 163 mtmsr(msr & ~MSR_POW); mpc52xx_pm_enter() 165 mtmsr(msr); mpc52xx_pm_enter()
/linux-4.1.27/drivers/mfd/
H A D	ezx-pcap.c	46 u32 msr; member in struct:pcap_chip 151 pcap->msr |= 1 << irq_to_pcap(pcap, d->irq); pcap_mask_irq() 159 pcap->msr &= ~(1 << irq_to_pcap(pcap, d->irq)); pcap_unmask_irq() 174 ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr); pcap_msr_work() 181 u32 msr, isr, int_sel, service; pcap_isr_work() local 185 ezx_pcap_read(pcap, PCAP_REG_MSR, &msr); pcap_isr_work() 194 ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr); pcap_isr_work() 198 service = isr & ~msr; pcap_isr_work() 204 ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr); pcap_isr_work() 476 pcap->msr = PCAP_MASK_ALL_INTERRUPT; ezx_pcap_probe()
/linux-4.1.27/arch/arm/kernel/
H A D	iwmmxt.S	201 msr cpsr_c, r2 235 1: msr cpsr_c, ip @ restore interrupt mode 253 msr cpsr_c, r2 262 msr cpsr_c, ip @ restore interrupt mode 273 msr cpsr_c, ip @ restore interrupt mode 291 msr cpsr_c, r2 301 msr cpsr_c, ip @ restore interrupt mode 311 msr cpsr_c, ip @ restore interrupt mode 358 msr cpsr_c, ip 364 msr cpsr_c, r2 @ restore interrupts
H A D	entry-header.S	157 msr psp, r2 178 msr cpsr_c, \rtemp @ switch to the SYS mode 184 msr cpsr_c, \rtemp @ switch back to the SVC mode 190 msr cpsr_c, \rtemp @ switch to the SYS mode 196 msr cpsr_c, \rtemp @ switch back to the SVC mode 218 msr spsr_cxsf, \rpsr 247 msr cpsr_c, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT 250 msr spsr_cxsf, r9 259 msr spsr_cxsf, r1 @ save in spsr_svc 319 msr cpsr_c, r1 344 msr spsr_cxsf, r1 @ save in spsr_svc
H A D	entry-armv.S	332 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 334 THUMB( msr cpsr_c, r0 ) 337 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 339 THUMB( msr cpsr_c, r0 ) 346 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 348 THUMB( msr cpsr_c, r0 ) 350 msr spsr_cxsf, r2 @ Restore spsr_abt 351 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 353 THUMB( msr cpsr_c, r0 ) 1057 msr spsr_cxsf, r0
/linux-4.1.27/arch/arm64/kernel/
H A D	head.S	511 msr sctlr_el2, x0 516 msr sctlr_el1, x0 523 msr hcr_el2, x0 528 msr cnthctl_el2, x0 529 msr cntvoff_el2, xzr // Clear virtual offset 551 msr vpidr_el2, x0 552 msr vmpidr_el2, x1 558 msr sctlr_el1, x0 562 msr cptr_el2, x0 // Disable copro. traps to EL2 565 msr hstr_el2, xzr // Disable CP15 traps to EL2 575 msr mdcr_el2, x0 // all PMU counters from EL1 579 msr vttbr_el2, xzr 584 msr vbar_el2, x0 589 msr spsr_el2, x0 590 msr elr_el2, lr 684 msr vbar_el1, x5 685 msr ttbr0_el1, x25 // load TTBR0 686 msr ttbr1_el1, x26 // load TTBR1 688 msr sctlr_el1, x0
H A D	efi-entry.S	101 msr sctlr_el2, x0 108 msr sctlr_el1, x0
H A D	process.c	218 asm ("msr tpidr_el0, xzr"); tls_thread_flush() 229 asm ("msr tpidrro_el0, xzr"); tls_thread_flush() 319 " msr tpidr_el0, %0\n" tls_thread_switch() 320 " msr tpidrro_el0, %1" tls_thread_switch()
H A D	perf_event.c	883 asm volatile("msr pmcr_el0, %0" :: "r" (val)); armv8pmu_pmcr_write() 923 asm volatile("msr pmselr_el0, %0" :: "r" (counter)); armv8pmu_select_counter() 950 asm volatile("msr pmccntr_el0, %0" :: "r" (value)); armv8pmu_write_counter() 952 asm volatile("msr pmxevcntr_el0, %0" :: "r" (value)); armv8pmu_write_counter() 959 asm volatile("msr pmxevtyper_el0, %0" :: "r" (val)); armv8pmu_write_evtype() 974 asm volatile("msr pmcntenset_el0, %0" :: "r" (BIT(counter))); armv8pmu_enable_counter() 989 asm volatile("msr pmcntenclr_el0, %0" :: "r" (BIT(counter))); armv8pmu_disable_counter() 1004 asm volatile("msr pmintenset_el1, %0" :: "r" (BIT(counter))); armv8pmu_enable_intens() 1019 asm volatile("msr pmintenclr_el1, %0" :: "r" (BIT(counter))); armv8pmu_disable_intens() 1022 asm volatile("msr pmovsclr_el0, %0" :: "r" (BIT(counter))); armv8pmu_disable_intens() 1036 asm volatile("msr pmovsclr_el0, %0" :: "r" (value)); armv8pmu_getreset_flags()
H A D	cacheinfo.c	59 asm volatile("msr csselr_el1, %x0" : : "r" (csselr)); cache_get_ccsidr()
H A D	hyp-stub.S	61 msr vbar_el2, x0 // Set vbar_el2
H A D	sys_compat.c	97 asm ("msr tpidrro_el0, %0" : : "r" (regs->regs[0])); compat_arm_syscall()
H A D	debug-monitors.c	46 asm volatile("msr mdscr_el1, %0" :: "r" (mdscr)); mdscr_write() 130 asm volatile("msr oslar_el1, %0" : : "r" (0)); clear_os_lock()
H A D	entry.S	124 msr sp_el0, x23 134 "mrs x29, contextidr_el1; msr contextidr_el1, x29; 1:", \ 139 "msr contextidr_el1, xzr; 1:", \ 144 msr elr_el1, x21 // set up the return data 145 msr spsr_el1, x22
/linux-4.1.27/arch/x86/kvm/
H A D	pmu.c	61 static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr, get_gp_pmc() argument 64 if (msr >= base && msr < base + pmu->nr_arch_gp_counters) get_gp_pmc() 65 return &pmu->gp_counters[msr - base]; get_gp_pmc() 69 static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr) get_fixed_pmc() argument 72 if (msr >= base && msr < base + pmu->nr_arch_fixed_counters) get_fixed_pmc() 73 return &pmu->fixed_counters[msr - base]; get_fixed_pmc() 323 bool kvm_pmu_msr(struct kvm_vcpu *vcpu, u32 msr) kvm_pmu_msr() argument 328 switch (msr) { kvm_pmu_msr() 336 ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) kvm_pmu_msr() 337 || get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) kvm_pmu_msr() 338 || get_fixed_pmc(pmu, msr); kvm_pmu_msr()
H A D	lapic.h	85 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 86 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 88 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 89 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
H A D	x86.c	58 #include <asm/msr.h> 202 static void shared_msr_update(unsigned slot, u32 msr) shared_msr_update() argument 214 rdmsrl_safe(msr, &value); shared_msr_update() 219 void kvm_define_shared_msr(unsigned slot, u32 msr) kvm_define_shared_msr() argument 224 shared_msrs_global.msrs[slot] = msr; kvm_define_shared_msr() 920 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1010 * Writes msr value into into the appropriate "register". 1014 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) kvm_set_msr() argument 1016 switch (msr->index) { kvm_set_msr() 1022 if (is_noncanonical_address(msr->data)) kvm_set_msr() 1039 msr->data = get_canonical(msr->data); kvm_set_msr() 1041 return kvm_x86_ops->set_msr(vcpu, msr); kvm_set_msr() 1050 struct msr_data msr; do_set_msr() local 1052 msr.data = *data; do_set_msr() 1053 msr.index = index; do_set_msr() 1054 msr.host_initiated = true; do_set_msr() 1055 return kvm_set_msr(vcpu, &msr); do_set_msr() 1293 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) kvm_write_tsc() argument 1301 u64 data = msr->data; kvm_write_tsc() 1400 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) kvm_write_tsc() 1775 static bool msr_mtrr_valid(unsigned msr) msr_mtrr_valid() argument 1777 switch (msr) { msr_mtrr_valid() 1809 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) kvm_mtrr_valid() argument 1814 if (!msr_mtrr_valid(msr)) kvm_mtrr_valid() 1817 if (msr == MSR_IA32_CR_PAT) { kvm_mtrr_valid() 1822 } else if (msr == MSR_MTRRdefType) { kvm_mtrr_valid() 1826 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { kvm_mtrr_valid() 1834 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR)); kvm_mtrr_valid() 1837 if ((msr & 1) == 0) { kvm_mtrr_valid() 1854 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) set_msr_mtrr() argument 1858 if (!kvm_mtrr_valid(vcpu, msr, data)) set_msr_mtrr() 1861 if (msr == MSR_MTRRdefType) { set_msr_mtrr() 1864 } else if (msr == MSR_MTRRfix64K_00000) set_msr_mtrr() 1866 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) set_msr_mtrr() 1867 p[1 + msr - MSR_MTRRfix16K_80000] = data; set_msr_mtrr() 1868 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) set_msr_mtrr() 1869 p[3 + msr - MSR_MTRRfix4K_C0000] = data; set_msr_mtrr() 1870 else if (msr == MSR_IA32_CR_PAT) set_msr_mtrr() 1876 idx = (msr - 0x200) / 2; set_msr_mtrr() 1877 is_mtrr_mask = msr - 0x200 - 2 * idx; set_msr_mtrr() 1891 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) set_msr_mce() argument 1896 switch (msr) { set_msr_mce() 1908 if (msr >= MSR_IA32_MC0_CTL && set_msr_mce() 1909 msr < MSR_IA32_MCx_CTL(bank_num)) { set_msr_mce() 1910 u32 offset = msr - MSR_IA32_MC0_CTL; set_msr_mce() 1963 static bool kvm_hv_msr_partition_wide(u32 msr) kvm_hv_msr_partition_wide() argument 1966 switch (msr) { kvm_hv_msr_partition_wide() 1978 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) set_msr_hyperv_pw() argument 1982 switch (msr) { set_msr_hyperv_pw() 2029 "data 0x%llx\n", msr, data); set_msr_hyperv_pw() 2035 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) set_msr_hyperv() argument 2037 switch (msr) { set_msr_hyperv() 2068 "data 0x%llx\n", msr, data); set_msr_hyperv() 2139 u32 msr = msr_info->index; kvm_set_msr_common() local 2142 switch (msr) { kvm_set_msr_common() 2184 return set_msr_mtrr(vcpu, msr, data); kvm_set_msr_common() 2188 return kvm_x2apic_msr_write(vcpu, msr, data); kvm_set_msr_common() 2217 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); kvm_set_msr_common() 2277 return set_msr_mce(vcpu, msr, data); kvm_set_msr_common() 2292 "0x%x data 0x%llx\n", msr, data); kvm_set_msr_common() 2302 "0x%x data 0x%llx\n", msr, data); kvm_set_msr_common() 2309 if (kvm_pmu_msr(vcpu, msr)) kvm_set_msr_common() 2314 "0x%x data 0x%llx\n", msr, data); kvm_set_msr_common() 2327 if (kvm_hv_msr_partition_wide(msr)) { kvm_set_msr_common() 2330 r = set_msr_hyperv_pw(vcpu, msr, data); kvm_set_msr_common() 2334 return set_msr_hyperv(vcpu, msr, data); kvm_set_msr_common() 2340 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); kvm_set_msr_common() 2353 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) kvm_set_msr_common() 2355 if (kvm_pmu_msr(vcpu, msr)) kvm_set_msr_common() 2359 msr, data); kvm_set_msr_common() 2363 msr, data); kvm_set_msr_common() 2373 * Reads an msr value (of 'msr_index') into 'pdata'. 2383 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) get_msr_mtrr() argument 2387 if (!msr_mtrr_valid(msr)) get_msr_mtrr() 2390 if (msr == MSR_MTRRdefType) get_msr_mtrr() 2393 else if (msr == MSR_MTRRfix64K_00000) get_msr_mtrr() 2395 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) get_msr_mtrr() 2396 *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; get_msr_mtrr() 2397 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) get_msr_mtrr() 2398 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; get_msr_mtrr() 2399 else if (msr == MSR_IA32_CR_PAT) get_msr_mtrr() 2405 idx = (msr - 0x200) / 2; get_msr_mtrr() 2406 is_mtrr_mask = msr - 0x200 - 2 * idx; get_msr_mtrr() 2419 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) get_msr_mce() argument 2425 switch (msr) { get_msr_mce() 2442 if (msr >= MSR_IA32_MC0_CTL && get_msr_mce() 2443 msr < MSR_IA32_MCx_CTL(bank_num)) { get_msr_mce() 2444 u32 offset = msr - MSR_IA32_MC0_CTL; get_msr_mce() 2454 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) get_msr_hyperv_pw() argument 2459 switch (msr) { get_msr_hyperv_pw() 2475 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); get_msr_hyperv_pw() 2483 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) get_msr_hyperv() argument 2487 switch (msr) { get_msr_hyperv() 2509 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); get_msr_hyperv() 2516 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) kvm_get_msr_common() argument 2520 switch (msr) { kvm_get_msr_common() 2549 if (kvm_pmu_msr(vcpu, msr)) kvm_get_msr_common() 2550 return kvm_pmu_get_msr(vcpu, msr, pdata); kvm_get_msr_common() 2560 return get_msr_mtrr(vcpu, msr, pdata); kvm_get_msr_common() 2582 return kvm_x2apic_msr_read(vcpu, msr, pdata); kvm_get_msr_common() 2625 return get_msr_mce(vcpu, msr, pdata); kvm_get_msr_common() 2639 if (kvm_hv_msr_partition_wide(msr)) { kvm_get_msr_common() 2642 r = get_msr_hyperv_pw(vcpu, msr, pdata); kvm_get_msr_common() 2646 return get_msr_hyperv(vcpu, msr, pdata); kvm_get_msr_common() 2672 if (kvm_pmu_msr(vcpu, msr)) kvm_get_msr_common() 2673 return kvm_pmu_get_msr(vcpu, msr, pdata); kvm_get_msr_common() 2675 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); kvm_get_msr_common() 2678 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); kvm_get_msr_common() 4957 struct msr_data msr; emulator_set_msr() local 4959 msr.data = data; emulator_set_msr() 4960 msr.index = msr_index; emulator_set_msr() 4961 msr.host_initiated = false; emulator_set_msr() 4962 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); emulator_set_msr() 7116 struct msr_data msr; kvm_arch_vcpu_postcreate() local 7121 msr.data = 0x0; kvm_arch_vcpu_postcreate() 7122 msr.index = MSR_IA32_TSC; kvm_arch_vcpu_postcreate() 7123 msr.host_initiated = true; kvm_arch_vcpu_postcreate() 7124 kvm_write_tsc(vcpu, &msr); kvm_arch_vcpu_postcreate()
H A D	vmx.c	1188 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) __find_msr_index() argument 1193 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) __find_msr_index() 1224 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) find_msr_entry() argument 1228 i = __find_msr_index(vmx, msr); find_msr_entry() 1600 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) clear_atomic_switch_msr() argument 1605 switch (msr) { clear_atomic_switch_msr() 1625 if (m->guest[i].index == msr) clear_atomic_switch_msr() 1648 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, add_atomic_switch_msr() argument 1654 switch (msr) { add_atomic_switch_msr() 1687 if (m->guest[i].index == msr) add_atomic_switch_msr() 1691 printk_once(KERN_WARNING "Not enough msr switch entries. " add_atomic_switch_msr() 1692 "Can't add msr %x\n", msr); add_atomic_switch_msr() 1700 m->guest[i].index = msr; add_atomic_switch_msr() 1702 m->host[i].index = msr; add_atomic_switch_msr() 2639 * Reads an msr value (of 'msr_index') into 'pdata'. 2646 struct shared_msr_entry *msr; vmx_get_msr() local 2704 msr = find_msr_entry(to_vmx(vcpu), msr_index); vmx_get_msr() 2705 if (msr) { vmx_get_msr() 2706 data = msr->data; vmx_get_msr() 2719 * Writes msr value into into the appropriate "register". 2726 struct shared_msr_entry *msr; vmx_set_msr() local 2814 msr = find_msr_entry(vmx, msr_index); vmx_set_msr() 2815 if (msr) { vmx_set_msr() 2816 u64 old_msr_data = msr->data; vmx_set_msr() 2817 msr->data = data; vmx_set_msr() 2818 if (msr - vmx->guest_msrs < vmx->save_nmsrs) { vmx_set_msr() 2820 ret = kvm_set_shared_msr(msr->index, msr->data, vmx_set_msr() 2821 msr->mask); vmx_set_msr() 2824 msr->data = old_msr_data; vmx_set_msr() 2860 u64 msr; vmx_disabled_by_bios() local 2862 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); vmx_disabled_by_bios() 2863 if (msr & FEATURE_CONTROL_LOCKED) { vmx_disabled_by_bios() 2865 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) vmx_disabled_by_bios() 2869 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) vmx_disabled_by_bios() 2870 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) vmx_disabled_by_bios() 2877 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) vmx_disabled_by_bios() 2966 u32 msr, u32 *result) adjust_vmx_controls() 2971 rdmsr(msr, vmx_msr_low, vmx_msr_high); adjust_vmx_controls() 2984 static __init bool allow_1_setting(u32 msr, u32 ctl) allow_1_setting() argument 2988 rdmsr(msr, vmx_msr_low, vmx_msr_high); allow_1_setting() 3139 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL. setup_vmcs_config() 3420 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); vmx_set_efer() local 3422 if (!msr) vmx_set_efer() 3427 * of this msr depends on is_long_mode(). vmx_set_efer() 3433 msr->data = efer; vmx_set_efer() 3437 msr->data = efer & ~EFER_LME; vmx_set_efer() 4213 u32 msr, int type) __vmx_disable_intercept_for_msr() 4225 if (msr <= 0x1fff) { __vmx_disable_intercept_for_msr() 4228 __clear_bit(msr, msr_bitmap + 0x000 / f); __vmx_disable_intercept_for_msr() 4232 __clear_bit(msr, msr_bitmap + 0x800 / f); __vmx_disable_intercept_for_msr() 4234 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { __vmx_disable_intercept_for_msr() 4235 msr &= 0x1fff; __vmx_disable_intercept_for_msr() 4238 __clear_bit(msr, msr_bitmap + 0x400 / f); __vmx_disable_intercept_for_msr() 4242 __clear_bit(msr, msr_bitmap + 0xc00 / f); __vmx_disable_intercept_for_msr() 4248 u32 msr, int type) __vmx_enable_intercept_for_msr() 4260 if (msr <= 0x1fff) { __vmx_enable_intercept_for_msr() 4263 __set_bit(msr, msr_bitmap + 0x000 / f); __vmx_enable_intercept_for_msr() 4267 __set_bit(msr, msr_bitmap + 0x800 / f); __vmx_enable_intercept_for_msr() 4269 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { __vmx_enable_intercept_for_msr() 4270 msr &= 0x1fff; __vmx_enable_intercept_for_msr() 4273 __set_bit(msr, msr_bitmap + 0x400 / f); __vmx_enable_intercept_for_msr() 4277 __set_bit(msr, msr_bitmap + 0xc00 / f); __vmx_enable_intercept_for_msr() 4283 * If a msr is allowed by L0, we should check whether it is allowed by L1. 4288 u32 msr, int type) nested_vmx_disable_intercept_for_msr() 4302 if (msr <= 0x1fff) { nested_vmx_disable_intercept_for_msr() 4304 !test_bit(msr, msr_bitmap_l1 + 0x000 / f)) nested_vmx_disable_intercept_for_msr() 4306 __clear_bit(msr, msr_bitmap_nested + 0x000 / f); nested_vmx_disable_intercept_for_msr() 4309 !test_bit(msr, msr_bitmap_l1 + 0x800 / f)) nested_vmx_disable_intercept_for_msr() 4311 __clear_bit(msr, msr_bitmap_nested + 0x800 / f); nested_vmx_disable_intercept_for_msr() 4313 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { nested_vmx_disable_intercept_for_msr() 4314 msr &= 0x1fff; nested_vmx_disable_intercept_for_msr() 4316 !test_bit(msr, msr_bitmap_l1 + 0x400 / f)) nested_vmx_disable_intercept_for_msr() 4318 __clear_bit(msr, msr_bitmap_nested + 0x400 / f); nested_vmx_disable_intercept_for_msr() 4321 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f)) nested_vmx_disable_intercept_for_msr() 4323 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f); nested_vmx_disable_intercept_for_msr() 4328 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) vmx_disable_intercept_for_msr() argument 4332 msr, MSR_TYPE_R | MSR_TYPE_W); vmx_disable_intercept_for_msr() 4334 msr, MSR_TYPE_R | MSR_TYPE_W); vmx_disable_intercept_for_msr() 4337 static void vmx_enable_intercept_msr_read_x2apic(u32 msr) vmx_enable_intercept_msr_read_x2apic() argument 4340 msr, MSR_TYPE_R); vmx_enable_intercept_msr_read_x2apic() 4342 msr, MSR_TYPE_R); vmx_enable_intercept_msr_read_x2apic() 4345 static void vmx_disable_intercept_msr_read_x2apic(u32 msr) vmx_disable_intercept_msr_read_x2apic() argument 4348 msr, MSR_TYPE_R); vmx_disable_intercept_msr_read_x2apic() 4350 msr, MSR_TYPE_R); vmx_disable_intercept_msr_read_x2apic() 4353 static void vmx_disable_intercept_msr_write_x2apic(u32 msr) vmx_disable_intercept_msr_write_x2apic() argument 4356 msr, MSR_TYPE_W); vmx_disable_intercept_msr_write_x2apic() 4358 msr, MSR_TYPE_W); vmx_disable_intercept_msr_write_x2apic() 5518 struct msr_data msr; handle_wrmsr() local 5523 msr.data = data; handle_wrmsr() 5524 msr.index = ecx; handle_wrmsr() 5525 msr.host_initiated = false; handle_wrmsr() 5526 if (kvm_set_msr(vcpu, &msr) != 0) { handle_wrmsr() 6030 int r = -ENOMEM, i, msr; hardware_setup() local 6171 for (msr = 0x800; msr <= 0x8ff; msr++) hardware_setup() 6172 vmx_disable_intercept_msr_read_x2apic(msr); hardware_setup() 8160 clear_atomic_switch_msr(vmx, msrs[i].msr); atomic_switch_perf_msrs() 8162 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, atomic_switch_perf_msrs() 8786 int msr; nested_vmx_merge_msr_bitmap() local 8807 for (msr = 0x800; msr <= 0x8ff; msr++) nested_vmx_merge_msr_bitmap() 8811 msr, MSR_TYPE_R); nested_vmx_merge_msr_bitmap() 8837 for (msr = 0x800; msr <= 0x8ff; msr++) nested_vmx_merge_msr_bitmap() 8840 msr, nested_vmx_merge_msr_bitmap() 8982 * Load guest's/host's msr at nested entry/exit. 8989 struct msr_data msr; nested_vmx_load_msr() local 8991 msr.host_initiated = false; nested_vmx_load_msr() 9006 msr.index = e.index; nested_vmx_load_msr() 9007 msr.data = e.value; nested_vmx_load_msr() 9008 if (kvm_set_msr(vcpu, &msr)) { nested_vmx_load_msr() 2965 adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, u32 msr, u32 *result) adjust_vmx_controls() argument 4212 __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr, int type) __vmx_disable_intercept_for_msr() argument 4247 __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr, int type) __vmx_enable_intercept_for_msr() argument 4286 nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1, unsigned long *msr_bitmap_nested, u32 msr, int type) nested_vmx_disable_intercept_for_msr() argument
H A D	x86.h	153 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr); 163 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
H A D	svm.c	426 static u32 svm_msrpm_offset(u32 msr) svm_msrpm_offset() argument 432 if (msr < msrpm_ranges[i] || svm_msrpm_offset() 433 msr >= msrpm_ranges[i] + MSRS_IN_RANGE) svm_msrpm_offset() 436 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ svm_msrpm_offset() 762 static void set_msr_interception(u32 *msrpm, unsigned msr, set_msr_interception() argument 773 WARN_ON(!valid_msr_intercept(msr)); set_msr_interception() 775 offset = svm_msrpm_offset(msr); set_msr_interception() 776 bit_read = 2 * (msr & 0x0f); set_msr_interception() 777 bit_write = 2 * (msr & 0x0f) + 1; set_msr_interception() 2164 u32 offset, msr, value; nested_svm_exit_handled_msr() local 2170 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; nested_svm_exit_handled_msr() 2171 offset = svm_msrpm_offset(msr); nested_svm_exit_handled_msr() 2173 mask = 1 << ((2 * (msr & 0xf)) + write); nested_svm_exit_handled_msr() 2433 * This function merges the msr permission bitmaps of kvm and the nested_svm_vmrun_msrpm() 2435 * the kvm msr permission bitmap may contain zero bits nested_svm_vmrun_msrpm() 3188 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) svm_set_msr() argument 3192 u32 ecx = msr->index; svm_set_msr() 3193 u64 data = msr->data; svm_set_msr() 3196 kvm_write_tsc(vcpu, msr); svm_set_msr() 3251 return kvm_set_msr_common(vcpu, msr); svm_set_msr() 3258 struct msr_data msr; wrmsr_interception() local 3262 msr.data = data; wrmsr_interception() 3263 msr.index = ecx; wrmsr_interception() 3264 msr.host_initiated = false; wrmsr_interception() 3267 if (kvm_set_msr(&svm->vcpu, &msr)) { wrmsr_interception()
/linux-4.1.27/drivers/tty/serial/
H A D	vr41xx_siu.c	223 uint8_t msr; siu_get_mctrl() local 226 msr = siu_read(port, UART_MSR); siu_get_mctrl() 227 if (msr & UART_MSR_DCD) siu_get_mctrl() 229 if (msr & UART_MSR_RI) siu_get_mctrl() 231 if (msr & UART_MSR_DSR) siu_get_mctrl() 233 if (msr & UART_MSR_CTS) siu_get_mctrl() 373 uint8_t msr; check_modem_status() local 375 msr = siu_read(port, UART_MSR); check_modem_status() 376 if ((msr & UART_MSR_ANY_DELTA) == 0) check_modem_status() 378 if (msr & UART_MSR_DDCD) check_modem_status() 379 uart_handle_dcd_change(port, msr & UART_MSR_DCD); check_modem_status() 380 if (msr & UART_MSR_TERI) check_modem_status() 382 if (msr & UART_MSR_DDSR) check_modem_status() 384 if (msr & UART_MSR_DCTS) check_modem_status() 385 uart_handle_cts_change(port, msr & UART_MSR_CTS); check_modem_status() 741 uint8_t lsr, msr; wait_for_xmitr() local 756 msr = siu_read(port, UART_MSR); wait_for_xmitr() 757 if ((msr & UART_MSR_CTS) != 0) wait_for_xmitr()
H A D	men_z135_uart.c	187 u8 msr; men_z135_handle_modem_status() local 189 msr = (uart->stat_reg >> 8) & 0xff; men_z135_handle_modem_status() 191 if (msr & MEN_Z135_MSR_DDCD) men_z135_handle_modem_status() 193 msr & MEN_Z135_MSR_DCD); men_z135_handle_modem_status() 194 if (msr & MEN_Z135_MSR_DCTS) men_z135_handle_modem_status() 196 msr & MEN_Z135_MSR_CTS); men_z135_handle_modem_status() 528 u8 msr; men_z135_get_mctrl() local 530 msr = ioread8(port->membase + MEN_Z135_STAT_REG + 1); men_z135_get_mctrl() 532 if (msr & MEN_Z135_MSR_CTS) men_z135_get_mctrl() 534 if (msr & MEN_Z135_MSR_DSR) men_z135_get_mctrl() 536 if (msr & MEN_Z135_MSR_RI) men_z135_get_mctrl() 538 if (msr & MEN_Z135_MSR_DCD) men_z135_get_mctrl()
H A D	serial-tegra.c	650 unsigned long msr; tegra_uart_handle_modem_signal_change() local 652 msr = tegra_uart_read(tup, UART_MSR); tegra_uart_handle_modem_signal_change() 653 if (!(msr & UART_MSR_ANY_DELTA)) tegra_uart_handle_modem_signal_change() 656 if (msr & UART_MSR_TERI) tegra_uart_handle_modem_signal_change() 658 if (msr & UART_MSR_DDSR) tegra_uart_handle_modem_signal_change() 661 if (msr & UART_MSR_DDCD) tegra_uart_handle_modem_signal_change() 662 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); tegra_uart_handle_modem_signal_change() 664 if (msr & UART_MSR_DCTS) tegra_uart_handle_modem_signal_change() 665 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); tegra_uart_handle_modem_signal_change() 784 unsigned long msr; tegra_uart_hw_deinit() local 792 msr = tegra_uart_read(tup, UART_MSR); tegra_uart_hw_deinit() 794 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS)) tegra_uart_hw_deinit() 804 msr = tegra_uart_read(tup, UART_MSR); tegra_uart_hw_deinit() 807 (msr & UART_MSR_CTS)) tegra_uart_hw_deinit()
H A D	pnx8xxx_uart.c	331 unsigned int msr; pnx8xxx_get_mctrl() local 335 msr = serial_in(sport, PNX8XXX_MCR); pnx8xxx_get_mctrl() 337 mctrl |= msr & PNX8XXX_UART_MCR_CTS ? TIOCM_CTS : 0; pnx8xxx_get_mctrl() 338 mctrl |= msr & PNX8XXX_UART_MCR_DCD ? TIOCM_CAR : 0; pnx8xxx_get_mctrl() 347 unsigned int msr; pnx8xxx_set_mctrl()
/linux-4.1.27/arch/powerpc/sysdev/
H A D	uic.c	202 u32 msr; uic_irq_cascade() local 213 msr = mfdcr(uic->dcrbase + UIC_MSR); uic_irq_cascade() 214 if (!msr) /* spurious interrupt */ uic_irq_cascade() 217 src = 32 - ffs(msr); uic_irq_cascade() 325 u32 msr; uic_get_irq() local 330 msr = mfdcr(primary_uic->dcrbase + UIC_MSR); uic_get_irq() 331 src = 32 - ffs(msr); uic_get_irq()
/linux-4.1.27/drivers/usb/serial/
H A D	mct_u232.c	310 unsigned char *msr) mct_u232_get_modem_stat() 317 *msr = 0; mct_u232_get_modem_stat() 327 *msr = 0; mct_u232_get_modem_stat() 329 *msr = buf[0]; mct_u232_get_modem_stat() 331 dev_dbg(&port->dev, "get_modem_stat: 0x%x\n", *msr); mct_u232_get_modem_stat() 337 unsigned char msr) mct_u232_msr_to_icount() 340 if (msr & MCT_U232_MSR_DDSR) mct_u232_msr_to_icount() 342 if (msr & MCT_U232_MSR_DCTS) mct_u232_msr_to_icount() 344 if (msr & MCT_U232_MSR_DRI) mct_u232_msr_to_icount() 346 if (msr & MCT_U232_MSR_DCD) mct_u232_msr_to_icount() 351 unsigned int *control_state, unsigned char msr) mct_u232_msr_to_state() 354 if (msr & MCT_U232_MSR_DSR) mct_u232_msr_to_state() 358 if (msr & MCT_U232_MSR_CTS) mct_u232_msr_to_state() 362 if (msr & MCT_U232_MSR_RI) mct_u232_msr_to_state() 366 if (msr & MCT_U232_MSR_CD) mct_u232_msr_to_state() 370 dev_dbg(&port->dev, "msr_to_state: msr=0x%x ==> state=0x%x\n", msr, *control_state); mct_u232_msr_to_state() 309 mct_u232_get_modem_stat(struct usb_serial_port *port, unsigned char *msr) mct_u232_get_modem_stat() argument 336 mct_u232_msr_to_icount(struct async_icount *icount, unsigned char msr) mct_u232_msr_to_icount() argument 350 mct_u232_msr_to_state(struct usb_serial_port *port, unsigned int *control_state, unsigned char msr) mct_u232_msr_to_state() argument
H A D	f81232.c	233 case 0x00: /* msr change */ f81232_update_line_status() 505 u8 mcr, msr; f81232_tiocmget() local 512 msr = port_priv->modem_status; f81232_tiocmget() 517 (msr & UART_MSR_CTS ? TIOCM_CTS : 0) | f81232_tiocmget() 518 (msr & UART_MSR_DCD ? TIOCM_CAR : 0) | f81232_tiocmget() 519 (msr & UART_MSR_RI ? TIOCM_RI : 0) | f81232_tiocmget() 520 (msr & UART_MSR_DSR ? TIOCM_DSR : 0); f81232_tiocmget() 578 u8 msr; f81232_carrier_raised() local 582 msr = priv->modem_status; f81232_carrier_raised() 585 if (msr & UART_MSR_DCD) f81232_carrier_raised()
H A D	ti_usb_3410_5052.c	123 static void ti_handle_new_msr(struct ti_port *tport, __u8 msr); 842 unsigned int msr; ti_tiocmget() local 850 msr = tport->tp_msr; ti_tiocmget() 857 | ((msr & TI_MSR_CTS) ? TIOCM_CTS : 0) ti_tiocmget() 858 | ((msr & TI_MSR_CD) ? TIOCM_CAR : 0) ti_tiocmget() 859 | ((msr & TI_MSR_RI) ? TIOCM_RI : 0) ti_tiocmget() 860 | ((msr & TI_MSR_DSR) ? TIOCM_DSR : 0); ti_tiocmget() 934 __u8 msr; ti_interrupt_callback() local 986 msr = data[1]; ti_interrupt_callback() 987 dev_dbg(dev, "%s - port %d, msr 0x%02X\n", __func__, port_number, msr); ti_interrupt_callback() 988 ti_handle_new_msr(tport, msr); ti_interrupt_callback() 1267 static void ti_handle_new_msr(struct ti_port *tport, __u8 msr) ti_handle_new_msr() argument 1273 dev_dbg(&tport->tp_port->dev, "%s - msr 0x%02X\n", __func__, msr); ti_handle_new_msr() 1275 if (msr & TI_MSR_DELTA_MASK) { ti_handle_new_msr() 1278 if (msr & TI_MSR_DELTA_CTS) ti_handle_new_msr() 1280 if (msr & TI_MSR_DELTA_DSR) ti_handle_new_msr() 1282 if (msr & TI_MSR_DELTA_CD) ti_handle_new_msr() 1284 if (msr & TI_MSR_DELTA_RI) ti_handle_new_msr() 1290 tport->tp_msr = msr & TI_MSR_MASK; ti_handle_new_msr() 1295 if (msr & TI_MSR_CTS) ti_handle_new_msr()
H A D	ssu100.c	441 static void ssu100_update_msr(struct usb_serial_port *port, u8 msr) ssu100_update_msr() argument 447 priv->shadowMSR = msr; ssu100_update_msr() 450 if (msr & UART_MSR_ANY_DELTA) { ssu100_update_msr() 452 if (msr & UART_MSR_DCTS) ssu100_update_msr() 454 if (msr & UART_MSR_DDSR) ssu100_update_msr() 456 if (msr & UART_MSR_DDCD) ssu100_update_msr() 458 if (msr & UART_MSR_TERI) ssu100_update_msr()
H A D	ark3116.c	77 __u32 msr; /* modem status register value */ member in struct:ark3116_private 376 priv->msr = ark3116_read_reg(serial, UART_MSR, buf); ark3116_open() 446 status = priv->msr; ark3116_tiocmget() 513 static void ark3116_update_msr(struct usb_serial_port *port, __u8 msr) ark3116_update_msr() argument 519 priv->msr = msr; ark3116_update_msr() 522 if (msr & UART_MSR_ANY_DELTA) { ark3116_update_msr() 524 if (msr & UART_MSR_DCTS) ark3116_update_msr() 526 if (msr & UART_MSR_DDSR) ark3116_update_msr() 528 if (msr & UART_MSR_DDCD) ark3116_update_msr() 530 if (msr & UART_MSR_TERI) ark3116_update_msr() 583 dev_dbg(&port->dev, "%s: msr=%02x\n", ark3116_read_int_callback()
H A D	io_ti.c	1430 static void handle_new_msr(struct edgeport_port *edge_port, __u8 msr) handle_new_msr() argument 1435 dev_dbg(&edge_port->port->dev, "%s - %02x\n", __func__, msr); handle_new_msr() 1437 if (msr & (EDGEPORT_MSR_DELTA_CTS | EDGEPORT_MSR_DELTA_DSR | handle_new_msr() 1442 if (msr & EDGEPORT_MSR_DELTA_CTS) handle_new_msr() 1444 if (msr & EDGEPORT_MSR_DELTA_DSR) handle_new_msr() 1446 if (msr & EDGEPORT_MSR_DELTA_CD) handle_new_msr() 1448 if (msr & EDGEPORT_MSR_DELTA_RI) handle_new_msr() 1454 edge_port->shadow_msr = msr & 0xf0; handle_new_msr() 1459 if (msr & EDGEPORT_MSR_CTS) handle_new_msr() 1512 __u8 msr; edge_interrupt_callback() local 1574 msr = data[1]; edge_interrupt_callback() 1576 __func__, port_number, msr); edge_interrupt_callback() 1577 handle_new_msr(edge_port, msr); edge_interrupt_callback() 2294 unsigned int msr; edge_tiocmget() local 2300 msr = edge_port->shadow_msr; edge_tiocmget() 2304 | ((msr & EDGEPORT_MSR_CTS) ? TIOCM_CTS: 0) /* 0x020 */ edge_tiocmget() 2305 | ((msr & EDGEPORT_MSR_CD) ? TIOCM_CAR: 0) /* 0x040 */ edge_tiocmget() 2306 | ((msr & EDGEPORT_MSR_RI) ? TIOCM_RI: 0) /* 0x080 */ edge_tiocmget() 2307 | ((msr & EDGEPORT_MSR_DSR) ? TIOCM_DSR: 0); /* 0x100 */ edge_tiocmget()
H A D	spcp8x5.c	252 u8 msr; spcp8x5_carrier_raised() local 255 ret = spcp8x5_get_msr(port, &msr); spcp8x5_carrier_raised() 256 if (ret || msr & MSR_STATUS_LINE_DCD) spcp8x5_carrier_raised()
/linux-4.1.27/arch/x86/kernel/cpu/mcheck/
H A D	winchip.c	13 #include <asm/msr.h>
H A D	p5.c	14 #include <asm/msr.h>
H A D	mce.c	49 #include <asm/msr.h> 373 static int msr_to_offset(u32 msr) msr_to_offset() argument 377 if (msr == mca_cfg.rip_msr) msr_to_offset() 379 if (msr == MSR_IA32_MCx_STATUS(bank)) msr_to_offset() 381 if (msr == MSR_IA32_MCx_ADDR(bank)) msr_to_offset() 383 if (msr == MSR_IA32_MCx_MISC(bank)) msr_to_offset() 385 if (msr == MSR_IA32_MCG_STATUS) msr_to_offset() 391 static u64 mce_rdmsrl(u32 msr) mce_rdmsrl() argument 396 int offset = msr_to_offset(msr); mce_rdmsrl() 403 if (rdmsrl_safe(msr, &v)) { mce_rdmsrl() 404 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); mce_rdmsrl() 416 static void mce_wrmsrl(u32 msr, u64 v) mce_wrmsrl() argument 419 int offset = msr_to_offset(msr); mce_wrmsrl() 425 wrmsrl(msr, v); mce_wrmsrl() 1249 * MSR_IA32_THERMAL_STATUS (Intel) msr.
H A D	mce_amd.c	34 #include <asm/msr.h> 119 int msr = (hi & MASK_LVTOFF_HI) >> 20; lvt_off_valid() local 128 if (apic != msr) { lvt_off_valid()
/linux-4.1.27/arch/mips/pci/
H A D	ops-loongson2.c	185 void _rdmsr(u32 msr, u32 *hi, u32 *lo) _rdmsr() argument 194 loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr); _rdmsr() 201 void _wrmsr(u32 msr, u32 hi, u32 lo) _wrmsr() argument 210 loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr); _wrmsr()
/linux-4.1.27/arch/arm/lib/
H A D	ecard.S	18 msr spsr_cxsf, rt
/linux-4.1.27/drivers/staging/dgnc/
H A D	dgnc_cls.h	35 * msr : WR MSG - Modem Status Reg 45 u8 msr; member in struct:cls_uart_struct
H A D	dgnc_neo.h	37 u8 msr; /* WR MSR - Modem Status Reg */ member in struct:neo_uart_struct
/linux-4.1.27/arch/arm/mach-ep93xx/
H A D	crunch-bits.S	214 msr cpsr_c, r2 246 1: msr cpsr_c, ip @ restore interrupt mode 260 msr cpsr_c, r2 269 msr cpsr_c, ip @ restore interrupt mode 279 msr cpsr_c, ip @ restore interrupt mode 293 msr cpsr_c, r2 302 msr cpsr_c, ip @ restore interrupt mode 312 msr cpsr_c, ip @ restore interrupt mode
/linux-4.1.27/tools/power/cpupower/utils/helpers/
H A D	msr.c	31 sprintf(msr_file_name, "/dev/cpu/%d/msr", cpu); read_msr() 60 sprintf(msr_file_name, "/dev/cpu/%d/msr", cpu); write_msr()
H A D	helpers.h	125 /* Read/Write msr ****************************/ 133 /* Read/Write msr ****************************/ 181 /* Read/Write msr ****************************/
/linux-4.1.27/drivers/i2c/busses/
H A D	i2c-rcar.c	268 static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) rcar_i2c_irq_send() argument 277 if (!(msr & MDE)) rcar_i2c_irq_send() 284 if (msr & MAT) rcar_i2c_irq_send() 329 static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) rcar_i2c_irq_recv() argument 338 if (!(msr & MDR)) rcar_i2c_irq_recv() 341 if (msr & MAT) { rcar_i2c_irq_recv() 429 u32 msr; rcar_i2c_irq() local 437 msr = rcar_i2c_read(priv, ICMSR); rcar_i2c_irq() 440 msr &= rcar_i2c_read(priv, ICMIER); rcar_i2c_irq() 441 if (!msr) { rcar_i2c_irq() 447 if (msr & MAL) { rcar_i2c_irq() 453 if (msr & MNR) { rcar_i2c_irq() 462 if (msr & MST) { rcar_i2c_irq() 468 rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr)); rcar_i2c_irq() 470 rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr)); rcar_i2c_irq()
H A D	i2c-sh7760.c	117 unsigned long msr, fsr, fier, len; sh7760_i2c_irq() local 119 msr = IN32(id, I2CMSR); sh7760_i2c_irq() 123 if (msr & MSR_MAL) { sh7760_i2c_irq() 131 if (msr & MSR_MNR) { sh7760_i2c_irq() 146 msr &= ~MSR_MAT; sh7760_i2c_irq() 152 if (msr & MSR_MST) { sh7760_i2c_irq() 158 if (msr & MSR_MAT) sh7760_i2c_irq() 231 OUT32(id, I2CMSR, ~msr); sh7760_i2c_irq()
/linux-4.1.27/drivers/powercap/
H A D	intel_rapl.c	702 /* name, mask, shift, msr index, unit divisor */ 759 u32 msr; rapl_read_data_raw() local 766 msr = rd->msrs[rp->id]; rapl_read_data_raw() 767 if (!msr) rapl_read_data_raw() 785 if (rdmsrl_safe_on_cpu(cpu, msr, &value)) { rapl_read_data_raw() 786 pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu); rapl_read_data_raw() 806 u32 msr; rapl_write_data_raw() local 813 msr = rd->msrs[rp->id]; rapl_write_data_raw() 814 if (rdmsrl_safe_on_cpu(cpu, msr, &msr_val)) { rapl_write_data_raw() 816 "failed to read msr 0x%x on cpu %d\n", msr, cpu); rapl_write_data_raw() 822 if (wrmsrl_safe_on_cpu(cpu, msr, msr_val)) { rapl_write_data_raw() 824 "failed to write msr 0x%x on cpu %d\n", msr, cpu); rapl_write_data_raw() 1242 unsigned msr; rapl_check_domain() local 1247 msr = MSR_PKG_ENERGY_STATUS; rapl_check_domain() 1250 msr = MSR_PP0_ENERGY_STATUS; rapl_check_domain() 1253 msr = MSR_PP1_ENERGY_STATUS; rapl_check_domain() 1256 msr = MSR_DRAM_ENERGY_STATUS; rapl_check_domain() 1265 if (rdmsrl_safe_on_cpu(cpu, msr, &val) || !val) rapl_check_domain()
/linux-4.1.27/ipc/
H A D	msg.c	188 struct msg_receiver *msr, *t; expunge_all() local 190 list_for_each_entry_safe(msr, t, &msq->q_receivers, r_list) { expunge_all() 191 msr->r_msg = NULL; /* initialize expunge ordering */ expunge_all() 192 wake_up_process(msr->r_tsk); expunge_all() 200 msr->r_msg = ERR_PTR(res); expunge_all() 571 struct msg_receiver *msr, *t; pipelined_send() local 573 list_for_each_entry_safe(msr, t, &msq->q_receivers, r_list) { pipelined_send() 574 if (testmsg(msg, msr->r_msgtype, msr->r_mode) && pipelined_send() 575 !security_msg_queue_msgrcv(msq, msg, msr->r_tsk, pipelined_send() 576 msr->r_msgtype, msr->r_mode)) { pipelined_send() 578 list_del(&msr->r_list); pipelined_send() 579 if (msr->r_maxsize < msg->m_ts) { pipelined_send() 581 msr->r_msg = NULL; pipelined_send() 582 wake_up_process(msr->r_tsk); pipelined_send() 584 msr->r_msg = ERR_PTR(-E2BIG); pipelined_send() 586 msr->r_msg = NULL; pipelined_send() 587 msq->q_lrpid = task_pid_vnr(msr->r_tsk); pipelined_send() 589 wake_up_process(msr->r_tsk); pipelined_send() 597 msr->r_msg = msg; pipelined_send()
/linux-4.1.27/drivers/video/fbdev/i810/
H A D	i810_gtf.c	129 u8 msr = 0; i810fb_encode_registers() local 191 msr |= 1 << 6; i810fb_encode_registers() 193 msr |= 1 << 7; i810fb_encode_registers() 194 par->regs.msr = msr; i810fb_encode_registers()
H A D	i810.h	222 u8 msr; member in struct:mode_registers 242 u8 cr39, cr41, cr70, sr01, msr; member in struct:state_registers
/linux-4.1.27/drivers/ssb/
H A D	driver_extif.c	43 u8 save_mcr, msr = 0; serial_exists() local 48 msr = regs[UART_MSR] & (UART_MSR_DCD | UART_MSR_RI serial_exists() 52 return (msr == (UART_MSR_DCD | UART_MSR_CTS)); serial_exists()
/linux-4.1.27/drivers/misc/
H A D	cs5535-mfgpt.c	50 uint32_t msr, mask, value, dummy; cs5535_mfgpt_toggle_event() local 69 msr = MSR_MFGPT_NR; cs5535_mfgpt_toggle_event() 74 msr = MSR_MFGPT_NR; cs5535_mfgpt_toggle_event() 79 msr = MSR_MFGPT_IRQ; cs5535_mfgpt_toggle_event() 87 rdmsr(msr, value, dummy); cs5535_mfgpt_toggle_event() 94 wrmsr(msr, value, dummy); cs5535_mfgpt_toggle_event()
/linux-4.1.27/drivers/ide/
H A D	cs5536.c	29 * driver can be loaded with the "msr=1" parameter which forces using 38 #include <asm/msr.h> 305 module_param_named(msr, use_msr, int, 0644); 306 MODULE_PARM_DESC(msr, "Force using MSR to configure IDE function (Default: 0)");
/linux-4.1.27/arch/x86/platform/efi/
H A D	efi_stub_64.S	11 #include <asm/msr.h>
/linux-4.1.27/arch/x86/platform/olpc/
H A D	olpc-xo1-rtc.c	17 #include <asm/msr.h>
/linux-4.1.27/arch/microblaze/include/uapi/asm/
H A D	ptrace.h	50 microblaze_reg_t msr; member in struct:pt_regs
/linux-4.1.27/drivers/ata/
H A D	pata_cs5536.c	29 * driver can be loaded with the "msr=1" parameter which forces using 43 #include <asm/msr.h> 45 module_param_named(msr, use_msr, int, 0644); 46 MODULE_PARM_DESC(msr, "Force using MSR to configure IDE function (Default: 0)");
/linux-4.1.27/arch/powerpc/kernel/vdso32/
H A D	sigtramp.S	69 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16 87 .uleb128 33*RSIZE; /* msr offset */ \ 101 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16 112 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
/linux-4.1.27/arch/powerpc/kernel/vdso64/
H A D	sigtramp.S	68 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16 86 .uleb128 33*RSIZE; /* msr offset */ \ 101 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16 112 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
/linux-4.1.27/tools/perf/arch/powerpc/util/
H A D	dwarf-regs.c	64 REG_DWARFNUM_NAME("%msr", 66),
/linux-4.1.27/drivers/net/hamradio/
H A D	baycom_ser_fdx.c	291 unsigned char iir, msr; ser12_interrupt() local 301 msr = inb(MSR(dev->base_addr)); ser12_interrupt() 303 if ((msr & 8) && bc->opt_dcd) ser12_interrupt() 304 hdlcdrv_setdcd(&bc->hdrv, !((msr ^ bc->opt_dcd) & 0x80)); ser12_interrupt() 335 msr = inb(MSR(dev->base_addr)); ser12_interrupt() 337 if ((msr & 8) && bc->opt_dcd) ser12_interrupt() 338 hdlcdrv_setdcd(&bc->hdrv, !((msr ^ bc->opt_dcd) & 0x80)); ser12_interrupt() 343 ser12_rx(dev, bc, &tv, msr & 0x10); /* CTS */ ser12_interrupt()
/linux-4.1.27/arch/x86/kernel/cpu/mtrr/
H A D	generic.c	16 #include <asm/msr.h> 454 void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b) mtrr_wrmsr() argument 456 if (wrmsr_safe(msr, a, b) < 0) { mtrr_wrmsr() 459 smp_processor_id(), msr, a, b); mtrr_wrmsr() 466 * @msr: MSR address of the MTTR which should be checked and updated 470 static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords) set_fixed_range() argument 474 rdmsr(msr, lo, hi); set_fixed_range() 477 mtrr_wrmsr(msr, msrwords[0], msrwords[1]); set_fixed_range()
H A D	centaur.c	5 #include <asm/msr.h>
H A D	amd.c	4 #include <asm/msr.h>
H A D	cyrix.c	8 #include <asm/msr.h>
/linux-4.1.27/arch/arm/mm/
H A D	proc-feroceon.S	264 msr cpsr_c, r3 @ disable interrupts 267 msr cpsr_c, r2 @ restore interrupts 310 msr cpsr_c, r3 @ disable interrupts 313 msr cpsr_c, r2 @ restore interrupts 342 msr cpsr_c, r3 @ disable interrupts 345 msr cpsr_c, r2 @ restore interrupts 373 msr cpsr_c, r3 @ disable interrupts 376 msr cpsr_c, r2 @ restore interrupts
/linux-4.1.27/tools/power/cpupower/utils/
H A D	cpupower.c	206 stat("/dev/cpu/0/msr", &statbuf) != 0) { main() 207 if (system("modprobe msr") == -1) main()
/linux-4.1.27/arch/x86/boot/
H A D	cpuflags.c	6 #include <asm/msr-index.h>
/linux-4.1.27/arch/m68k/include/asm/
H A D	bvme6000hw.h	50 pad_a[3], msr, member in struct:__anon1786
/linux-4.1.27/arch/arm/mach-s3c64xx/
H A D	sleep.S	43 msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
/linux-4.1.27/arch/arm/probes/kprobes/
H A D	actions-arm.c	181 "msr cpsr_fs, %[cpsr] \n\t" emulate_rd12rn16rm0rs8_rwflags() 211 "msr cpsr_fs, %[cpsr] \n\t" emulate_rd12rn16rm0_rwflags_nopc() 241 "msr cpsr_fs, %[cpsr] \n\t" emulate_rd16rn12rm0rs8_rwflags_nopc() 291 "msr cpsr_fs, %[cpsr] \n\t" emulate_rdlo12rdhi16rn0rm8_rwflags_nopc()
/linux-4.1.27/arch/x86/pci/
H A D	mmconfig-shared.c	190 u64 base, msr; pci_mmcfg_amd_fam10h() local 201 msr = high; pci_mmcfg_amd_fam10h() 202 msr <<= 32; pci_mmcfg_amd_fam10h() 203 msr |= low; pci_mmcfg_amd_fam10h() 206 if (!(msr & FAM10H_MMIO_CONF_ENABLE)) pci_mmcfg_amd_fam10h() 209 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); pci_mmcfg_amd_fam10h() 211 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & pci_mmcfg_amd_fam10h()
/linux-4.1.27/net/mac80211/
H A D	rc80211_minstrel.c	340 struct minstrel_rate *msr, *mr; minstrel_get_rate() local 396 msr = &mi->r[ndx]; minstrel_get_rate() 404 msr->perfect_tx_time > mr->perfect_tx_time && minstrel_get_rate() 405 msr->stats.sample_skipped < 20) { minstrel_get_rate() 416 if (!msr->sample_limit) minstrel_get_rate() 420 if (msr->sample_limit > 0) minstrel_get_rate() 421 msr->sample_limit--; minstrel_get_rate()
/linux-4.1.27/arch/powerpc/xmon/
H A D	xmon.c	398 return ((regs->msr & MSR_RI) == 0); unrecoverable_excp() 453 if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) == (MSR_IR|MSR_64BIT)) xmon_core() 577 if (regs->msr & MSR_DE) { xmon_core() 585 if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) == (MSR_IR|MSR_64BIT)) { xmon_core() 635 if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) != (MSR_IR|MSR_64BIT)) xmon_bpt() 666 if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) != (MSR_IR|MSR_64BIT)) xmon_break_match() 676 if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) != (MSR_IR|MSR_64BIT)) xmon_iabr_match() 701 if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) == (MSR_IR|MSR_64BIT)) { xmon_fault_handler() 974 regs->msr |= MSR_DE; do_step() 989 if ((regs->msr & (MSR_64BIT|MSR_PR|MSR_IR)) == (MSR_64BIT|MSR_IR)) { do_step() 1006 regs->msr |= MSR_SE; do_step() 1454 if (regs->msr & MSR_PR) print_bug_trap() 1491 printf(" msr: %lx\n", fp->msr); excprint() 1564 printf("msr = "REG" cr = %.8lx\n", fp->msr, fp->ccr); prregs() 1691 printf("msr = "REG" sprg0= "REG"\n", super_regs() 2501 "pc", "msr", "or3", "ctr", "lr", "xer", "ccr",
/linux-4.1.27/arch/x86/kernel/acpi/
H A D	wakeup_64.S	6 #include <asm/msr.h>
/linux-4.1.27/drivers/bluetooth/
H A D	dtl1_cs.c	292 unsigned char msr; dtl1_interrupt() local 339 msr = inb(iobase + UART_MSR); dtl1_interrupt() 341 if (info->ri_latch ^ (msr & UART_MSR_RI)) { dtl1_interrupt() 342 info->ri_latch = msr & UART_MSR_RI; dtl1_interrupt()
/linux-4.1.27/arch/powerpc/platforms/cell/
H A D	pervasive.c	89 switch (regs->msr & SRR1_WAKEMASK) { cbe_system_reset_exception()
/linux-4.1.27/arch/powerpc/include/uapi/asm/
H A D	kvm_para.h	47 __u64 msr; member in struct:kvm_vcpu_arch_shared
/linux-4.1.27/arch/frv/kernel/
H A D	asm-offsets.c	74 DEF_FREG(__FPMEDIA_MSR0, f.msr[0]); foo()
/linux-4.1.27/drivers/isdn/i4l/
H A D	isdn_tty.c	301 info->msr &= ~UART_MSR_CTS; isdn_tty_tint() 446 info->msr &= ~UART_MSR_CTS; isdn_tty_senddown() 727 if ((info->msr & UART_MSR_RI) && isdn_tty_modem_hup() 730 info->msr &= ~(UART_MSR_DCD | UART_MSR_RI); isdn_tty_modem_hup() 1074 info->msr |= (UART_MSR_DSR | UART_MSR_CTS); isdn_tty_startup() 1092 info->msr &= ~UART_MSR_RI; isdn_tty_shutdown() 1159 info->msr |= UART_MSR_CTS; isdn_tty_write() 1201 info->msr |= UART_MSR_CTS; isdn_tty_write() 1363 status = info->msr; isdn_tty_tiocmget() 1757 return info->msr & UART_MSR_DCD; isdn_tty_carrier_raised() 2006 info->msr |= UART_MSR_RI; isdn_tty_find_icall() 2047 info->msr |= UART_MSR_CTS; isdn_tty_stat_callback() 2123 info->msr |= UART_MSR_DCD; isdn_tty_stat_callback() 2742 if (info->msr & UART_MSR_DCD) isdn_tty_cmd_ATand() 2979 if (info->msr & UART_MSR_RI) { isdn_tty_cmd_ATA() 2984 info->msr &= ~UART_MSR_RI; isdn_tty_cmd_ATA() 3424 if (info->msr & UART_MSR_DCD) isdn_tty_parse_at() 3426 if (info->msr & UART_MSR_RI) { isdn_tty_parse_at() 3503 if (info->msr & UART_MSR_DCD) isdn_tty_parse_at() 3546 if (info->msr & UART_MSR_DCD) { isdn_tty_parse_at() 3727 if (info->msr & UART_MSR_RI) { isdn_tty_modem_ring()
/linux-4.1.27/arch/mips/include/asm/mach-loongson/cs5536/
H A D	cs5536.h	13 extern void _rdmsr(u32 msr, u32 *hi, u32 *lo); 14 extern void _wrmsr(u32 msr, u32 hi, u32 lo);
/linux-4.1.27/drivers/staging/rtl8192e/rtl8192e/
H A D	r8192E_dev.c	63 u8 msr; rtl8192e_update_msr() local 66 msr = read_nic_byte(dev, MSR); rtl8192e_update_msr() 67 msr &= ~MSR_LINK_MASK; rtl8192e_update_msr() 72 msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT); rtl8192e_update_msr() 74 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); rtl8192e_update_msr() 79 msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT); rtl8192e_update_msr() 81 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); rtl8192e_update_msr() 85 msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT); rtl8192e_update_msr() 87 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); rtl8192e_update_msr() 93 write_nic_byte(dev, MSR, msr); rtl8192e_update_msr()
/linux-4.1.27/arch/x86/xen/
H A D	enlighten.c	64 #include <asm/msr-index.h> 1033 static u64 xen_read_msr_safe(unsigned int msr, int *err) xen_read_msr_safe() argument 1037 val = native_read_msr_safe(msr, err); xen_read_msr_safe() 1038 switch (msr) { xen_read_msr_safe() 1049 static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high) xen_write_msr_safe() argument 1055 switch (msr) { xen_write_msr_safe() 1083 ret = native_write_msr_safe(msr, low, high); xen_write_msr_safe() 1761 uint32_t eax, ebx, ecx, edx, pages, msr, base; init_hvm_pv_info() local 1771 cpuid(base + 2, &pages, &msr, &ecx, &edx); init_hvm_pv_info() 1774 wrmsr_safe(msr, (u32)pfn, (u32)(pfn >> 32)); init_hvm_pv_info()
/linux-4.1.27/drivers/acpi/
H A D	processor_throttling.c	720 u64 msr = 0; acpi_throttling_rdmsr() local 732 msr = (msr_high << 32) | msr_low; acpi_throttling_rdmsr() 733 *value = (u64) msr; acpi_throttling_rdmsr() 742 u64 msr; acpi_throttling_wrmsr() local 749 msr = value; acpi_throttling_wrmsr() 751 msr & 0xffffffff, msr >> 32); acpi_throttling_wrmsr()
/linux-4.1.27/arch/x86/kernel/cpu/microcode/
H A D	intel_lib.c	32 #include <asm/msr.h>
/linux-4.1.27/arch/x86/oprofile/
H A D	op_model_ppro.c	19 #include <asm/msr.h>
/linux-4.1.27/arch/x86/realmode/rm/
H A D	reboot.S	5 #include <asm/msr-index.h>

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