1/* 2 * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong 3 * because MTRRs can span up to 40 bits (36bits on most modern x86) 4 */ 5#define DEBUG 6 7#include <linux/module.h> 8#include <linux/init.h> 9#include <linux/io.h> 10#include <linux/mm.h> 11 12#include <asm/processor-flags.h> 13#include <asm/cpufeature.h> 14#include <asm/tlbflush.h> 15#include <asm/mtrr.h> 16#include <asm/msr.h> 17#include <asm/pat.h> 18 19#include "mtrr.h" 20 21struct fixed_range_block { 22 int base_msr; /* start address of an MTRR block */ 23 int ranges; /* number of MTRRs in this block */ 24}; 25 26static struct fixed_range_block fixed_range_blocks[] = { 27 { MSR_MTRRfix64K_00000, 1 }, /* one 64k MTRR */ 28 { MSR_MTRRfix16K_80000, 2 }, /* two 16k MTRRs */ 29 { MSR_MTRRfix4K_C0000, 8 }, /* eight 4k MTRRs */ 30 {} 31}; 32 33static unsigned long smp_changes_mask; 34static int mtrr_state_set; 35u64 mtrr_tom2; 36 37struct mtrr_state_type mtrr_state; 38EXPORT_SYMBOL_GPL(mtrr_state); 39 40/* 41 * BIOS is expected to clear MtrrFixDramModEn bit, see for example 42 * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD 43 * Opteron Processors" (26094 Rev. 3.30 February 2006), section 44 * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set 45 * to 1 during BIOS initalization of the fixed MTRRs, then cleared to 46 * 0 for operation." 47 */ 48static inline void k8_check_syscfg_dram_mod_en(void) 49{ 50 u32 lo, hi; 51 52 if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && 53 (boot_cpu_data.x86 >= 0x0f))) 54 return; 55 56 rdmsr(MSR_K8_SYSCFG, lo, hi); 57 if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) { 58 printk(KERN_ERR FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]" 59 " not cleared by BIOS, clearing this bit\n", 60 smp_processor_id()); 61 lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY; 62 mtrr_wrmsr(MSR_K8_SYSCFG, lo, hi); 63 } 64} 65 66/* Get the size of contiguous MTRR range */ 67static u64 get_mtrr_size(u64 mask) 68{ 69 u64 size; 70 71 mask >>= PAGE_SHIFT; 72 mask |= size_or_mask; 73 size = -mask; 74 size <<= PAGE_SHIFT; 75 return size; 76} 77 78/* 79 * Check and return the effective type for MTRR-MTRR type overlap. 80 * Returns 1 if the effective type is UNCACHEABLE, else returns 0 81 */ 82static int check_type_overlap(u8 *prev, u8 *curr) 83{ 84 if (*prev == MTRR_TYPE_UNCACHABLE || *curr == MTRR_TYPE_UNCACHABLE) { 85 *prev = MTRR_TYPE_UNCACHABLE; 86 *curr = MTRR_TYPE_UNCACHABLE; 87 return 1; 88 } 89 90 if ((*prev == MTRR_TYPE_WRBACK && *curr == MTRR_TYPE_WRTHROUGH) || 91 (*prev == MTRR_TYPE_WRTHROUGH && *curr == MTRR_TYPE_WRBACK)) { 92 *prev = MTRR_TYPE_WRTHROUGH; 93 *curr = MTRR_TYPE_WRTHROUGH; 94 } 95 96 if (*prev != *curr) { 97 *prev = MTRR_TYPE_UNCACHABLE; 98 *curr = MTRR_TYPE_UNCACHABLE; 99 return 1; 100 } 101 102 return 0; 103} 104 105/* 106 * Error/Semi-error returns: 107 * 0xFF - when MTRR is not enabled 108 * *repeat == 1 implies [start:end] spanned across MTRR range and type returned 109 * corresponds only to [start:*partial_end]. 110 * Caller has to lookup again for [*partial_end:end]. 111 */ 112static u8 __mtrr_type_lookup(u64 start, u64 end, u64 *partial_end, int *repeat) 113{ 114 int i; 115 u64 base, mask; 116 u8 prev_match, curr_match; 117 118 *repeat = 0; 119 if (!mtrr_state_set) 120 return 0xFF; 121 122 if (!mtrr_state.enabled) 123 return 0xFF; 124 125 /* Make end inclusive end, instead of exclusive */ 126 end--; 127 128 /* Look in fixed ranges. Just return the type as per start */ 129 if (mtrr_state.have_fixed && (start < 0x100000)) { 130 int idx; 131 132 if (start < 0x80000) { 133 idx = 0; 134 idx += (start >> 16); 135 return mtrr_state.fixed_ranges[idx]; 136 } else if (start < 0xC0000) { 137 idx = 1 * 8; 138 idx += ((start - 0x80000) >> 14); 139 return mtrr_state.fixed_ranges[idx]; 140 } else if (start < 0x1000000) { 141 idx = 3 * 8; 142 idx += ((start - 0xC0000) >> 12); 143 return mtrr_state.fixed_ranges[idx]; 144 } 145 } 146 147 /* 148 * Look in variable ranges 149 * Look of multiple ranges matching this address and pick type 150 * as per MTRR precedence 151 */ 152 if (!(mtrr_state.enabled & 2)) 153 return mtrr_state.def_type; 154 155 prev_match = 0xFF; 156 for (i = 0; i < num_var_ranges; ++i) { 157 unsigned short start_state, end_state; 158 159 if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11))) 160 continue; 161 162 base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + 163 (mtrr_state.var_ranges[i].base_lo & PAGE_MASK); 164 mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) + 165 (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK); 166 167 start_state = ((start & mask) == (base & mask)); 168 end_state = ((end & mask) == (base & mask)); 169 170 if (start_state != end_state) { 171 /* 172 * We have start:end spanning across an MTRR. 173 * We split the region into 174 * either 175 * (start:mtrr_end) (mtrr_end:end) 176 * or 177 * (start:mtrr_start) (mtrr_start:end) 178 * depending on kind of overlap. 179 * Return the type for first region and a pointer to 180 * the start of second region so that caller will 181 * lookup again on the second region. 182 * Note: This way we handle multiple overlaps as well. 183 */ 184 if (start_state) 185 *partial_end = base + get_mtrr_size(mask); 186 else 187 *partial_end = base; 188 189 if (unlikely(*partial_end <= start)) { 190 WARN_ON(1); 191 *partial_end = start + PAGE_SIZE; 192 } 193 194 end = *partial_end - 1; /* end is inclusive */ 195 *repeat = 1; 196 } 197 198 if ((start & mask) != (base & mask)) 199 continue; 200 201 curr_match = mtrr_state.var_ranges[i].base_lo & 0xff; 202 if (prev_match == 0xFF) { 203 prev_match = curr_match; 204 continue; 205 } 206 207 if (check_type_overlap(&prev_match, &curr_match)) 208 return curr_match; 209 } 210 211 if (mtrr_tom2) { 212 if (start >= (1ULL<<32) && (end < mtrr_tom2)) 213 return MTRR_TYPE_WRBACK; 214 } 215 216 if (prev_match != 0xFF) 217 return prev_match; 218 219 return mtrr_state.def_type; 220} 221 222/* 223 * Returns the effective MTRR type for the region 224 * Error return: 225 * 0xFF - when MTRR is not enabled 226 */ 227u8 mtrr_type_lookup(u64 start, u64 end) 228{ 229 u8 type, prev_type; 230 int repeat; 231 u64 partial_end; 232 233 type = __mtrr_type_lookup(start, end, &partial_end, &repeat); 234 235 /* 236 * Common path is with repeat = 0. 237 * However, we can have cases where [start:end] spans across some 238 * MTRR range. Do repeated lookups for that case here. 239 */ 240 while (repeat) { 241 prev_type = type; 242 start = partial_end; 243 type = __mtrr_type_lookup(start, end, &partial_end, &repeat); 244 245 if (check_type_overlap(&prev_type, &type)) 246 return type; 247 } 248 249 return type; 250} 251 252/* Get the MSR pair relating to a var range */ 253static void 254get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr) 255{ 256 rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); 257 rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); 258} 259 260/* Fill the MSR pair relating to a var range */ 261void fill_mtrr_var_range(unsigned int index, 262 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi) 263{ 264 struct mtrr_var_range *vr; 265 266 vr = mtrr_state.var_ranges; 267 268 vr[index].base_lo = base_lo; 269 vr[index].base_hi = base_hi; 270 vr[index].mask_lo = mask_lo; 271 vr[index].mask_hi = mask_hi; 272} 273 274static void get_fixed_ranges(mtrr_type *frs) 275{ 276 unsigned int *p = (unsigned int *)frs; 277 int i; 278 279 k8_check_syscfg_dram_mod_en(); 280 281 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]); 282 283 for (i = 0; i < 2; i++) 284 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]); 285 for (i = 0; i < 8; i++) 286 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]); 287} 288 289void mtrr_save_fixed_ranges(void *info) 290{ 291 if (cpu_has_mtrr) 292 get_fixed_ranges(mtrr_state.fixed_ranges); 293} 294 295static unsigned __initdata last_fixed_start; 296static unsigned __initdata last_fixed_end; 297static mtrr_type __initdata last_fixed_type; 298 299static void __init print_fixed_last(void) 300{ 301 if (!last_fixed_end) 302 return; 303 304 pr_debug(" %05X-%05X %s\n", last_fixed_start, 305 last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type)); 306 307 last_fixed_end = 0; 308} 309 310static void __init update_fixed_last(unsigned base, unsigned end, 311 mtrr_type type) 312{ 313 last_fixed_start = base; 314 last_fixed_end = end; 315 last_fixed_type = type; 316} 317 318static void __init 319print_fixed(unsigned base, unsigned step, const mtrr_type *types) 320{ 321 unsigned i; 322 323 for (i = 0; i < 8; ++i, ++types, base += step) { 324 if (last_fixed_end == 0) { 325 update_fixed_last(base, base + step, *types); 326 continue; 327 } 328 if (last_fixed_end == base && last_fixed_type == *types) { 329 last_fixed_end = base + step; 330 continue; 331 } 332 /* new segments: gap or different type */ 333 print_fixed_last(); 334 update_fixed_last(base, base + step, *types); 335 } 336} 337 338static void prepare_set(void); 339static void post_set(void); 340 341static void __init print_mtrr_state(void) 342{ 343 unsigned int i; 344 int high_width; 345 346 pr_debug("MTRR default type: %s\n", 347 mtrr_attrib_to_str(mtrr_state.def_type)); 348 if (mtrr_state.have_fixed) { 349 pr_debug("MTRR fixed ranges %sabled:\n", 350 mtrr_state.enabled & 1 ? "en" : "dis"); 351 print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0); 352 for (i = 0; i < 2; ++i) 353 print_fixed(0x80000 + i * 0x20000, 0x04000, 354 mtrr_state.fixed_ranges + (i + 1) * 8); 355 for (i = 0; i < 8; ++i) 356 print_fixed(0xC0000 + i * 0x08000, 0x01000, 357 mtrr_state.fixed_ranges + (i + 3) * 8); 358 359 /* tail */ 360 print_fixed_last(); 361 } 362 pr_debug("MTRR variable ranges %sabled:\n", 363 mtrr_state.enabled & 2 ? "en" : "dis"); 364 high_width = (__ffs64(size_or_mask) - (32 - PAGE_SHIFT) + 3) / 4; 365 366 for (i = 0; i < num_var_ranges; ++i) { 367 if (mtrr_state.var_ranges[i].mask_lo & (1 << 11)) 368 pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", 369 i, 370 high_width, 371 mtrr_state.var_ranges[i].base_hi, 372 mtrr_state.var_ranges[i].base_lo >> 12, 373 high_width, 374 mtrr_state.var_ranges[i].mask_hi, 375 mtrr_state.var_ranges[i].mask_lo >> 12, 376 mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff)); 377 else 378 pr_debug(" %u disabled\n", i); 379 } 380 if (mtrr_tom2) 381 pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20); 382} 383 384/* Grab all of the MTRR state for this CPU into *state */ 385void __init get_mtrr_state(void) 386{ 387 struct mtrr_var_range *vrs; 388 unsigned long flags; 389 unsigned lo, dummy; 390 unsigned int i; 391 392 vrs = mtrr_state.var_ranges; 393 394 rdmsr(MSR_MTRRcap, lo, dummy); 395 mtrr_state.have_fixed = (lo >> 8) & 1; 396 397 for (i = 0; i < num_var_ranges; i++) 398 get_mtrr_var_range(i, &vrs[i]); 399 if (mtrr_state.have_fixed) 400 get_fixed_ranges(mtrr_state.fixed_ranges); 401 402 rdmsr(MSR_MTRRdefType, lo, dummy); 403 mtrr_state.def_type = (lo & 0xff); 404 mtrr_state.enabled = (lo & 0xc00) >> 10; 405 406 if (amd_special_default_mtrr()) { 407 unsigned low, high; 408 409 /* TOP_MEM2 */ 410 rdmsr(MSR_K8_TOP_MEM2, low, high); 411 mtrr_tom2 = high; 412 mtrr_tom2 <<= 32; 413 mtrr_tom2 |= low; 414 mtrr_tom2 &= 0xffffff800000ULL; 415 } 416 417 print_mtrr_state(); 418 419 mtrr_state_set = 1; 420 421 /* PAT setup for BP. We need to go through sync steps here */ 422 local_irq_save(flags); 423 prepare_set(); 424 425 pat_init(); 426 427 post_set(); 428 local_irq_restore(flags); 429} 430 431/* Some BIOS's are messed up and don't set all MTRRs the same! */ 432void __init mtrr_state_warn(void) 433{ 434 unsigned long mask = smp_changes_mask; 435 436 if (!mask) 437 return; 438 if (mask & MTRR_CHANGE_MASK_FIXED) 439 pr_warning("mtrr: your CPUs had inconsistent fixed MTRR settings\n"); 440 if (mask & MTRR_CHANGE_MASK_VARIABLE) 441 pr_warning("mtrr: your CPUs had inconsistent variable MTRR settings\n"); 442 if (mask & MTRR_CHANGE_MASK_DEFTYPE) 443 pr_warning("mtrr: your CPUs had inconsistent MTRRdefType settings\n"); 444 445 printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n"); 446 printk(KERN_INFO "mtrr: corrected configuration.\n"); 447} 448 449/* 450 * Doesn't attempt to pass an error out to MTRR users 451 * because it's quite complicated in some cases and probably not 452 * worth it because the best error handling is to ignore it. 453 */ 454void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b) 455{ 456 if (wrmsr_safe(msr, a, b) < 0) { 457 printk(KERN_ERR 458 "MTRR: CPU %u: Writing MSR %x to %x:%x failed\n", 459 smp_processor_id(), msr, a, b); 460 } 461} 462 463/** 464 * set_fixed_range - checks & updates a fixed-range MTRR if it 465 * differs from the value it should have 466 * @msr: MSR address of the MTTR which should be checked and updated 467 * @changed: pointer which indicates whether the MTRR needed to be changed 468 * @msrwords: pointer to the MSR values which the MSR should have 469 */ 470static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords) 471{ 472 unsigned lo, hi; 473 474 rdmsr(msr, lo, hi); 475 476 if (lo != msrwords[0] || hi != msrwords[1]) { 477 mtrr_wrmsr(msr, msrwords[0], msrwords[1]); 478 *changed = true; 479 } 480} 481 482/** 483 * generic_get_free_region - Get a free MTRR. 484 * @base: The starting (base) address of the region. 485 * @size: The size (in bytes) of the region. 486 * @replace_reg: mtrr index to be replaced; set to invalid value if none. 487 * 488 * Returns: The index of the region on success, else negative on error. 489 */ 490int 491generic_get_free_region(unsigned long base, unsigned long size, int replace_reg) 492{ 493 unsigned long lbase, lsize; 494 mtrr_type ltype; 495 int i, max; 496 497 max = num_var_ranges; 498 if (replace_reg >= 0 && replace_reg < max) 499 return replace_reg; 500 501 for (i = 0; i < max; ++i) { 502 mtrr_if->get(i, &lbase, &lsize, <ype); 503 if (lsize == 0) 504 return i; 505 } 506 507 return -ENOSPC; 508} 509 510static void generic_get_mtrr(unsigned int reg, unsigned long *base, 511 unsigned long *size, mtrr_type *type) 512{ 513 u32 mask_lo, mask_hi, base_lo, base_hi; 514 unsigned int hi; 515 u64 tmp, mask; 516 517 /* 518 * get_mtrr doesn't need to update mtrr_state, also it could be called 519 * from any cpu, so try to print it out directly. 520 */ 521 get_cpu(); 522 523 rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); 524 525 if ((mask_lo & 0x800) == 0) { 526 /* Invalid (i.e. free) range */ 527 *base = 0; 528 *size = 0; 529 *type = 0; 530 goto out_put_cpu; 531 } 532 533 rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi); 534 535 /* Work out the shifted address mask: */ 536 tmp = (u64)mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT; 537 mask = size_or_mask | tmp; 538 539 /* Expand tmp with high bits to all 1s: */ 540 hi = fls64(tmp); 541 if (hi > 0) { 542 tmp |= ~((1ULL<<(hi - 1)) - 1); 543 544 if (tmp != mask) { 545 printk(KERN_WARNING "mtrr: your BIOS has configured an incorrect mask, fixing it.\n"); 546 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 547 mask = tmp; 548 } 549 } 550 551 /* 552 * This works correctly if size is a power of two, i.e. a 553 * contiguous range: 554 */ 555 *size = -mask; 556 *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT; 557 *type = base_lo & 0xff; 558 559out_put_cpu: 560 put_cpu(); 561} 562 563/** 564 * set_fixed_ranges - checks & updates the fixed-range MTRRs if they 565 * differ from the saved set 566 * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges() 567 */ 568static int set_fixed_ranges(mtrr_type *frs) 569{ 570 unsigned long long *saved = (unsigned long long *)frs; 571 bool changed = false; 572 int block = -1, range; 573 574 k8_check_syscfg_dram_mod_en(); 575 576 while (fixed_range_blocks[++block].ranges) { 577 for (range = 0; range < fixed_range_blocks[block].ranges; range++) 578 set_fixed_range(fixed_range_blocks[block].base_msr + range, 579 &changed, (unsigned int *)saved++); 580 } 581 582 return changed; 583} 584 585/* 586 * Set the MSR pair relating to a var range. 587 * Returns true if changes are made. 588 */ 589static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr) 590{ 591 unsigned int lo, hi; 592 bool changed = false; 593 594 rdmsr(MTRRphysBase_MSR(index), lo, hi); 595 if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL) 596 || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) != 597 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { 598 599 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); 600 changed = true; 601 } 602 603 rdmsr(MTRRphysMask_MSR(index), lo, hi); 604 605 if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL) 606 || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) != 607 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { 608 mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); 609 changed = true; 610 } 611 return changed; 612} 613 614static u32 deftype_lo, deftype_hi; 615 616/** 617 * set_mtrr_state - Set the MTRR state for this CPU. 618 * 619 * NOTE: The CPU must already be in a safe state for MTRR changes. 620 * RETURNS: 0 if no changes made, else a mask indicating what was changed. 621 */ 622static unsigned long set_mtrr_state(void) 623{ 624 unsigned long change_mask = 0; 625 unsigned int i; 626 627 for (i = 0; i < num_var_ranges; i++) { 628 if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i])) 629 change_mask |= MTRR_CHANGE_MASK_VARIABLE; 630 } 631 632 if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges)) 633 change_mask |= MTRR_CHANGE_MASK_FIXED; 634 635 /* 636 * Set_mtrr_restore restores the old value of MTRRdefType, 637 * so to set it we fiddle with the saved value: 638 */ 639 if ((deftype_lo & 0xff) != mtrr_state.def_type 640 || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) { 641 642 deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type | 643 (mtrr_state.enabled << 10); 644 change_mask |= MTRR_CHANGE_MASK_DEFTYPE; 645 } 646 647 return change_mask; 648} 649 650 651static unsigned long cr4; 652static DEFINE_RAW_SPINLOCK(set_atomicity_lock); 653 654/* 655 * Since we are disabling the cache don't allow any interrupts, 656 * they would run extremely slow and would only increase the pain. 657 * 658 * The caller must ensure that local interrupts are disabled and 659 * are reenabled after post_set() has been called. 660 */ 661static void prepare_set(void) __acquires(set_atomicity_lock) 662{ 663 unsigned long cr0; 664 665 /* 666 * Note that this is not ideal 667 * since the cache is only flushed/disabled for this CPU while the 668 * MTRRs are changed, but changing this requires more invasive 669 * changes to the way the kernel boots 670 */ 671 672 raw_spin_lock(&set_atomicity_lock); 673 674 /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */ 675 cr0 = read_cr0() | X86_CR0_CD; 676 write_cr0(cr0); 677 wbinvd(); 678 679 /* Save value of CR4 and clear Page Global Enable (bit 7) */ 680 if (cpu_has_pge) { 681 cr4 = __read_cr4(); 682 __write_cr4(cr4 & ~X86_CR4_PGE); 683 } 684 685 /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */ 686 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); 687 __flush_tlb(); 688 689 /* Save MTRR state */ 690 rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); 691 692 /* Disable MTRRs, and set the default type to uncached */ 693 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi); 694 wbinvd(); 695} 696 697static void post_set(void) __releases(set_atomicity_lock) 698{ 699 /* Flush TLBs (no need to flush caches - they are disabled) */ 700 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); 701 __flush_tlb(); 702 703 /* Intel (P6) standard MTRRs */ 704 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); 705 706 /* Enable caches */ 707 write_cr0(read_cr0() & ~X86_CR0_CD); 708 709 /* Restore value of CR4 */ 710 if (cpu_has_pge) 711 __write_cr4(cr4); 712 raw_spin_unlock(&set_atomicity_lock); 713} 714 715static void generic_set_all(void) 716{ 717 unsigned long mask, count; 718 unsigned long flags; 719 720 local_irq_save(flags); 721 prepare_set(); 722 723 /* Actually set the state */ 724 mask = set_mtrr_state(); 725 726 /* also set PAT */ 727 pat_init(); 728 729 post_set(); 730 local_irq_restore(flags); 731 732 /* Use the atomic bitops to update the global mask */ 733 for (count = 0; count < sizeof mask * 8; ++count) { 734 if (mask & 0x01) 735 set_bit(count, &smp_changes_mask); 736 mask >>= 1; 737 } 738 739} 740 741/** 742 * generic_set_mtrr - set variable MTRR register on the local CPU. 743 * 744 * @reg: The register to set. 745 * @base: The base address of the region. 746 * @size: The size of the region. If this is 0 the region is disabled. 747 * @type: The type of the region. 748 * 749 * Returns nothing. 750 */ 751static void generic_set_mtrr(unsigned int reg, unsigned long base, 752 unsigned long size, mtrr_type type) 753{ 754 unsigned long flags; 755 struct mtrr_var_range *vr; 756 757 vr = &mtrr_state.var_ranges[reg]; 758 759 local_irq_save(flags); 760 prepare_set(); 761 762 if (size == 0) { 763 /* 764 * The invalid bit is kept in the mask, so we simply 765 * clear the relevant mask register to disable a range. 766 */ 767 mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0); 768 memset(vr, 0, sizeof(struct mtrr_var_range)); 769 } else { 770 vr->base_lo = base << PAGE_SHIFT | type; 771 vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT); 772 vr->mask_lo = -size << PAGE_SHIFT | 0x800; 773 vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT); 774 775 mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); 776 mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi); 777 } 778 779 post_set(); 780 local_irq_restore(flags); 781} 782 783int generic_validate_add_page(unsigned long base, unsigned long size, 784 unsigned int type) 785{ 786 unsigned long lbase, last; 787 788 /* 789 * For Intel PPro stepping <= 7 790 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF 791 */ 792 if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 && 793 boot_cpu_data.x86_model == 1 && 794 boot_cpu_data.x86_mask <= 7) { 795 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) { 796 pr_warning("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base); 797 return -EINVAL; 798 } 799 if (!(base + size < 0x70000 || base > 0x7003F) && 800 (type == MTRR_TYPE_WRCOMB 801 || type == MTRR_TYPE_WRBACK)) { 802 pr_warning("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n"); 803 return -EINVAL; 804 } 805 } 806 807 /* 808 * Check upper bits of base and last are equal and lower bits are 0 809 * for base and 1 for last 810 */ 811 last = base + size - 1; 812 for (lbase = base; !(lbase & 1) && (last & 1); 813 lbase = lbase >> 1, last = last >> 1) 814 ; 815 if (lbase != last) { 816 pr_warning("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size); 817 return -EINVAL; 818 } 819 return 0; 820} 821 822static int generic_have_wrcomb(void) 823{ 824 unsigned long config, dummy; 825 rdmsr(MSR_MTRRcap, config, dummy); 826 return config & (1 << 10); 827} 828 829int positive_have_wrcomb(void) 830{ 831 return 1; 832} 833 834/* 835 * Generic structure... 836 */ 837const struct mtrr_ops generic_mtrr_ops = { 838 .use_intel_if = 1, 839 .set_all = generic_set_all, 840 .get = generic_get_mtrr, 841 .get_free_region = generic_get_free_region, 842 .set = generic_set_mtrr, 843 .validate_add_page = generic_validate_add_page, 844 .have_wrcomb = generic_have_wrcomb, 845}; 846