Lines Matching refs:msr
56 msr sctlr_el1, x0
74 msr sctlr_el1, x1 // disable the MMU
152 msr tpidr_el0, x2
153 msr tpidrro_el0, x3
154 msr contextidr_el1, x4
155 msr mair_el1, x5
156 msr cpacr_el1, x6
157 msr ttbr0_el1, x1
158 msr ttbr1_el1, x7
160 msr tcr_el1, x8
161 msr vbar_el1, x9
162 msr mdscr_el1, x10
167 msr oslar_el1, x11
186 msr ttbr0_el1, x0 // set TTBR0
205 msr cpacr_el1, x0 // Enable FP/ASIMD
207 msr mdscr_el1, x0 // access to the DCC from EL0
225 msr mair_el1, x5
248 msr tcr_el1, x10