1/* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17#include <linux/perf_event.h> 18#include <linux/kernel_stat.h> 19#include <linux/mc146818rtc.h> 20#include <linux/acpi_pmtmr.h> 21#include <linux/clockchips.h> 22#include <linux/interrupt.h> 23#include <linux/bootmem.h> 24#include <linux/ftrace.h> 25#include <linux/ioport.h> 26#include <linux/module.h> 27#include <linux/syscore_ops.h> 28#include <linux/delay.h> 29#include <linux/timex.h> 30#include <linux/i8253.h> 31#include <linux/dmar.h> 32#include <linux/init.h> 33#include <linux/cpu.h> 34#include <linux/dmi.h> 35#include <linux/smp.h> 36#include <linux/mm.h> 37 38#include <asm/trace/irq_vectors.h> 39#include <asm/irq_remapping.h> 40#include <asm/perf_event.h> 41#include <asm/x86_init.h> 42#include <asm/pgalloc.h> 43#include <linux/atomic.h> 44#include <asm/mpspec.h> 45#include <asm/i8259.h> 46#include <asm/proto.h> 47#include <asm/apic.h> 48#include <asm/io_apic.h> 49#include <asm/desc.h> 50#include <asm/hpet.h> 51#include <asm/idle.h> 52#include <asm/mtrr.h> 53#include <asm/time.h> 54#include <asm/smp.h> 55#include <asm/mce.h> 56#include <asm/tsc.h> 57#include <asm/hypervisor.h> 58 59unsigned int num_processors; 60 61unsigned disabled_cpus; 62 63/* Processor that is doing the boot up */ 64unsigned int boot_cpu_physical_apicid = -1U; 65EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 66 67/* 68 * The highest APIC ID seen during enumeration. 69 */ 70static unsigned int max_physical_apicid; 71 72/* 73 * Bitmask of physically existing CPUs: 74 */ 75physid_mask_t phys_cpu_present_map; 76 77/* 78 * Processor to be disabled specified by kernel parameter 79 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 80 * avoid undefined behaviour caused by sending INIT from AP to BSP. 81 */ 82static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 83 84/* 85 * Map cpu index to physical APIC ID 86 */ 87DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 88DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 89EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 90EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 91 92#ifdef CONFIG_X86_32 93 94/* 95 * On x86_32, the mapping between cpu and logical apicid may vary 96 * depending on apic in use. The following early percpu variable is 97 * used for the mapping. This is where the behaviors of x86_64 and 32 98 * actually diverge. Let's keep it ugly for now. 99 */ 100DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 101 102/* Local APIC was disabled by the BIOS and enabled by the kernel */ 103static int enabled_via_apicbase; 104 105/* 106 * Handle interrupt mode configuration register (IMCR). 107 * This register controls whether the interrupt signals 108 * that reach the BSP come from the master PIC or from the 109 * local APIC. Before entering Symmetric I/O Mode, either 110 * the BIOS or the operating system must switch out of 111 * PIC Mode by changing the IMCR. 112 */ 113static inline void imcr_pic_to_apic(void) 114{ 115 /* select IMCR register */ 116 outb(0x70, 0x22); 117 /* NMI and 8259 INTR go through APIC */ 118 outb(0x01, 0x23); 119} 120 121static inline void imcr_apic_to_pic(void) 122{ 123 /* select IMCR register */ 124 outb(0x70, 0x22); 125 /* NMI and 8259 INTR go directly to BSP */ 126 outb(0x00, 0x23); 127} 128#endif 129 130/* 131 * Knob to control our willingness to enable the local APIC. 132 * 133 * +1=force-enable 134 */ 135static int force_enable_local_apic __initdata; 136 137/* 138 * APIC command line parameters 139 */ 140static int __init parse_lapic(char *arg) 141{ 142 if (config_enabled(CONFIG_X86_32) && !arg) 143 force_enable_local_apic = 1; 144 else if (arg && !strncmp(arg, "notscdeadline", 13)) 145 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 146 return 0; 147} 148early_param("lapic", parse_lapic); 149 150#ifdef CONFIG_X86_64 151static int apic_calibrate_pmtmr __initdata; 152static __init int setup_apicpmtimer(char *s) 153{ 154 apic_calibrate_pmtmr = 1; 155 notsc_setup(NULL); 156 return 0; 157} 158__setup("apicpmtimer", setup_apicpmtimer); 159#endif 160 161unsigned long mp_lapic_addr; 162int disable_apic; 163/* Disable local APIC timer from the kernel commandline or via dmi quirk */ 164static int disable_apic_timer __initdata; 165/* Local APIC timer works in C2 */ 166int local_apic_timer_c2_ok; 167EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 168 169int first_system_vector = FIRST_SYSTEM_VECTOR; 170 171/* 172 * Debug level, exported for io_apic.c 173 */ 174unsigned int apic_verbosity; 175 176int pic_mode; 177 178/* Have we found an MP table */ 179int smp_found_config; 180 181static struct resource lapic_resource = { 182 .name = "Local APIC", 183 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 184}; 185 186unsigned int lapic_timer_frequency = 0; 187 188static void apic_pm_activate(void); 189 190static unsigned long apic_phys; 191 192/* 193 * Get the LAPIC version 194 */ 195static inline int lapic_get_version(void) 196{ 197 return GET_APIC_VERSION(apic_read(APIC_LVR)); 198} 199 200/* 201 * Check, if the APIC is integrated or a separate chip 202 */ 203static inline int lapic_is_integrated(void) 204{ 205#ifdef CONFIG_X86_64 206 return 1; 207#else 208 return APIC_INTEGRATED(lapic_get_version()); 209#endif 210} 211 212/* 213 * Check, whether this is a modern or a first generation APIC 214 */ 215static int modern_apic(void) 216{ 217 /* AMD systems use old APIC versions, so check the CPU */ 218 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 219 boot_cpu_data.x86 >= 0xf) 220 return 1; 221 return lapic_get_version() >= 0x14; 222} 223 224/* 225 * right after this call apic become NOOP driven 226 * so apic->write/read doesn't do anything 227 */ 228static void __init apic_disable(void) 229{ 230 pr_info("APIC: switched to apic NOOP\n"); 231 apic = &apic_noop; 232} 233 234void native_apic_wait_icr_idle(void) 235{ 236 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 237 cpu_relax(); 238} 239 240u32 native_safe_apic_wait_icr_idle(void) 241{ 242 u32 send_status; 243 int timeout; 244 245 timeout = 0; 246 do { 247 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 248 if (!send_status) 249 break; 250 inc_irq_stat(icr_read_retry_count); 251 udelay(100); 252 } while (timeout++ < 1000); 253 254 return send_status; 255} 256 257void native_apic_icr_write(u32 low, u32 id) 258{ 259 unsigned long flags; 260 261 local_irq_save(flags); 262 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 263 apic_write(APIC_ICR, low); 264 local_irq_restore(flags); 265} 266 267u64 native_apic_icr_read(void) 268{ 269 u32 icr1, icr2; 270 271 icr2 = apic_read(APIC_ICR2); 272 icr1 = apic_read(APIC_ICR); 273 274 return icr1 | ((u64)icr2 << 32); 275} 276 277#ifdef CONFIG_X86_32 278/** 279 * get_physical_broadcast - Get number of physical broadcast IDs 280 */ 281int get_physical_broadcast(void) 282{ 283 return modern_apic() ? 0xff : 0xf; 284} 285#endif 286 287/** 288 * lapic_get_maxlvt - get the maximum number of local vector table entries 289 */ 290int lapic_get_maxlvt(void) 291{ 292 unsigned int v; 293 294 v = apic_read(APIC_LVR); 295 /* 296 * - we always have APIC integrated on 64bit mode 297 * - 82489DXs do not report # of LVT entries 298 */ 299 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 300} 301 302/* 303 * Local APIC timer 304 */ 305 306/* Clock divisor */ 307#define APIC_DIVISOR 16 308#define TSC_DIVISOR 32 309 310/* 311 * This function sets up the local APIC timer, with a timeout of 312 * 'clocks' APIC bus clock. During calibration we actually call 313 * this function twice on the boot CPU, once with a bogus timeout 314 * value, second time for real. The other (noncalibrating) CPUs 315 * call this function only once, with the real, calibrated value. 316 * 317 * We do reads before writes even if unnecessary, to get around the 318 * P5 APIC double write bug. 319 */ 320static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 321{ 322 unsigned int lvtt_value, tmp_value; 323 324 lvtt_value = LOCAL_TIMER_VECTOR; 325 if (!oneshot) 326 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 327 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 328 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 329 330 if (!lapic_is_integrated()) 331 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 332 333 if (!irqen) 334 lvtt_value |= APIC_LVT_MASKED; 335 336 apic_write(APIC_LVTT, lvtt_value); 337 338 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 339 /* 340 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 341 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 342 * According to Intel, MFENCE can do the serialization here. 343 */ 344 asm volatile("mfence" : : : "memory"); 345 346 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 347 return; 348 } 349 350 /* 351 * Divide PICLK by 16 352 */ 353 tmp_value = apic_read(APIC_TDCR); 354 apic_write(APIC_TDCR, 355 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 356 APIC_TDR_DIV_16); 357 358 if (!oneshot) 359 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 360} 361 362/* 363 * Setup extended LVT, AMD specific 364 * 365 * Software should use the LVT offsets the BIOS provides. The offsets 366 * are determined by the subsystems using it like those for MCE 367 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 368 * are supported. Beginning with family 10h at least 4 offsets are 369 * available. 370 * 371 * Since the offsets must be consistent for all cores, we keep track 372 * of the LVT offsets in software and reserve the offset for the same 373 * vector also to be used on other cores. An offset is freed by 374 * setting the entry to APIC_EILVT_MASKED. 375 * 376 * If the BIOS is right, there should be no conflicts. Otherwise a 377 * "[Firmware Bug]: ..." error message is generated. However, if 378 * software does not properly determines the offsets, it is not 379 * necessarily a BIOS bug. 380 */ 381 382static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 383 384static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 385{ 386 return (old & APIC_EILVT_MASKED) 387 || (new == APIC_EILVT_MASKED) 388 || ((new & ~APIC_EILVT_MASKED) == old); 389} 390 391static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 392{ 393 unsigned int rsvd, vector; 394 395 if (offset >= APIC_EILVT_NR_MAX) 396 return ~0; 397 398 rsvd = atomic_read(&eilvt_offsets[offset]); 399 do { 400 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 401 if (vector && !eilvt_entry_is_changeable(vector, new)) 402 /* may not change if vectors are different */ 403 return rsvd; 404 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 405 } while (rsvd != new); 406 407 rsvd &= ~APIC_EILVT_MASKED; 408 if (rsvd && rsvd != vector) 409 pr_info("LVT offset %d assigned for vector 0x%02x\n", 410 offset, rsvd); 411 412 return new; 413} 414 415/* 416 * If mask=1, the LVT entry does not generate interrupts while mask=0 417 * enables the vector. See also the BKDGs. Must be called with 418 * preemption disabled. 419 */ 420 421int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 422{ 423 unsigned long reg = APIC_EILVTn(offset); 424 unsigned int new, old, reserved; 425 426 new = (mask << 16) | (msg_type << 8) | vector; 427 old = apic_read(reg); 428 reserved = reserve_eilvt_offset(offset, new); 429 430 if (reserved != new) { 431 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 432 "vector 0x%x, but the register is already in use for " 433 "vector 0x%x on another cpu\n", 434 smp_processor_id(), reg, offset, new, reserved); 435 return -EINVAL; 436 } 437 438 if (!eilvt_entry_is_changeable(old, new)) { 439 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 440 "vector 0x%x, but the register is already in use for " 441 "vector 0x%x on this cpu\n", 442 smp_processor_id(), reg, offset, new, old); 443 return -EBUSY; 444 } 445 446 apic_write(reg, new); 447 448 return 0; 449} 450EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 451 452/* 453 * Program the next event, relative to now 454 */ 455static int lapic_next_event(unsigned long delta, 456 struct clock_event_device *evt) 457{ 458 apic_write(APIC_TMICT, delta); 459 return 0; 460} 461 462static int lapic_next_deadline(unsigned long delta, 463 struct clock_event_device *evt) 464{ 465 u64 tsc; 466 467 rdtscll(tsc); 468 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 469 return 0; 470} 471 472/* 473 * Setup the lapic timer in periodic or oneshot mode 474 */ 475static void lapic_timer_setup(enum clock_event_mode mode, 476 struct clock_event_device *evt) 477{ 478 unsigned long flags; 479 unsigned int v; 480 481 /* Lapic used as dummy for broadcast ? */ 482 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 483 return; 484 485 local_irq_save(flags); 486 487 switch (mode) { 488 case CLOCK_EVT_MODE_PERIODIC: 489 case CLOCK_EVT_MODE_ONESHOT: 490 __setup_APIC_LVTT(lapic_timer_frequency, 491 mode != CLOCK_EVT_MODE_PERIODIC, 1); 492 break; 493 case CLOCK_EVT_MODE_UNUSED: 494 case CLOCK_EVT_MODE_SHUTDOWN: 495 v = apic_read(APIC_LVTT); 496 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 497 apic_write(APIC_LVTT, v); 498 apic_write(APIC_TMICT, 0); 499 break; 500 case CLOCK_EVT_MODE_RESUME: 501 /* Nothing to do here */ 502 break; 503 } 504 505 local_irq_restore(flags); 506} 507 508/* 509 * Local APIC timer broadcast function 510 */ 511static void lapic_timer_broadcast(const struct cpumask *mask) 512{ 513#ifdef CONFIG_SMP 514 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 515#endif 516} 517 518 519/* 520 * The local apic timer can be used for any function which is CPU local. 521 */ 522static struct clock_event_device lapic_clockevent = { 523 .name = "lapic", 524 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 525 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 526 .shift = 32, 527 .set_mode = lapic_timer_setup, 528 .set_next_event = lapic_next_event, 529 .broadcast = lapic_timer_broadcast, 530 .rating = 100, 531 .irq = -1, 532}; 533static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 534 535/* 536 * Setup the local APIC timer for this CPU. Copy the initialized values 537 * of the boot CPU and register the clock event in the framework. 538 */ 539static void setup_APIC_timer(void) 540{ 541 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 542 543 if (this_cpu_has(X86_FEATURE_ARAT)) { 544 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 545 /* Make LAPIC timer preferrable over percpu HPET */ 546 lapic_clockevent.rating = 150; 547 } 548 549 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 550 levt->cpumask = cpumask_of(smp_processor_id()); 551 552 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 553 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 554 CLOCK_EVT_FEAT_DUMMY); 555 levt->set_next_event = lapic_next_deadline; 556 clockevents_config_and_register(levt, 557 (tsc_khz / TSC_DIVISOR) * 1000, 558 0xF, ~0UL); 559 } else 560 clockevents_register_device(levt); 561} 562 563/* 564 * In this functions we calibrate APIC bus clocks to the external timer. 565 * 566 * We want to do the calibration only once since we want to have local timer 567 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 568 * frequency. 569 * 570 * This was previously done by reading the PIT/HPET and waiting for a wrap 571 * around to find out, that a tick has elapsed. I have a box, where the PIT 572 * readout is broken, so it never gets out of the wait loop again. This was 573 * also reported by others. 574 * 575 * Monitoring the jiffies value is inaccurate and the clockevents 576 * infrastructure allows us to do a simple substitution of the interrupt 577 * handler. 578 * 579 * The calibration routine also uses the pm_timer when possible, as the PIT 580 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 581 * back to normal later in the boot process). 582 */ 583 584#define LAPIC_CAL_LOOPS (HZ/10) 585 586static __initdata int lapic_cal_loops = -1; 587static __initdata long lapic_cal_t1, lapic_cal_t2; 588static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 589static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 590static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 591 592/* 593 * Temporary interrupt handler. 594 */ 595static void __init lapic_cal_handler(struct clock_event_device *dev) 596{ 597 unsigned long long tsc = 0; 598 long tapic = apic_read(APIC_TMCCT); 599 unsigned long pm = acpi_pm_read_early(); 600 601 if (cpu_has_tsc) 602 rdtscll(tsc); 603 604 switch (lapic_cal_loops++) { 605 case 0: 606 lapic_cal_t1 = tapic; 607 lapic_cal_tsc1 = tsc; 608 lapic_cal_pm1 = pm; 609 lapic_cal_j1 = jiffies; 610 break; 611 612 case LAPIC_CAL_LOOPS: 613 lapic_cal_t2 = tapic; 614 lapic_cal_tsc2 = tsc; 615 if (pm < lapic_cal_pm1) 616 pm += ACPI_PM_OVRRUN; 617 lapic_cal_pm2 = pm; 618 lapic_cal_j2 = jiffies; 619 break; 620 } 621} 622 623static int __init 624calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 625{ 626 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 627 const long pm_thresh = pm_100ms / 100; 628 unsigned long mult; 629 u64 res; 630 631#ifndef CONFIG_X86_PM_TIMER 632 return -1; 633#endif 634 635 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 636 637 /* Check, if the PM timer is available */ 638 if (!deltapm) 639 return -1; 640 641 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 642 643 if (deltapm > (pm_100ms - pm_thresh) && 644 deltapm < (pm_100ms + pm_thresh)) { 645 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 646 return 0; 647 } 648 649 res = (((u64)deltapm) * mult) >> 22; 650 do_div(res, 1000000); 651 pr_warning("APIC calibration not consistent " 652 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 653 654 /* Correct the lapic counter value */ 655 res = (((u64)(*delta)) * pm_100ms); 656 do_div(res, deltapm); 657 pr_info("APIC delta adjusted to PM-Timer: " 658 "%lu (%ld)\n", (unsigned long)res, *delta); 659 *delta = (long)res; 660 661 /* Correct the tsc counter value */ 662 if (cpu_has_tsc) { 663 res = (((u64)(*deltatsc)) * pm_100ms); 664 do_div(res, deltapm); 665 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 666 "PM-Timer: %lu (%ld)\n", 667 (unsigned long)res, *deltatsc); 668 *deltatsc = (long)res; 669 } 670 671 return 0; 672} 673 674static int __init calibrate_APIC_clock(void) 675{ 676 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 677 void (*real_handler)(struct clock_event_device *dev); 678 unsigned long deltaj; 679 long delta, deltatsc; 680 int pm_referenced = 0; 681 682 /** 683 * check if lapic timer has already been calibrated by platform 684 * specific routine, such as tsc calibration code. if so, we just fill 685 * in the clockevent structure and return. 686 */ 687 688 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 689 return 0; 690 } else if (lapic_timer_frequency) { 691 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 692 lapic_timer_frequency); 693 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 694 TICK_NSEC, lapic_clockevent.shift); 695 lapic_clockevent.max_delta_ns = 696 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 697 lapic_clockevent.min_delta_ns = 698 clockevent_delta2ns(0xF, &lapic_clockevent); 699 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 700 return 0; 701 } 702 703 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 704 "calibrating APIC timer ...\n"); 705 706 local_irq_disable(); 707 708 /* Replace the global interrupt handler */ 709 real_handler = global_clock_event->event_handler; 710 global_clock_event->event_handler = lapic_cal_handler; 711 712 /* 713 * Setup the APIC counter to maximum. There is no way the lapic 714 * can underflow in the 100ms detection time frame 715 */ 716 __setup_APIC_LVTT(0xffffffff, 0, 0); 717 718 /* Let the interrupts run */ 719 local_irq_enable(); 720 721 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 722 cpu_relax(); 723 724 local_irq_disable(); 725 726 /* Restore the real event handler */ 727 global_clock_event->event_handler = real_handler; 728 729 /* Build delta t1-t2 as apic timer counts down */ 730 delta = lapic_cal_t1 - lapic_cal_t2; 731 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 732 733 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 734 735 /* we trust the PM based calibration if possible */ 736 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 737 &delta, &deltatsc); 738 739 /* Calculate the scaled math multiplication factor */ 740 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 741 lapic_clockevent.shift); 742 lapic_clockevent.max_delta_ns = 743 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 744 lapic_clockevent.min_delta_ns = 745 clockevent_delta2ns(0xF, &lapic_clockevent); 746 747 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 748 749 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 750 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 751 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 752 lapic_timer_frequency); 753 754 if (cpu_has_tsc) { 755 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 756 "%ld.%04ld MHz.\n", 757 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 758 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 759 } 760 761 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 762 "%u.%04u MHz.\n", 763 lapic_timer_frequency / (1000000 / HZ), 764 lapic_timer_frequency % (1000000 / HZ)); 765 766 /* 767 * Do a sanity check on the APIC calibration result 768 */ 769 if (lapic_timer_frequency < (1000000 / HZ)) { 770 local_irq_enable(); 771 pr_warning("APIC frequency too slow, disabling apic timer\n"); 772 return -1; 773 } 774 775 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 776 777 /* 778 * PM timer calibration failed or not turned on 779 * so lets try APIC timer based calibration 780 */ 781 if (!pm_referenced) { 782 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 783 784 /* 785 * Setup the apic timer manually 786 */ 787 levt->event_handler = lapic_cal_handler; 788 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 789 lapic_cal_loops = -1; 790 791 /* Let the interrupts run */ 792 local_irq_enable(); 793 794 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 795 cpu_relax(); 796 797 /* Stop the lapic timer */ 798 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 799 800 /* Jiffies delta */ 801 deltaj = lapic_cal_j2 - lapic_cal_j1; 802 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 803 804 /* Check, if the jiffies result is consistent */ 805 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 806 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 807 else 808 levt->features |= CLOCK_EVT_FEAT_DUMMY; 809 } else 810 local_irq_enable(); 811 812 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 813 pr_warning("APIC timer disabled due to verification failure\n"); 814 return -1; 815 } 816 817 return 0; 818} 819 820/* 821 * Setup the boot APIC 822 * 823 * Calibrate and verify the result. 824 */ 825void __init setup_boot_APIC_clock(void) 826{ 827 /* 828 * The local apic timer can be disabled via the kernel 829 * commandline or from the CPU detection code. Register the lapic 830 * timer as a dummy clock event source on SMP systems, so the 831 * broadcast mechanism is used. On UP systems simply ignore it. 832 */ 833 if (disable_apic_timer) { 834 pr_info("Disabling APIC timer\n"); 835 /* No broadcast on UP ! */ 836 if (num_possible_cpus() > 1) { 837 lapic_clockevent.mult = 1; 838 setup_APIC_timer(); 839 } 840 return; 841 } 842 843 if (calibrate_APIC_clock()) { 844 /* No broadcast on UP ! */ 845 if (num_possible_cpus() > 1) 846 setup_APIC_timer(); 847 return; 848 } 849 850 /* 851 * If nmi_watchdog is set to IO_APIC, we need the 852 * PIT/HPET going. Otherwise register lapic as a dummy 853 * device. 854 */ 855 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 856 857 /* Setup the lapic or request the broadcast */ 858 setup_APIC_timer(); 859} 860 861void setup_secondary_APIC_clock(void) 862{ 863 setup_APIC_timer(); 864} 865 866/* 867 * The guts of the apic timer interrupt 868 */ 869static void local_apic_timer_interrupt(void) 870{ 871 int cpu = smp_processor_id(); 872 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 873 874 /* 875 * Normally we should not be here till LAPIC has been initialized but 876 * in some cases like kdump, its possible that there is a pending LAPIC 877 * timer interrupt from previous kernel's context and is delivered in 878 * new kernel the moment interrupts are enabled. 879 * 880 * Interrupts are enabled early and LAPIC is setup much later, hence 881 * its possible that when we get here evt->event_handler is NULL. 882 * Check for event_handler being NULL and discard the interrupt as 883 * spurious. 884 */ 885 if (!evt->event_handler) { 886 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 887 /* Switch it off */ 888 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 889 return; 890 } 891 892 /* 893 * the NMI deadlock-detector uses this. 894 */ 895 inc_irq_stat(apic_timer_irqs); 896 897 evt->event_handler(evt); 898} 899 900/* 901 * Local APIC timer interrupt. This is the most natural way for doing 902 * local interrupts, but local timer interrupts can be emulated by 903 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 904 * 905 * [ if a single-CPU system runs an SMP kernel then we call the local 906 * interrupt as well. Thus we cannot inline the local irq ... ] 907 */ 908__visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 909{ 910 struct pt_regs *old_regs = set_irq_regs(regs); 911 912 /* 913 * NOTE! We'd better ACK the irq immediately, 914 * because timer handling can be slow. 915 * 916 * update_process_times() expects us to have done irq_enter(). 917 * Besides, if we don't timer interrupts ignore the global 918 * interrupt lock, which is the WrongThing (tm) to do. 919 */ 920 entering_ack_irq(); 921 local_apic_timer_interrupt(); 922 exiting_irq(); 923 924 set_irq_regs(old_regs); 925} 926 927__visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) 928{ 929 struct pt_regs *old_regs = set_irq_regs(regs); 930 931 /* 932 * NOTE! We'd better ACK the irq immediately, 933 * because timer handling can be slow. 934 * 935 * update_process_times() expects us to have done irq_enter(). 936 * Besides, if we don't timer interrupts ignore the global 937 * interrupt lock, which is the WrongThing (tm) to do. 938 */ 939 entering_ack_irq(); 940 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 941 local_apic_timer_interrupt(); 942 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 943 exiting_irq(); 944 945 set_irq_regs(old_regs); 946} 947 948int setup_profiling_timer(unsigned int multiplier) 949{ 950 return -EINVAL; 951} 952 953/* 954 * Local APIC start and shutdown 955 */ 956 957/** 958 * clear_local_APIC - shutdown the local APIC 959 * 960 * This is called, when a CPU is disabled and before rebooting, so the state of 961 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 962 * leftovers during boot. 963 */ 964void clear_local_APIC(void) 965{ 966 int maxlvt; 967 u32 v; 968 969 /* APIC hasn't been mapped yet */ 970 if (!x2apic_mode && !apic_phys) 971 return; 972 973 maxlvt = lapic_get_maxlvt(); 974 /* 975 * Masking an LVT entry can trigger a local APIC error 976 * if the vector is zero. Mask LVTERR first to prevent this. 977 */ 978 if (maxlvt >= 3) { 979 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 980 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 981 } 982 /* 983 * Careful: we have to set masks only first to deassert 984 * any level-triggered sources. 985 */ 986 v = apic_read(APIC_LVTT); 987 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 988 v = apic_read(APIC_LVT0); 989 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 990 v = apic_read(APIC_LVT1); 991 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 992 if (maxlvt >= 4) { 993 v = apic_read(APIC_LVTPC); 994 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 995 } 996 997 /* lets not touch this if we didn't frob it */ 998#ifdef CONFIG_X86_THERMAL_VECTOR 999 if (maxlvt >= 5) { 1000 v = apic_read(APIC_LVTTHMR); 1001 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1002 } 1003#endif 1004#ifdef CONFIG_X86_MCE_INTEL 1005 if (maxlvt >= 6) { 1006 v = apic_read(APIC_LVTCMCI); 1007 if (!(v & APIC_LVT_MASKED)) 1008 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1009 } 1010#endif 1011 1012 /* 1013 * Clean APIC state for other OSs: 1014 */ 1015 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1016 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1017 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1018 if (maxlvt >= 3) 1019 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1020 if (maxlvt >= 4) 1021 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1022 1023 /* Integrated APIC (!82489DX) ? */ 1024 if (lapic_is_integrated()) { 1025 if (maxlvt > 3) 1026 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1027 apic_write(APIC_ESR, 0); 1028 apic_read(APIC_ESR); 1029 } 1030} 1031 1032/** 1033 * disable_local_APIC - clear and disable the local APIC 1034 */ 1035void disable_local_APIC(void) 1036{ 1037 unsigned int value; 1038 1039 /* APIC hasn't been mapped yet */ 1040 if (!x2apic_mode && !apic_phys) 1041 return; 1042 1043 clear_local_APIC(); 1044 1045 /* 1046 * Disable APIC (implies clearing of registers 1047 * for 82489DX!). 1048 */ 1049 value = apic_read(APIC_SPIV); 1050 value &= ~APIC_SPIV_APIC_ENABLED; 1051 apic_write(APIC_SPIV, value); 1052 1053#ifdef CONFIG_X86_32 1054 /* 1055 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1056 * restore the disabled state. 1057 */ 1058 if (enabled_via_apicbase) { 1059 unsigned int l, h; 1060 1061 rdmsr(MSR_IA32_APICBASE, l, h); 1062 l &= ~MSR_IA32_APICBASE_ENABLE; 1063 wrmsr(MSR_IA32_APICBASE, l, h); 1064 } 1065#endif 1066} 1067 1068/* 1069 * If Linux enabled the LAPIC against the BIOS default disable it down before 1070 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1071 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1072 * for the case where Linux didn't enable the LAPIC. 1073 */ 1074void lapic_shutdown(void) 1075{ 1076 unsigned long flags; 1077 1078 if (!cpu_has_apic && !apic_from_smp_config()) 1079 return; 1080 1081 local_irq_save(flags); 1082 1083#ifdef CONFIG_X86_32 1084 if (!enabled_via_apicbase) 1085 clear_local_APIC(); 1086 else 1087#endif 1088 disable_local_APIC(); 1089 1090 1091 local_irq_restore(flags); 1092} 1093 1094/** 1095 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1096 */ 1097void __init sync_Arb_IDs(void) 1098{ 1099 /* 1100 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1101 * needed on AMD. 1102 */ 1103 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1104 return; 1105 1106 /* 1107 * Wait for idle. 1108 */ 1109 apic_wait_icr_idle(); 1110 1111 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1112 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1113 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1114} 1115 1116/* 1117 * An initial setup of the virtual wire mode. 1118 */ 1119void __init init_bsp_APIC(void) 1120{ 1121 unsigned int value; 1122 1123 /* 1124 * Don't do the setup now if we have a SMP BIOS as the 1125 * through-I/O-APIC virtual wire mode might be active. 1126 */ 1127 if (smp_found_config || !cpu_has_apic) 1128 return; 1129 1130 /* 1131 * Do not trust the local APIC being empty at bootup. 1132 */ 1133 clear_local_APIC(); 1134 1135 /* 1136 * Enable APIC. 1137 */ 1138 value = apic_read(APIC_SPIV); 1139 value &= ~APIC_VECTOR_MASK; 1140 value |= APIC_SPIV_APIC_ENABLED; 1141 1142#ifdef CONFIG_X86_32 1143 /* This bit is reserved on P4/Xeon and should be cleared */ 1144 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1145 (boot_cpu_data.x86 == 15)) 1146 value &= ~APIC_SPIV_FOCUS_DISABLED; 1147 else 1148#endif 1149 value |= APIC_SPIV_FOCUS_DISABLED; 1150 value |= SPURIOUS_APIC_VECTOR; 1151 apic_write(APIC_SPIV, value); 1152 1153 /* 1154 * Set up the virtual wire mode. 1155 */ 1156 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1157 value = APIC_DM_NMI; 1158 if (!lapic_is_integrated()) /* 82489DX */ 1159 value |= APIC_LVT_LEVEL_TRIGGER; 1160 apic_write(APIC_LVT1, value); 1161} 1162 1163static void lapic_setup_esr(void) 1164{ 1165 unsigned int oldvalue, value, maxlvt; 1166 1167 if (!lapic_is_integrated()) { 1168 pr_info("No ESR for 82489DX.\n"); 1169 return; 1170 } 1171 1172 if (apic->disable_esr) { 1173 /* 1174 * Something untraceable is creating bad interrupts on 1175 * secondary quads ... for the moment, just leave the 1176 * ESR disabled - we can't do anything useful with the 1177 * errors anyway - mbligh 1178 */ 1179 pr_info("Leaving ESR disabled.\n"); 1180 return; 1181 } 1182 1183 maxlvt = lapic_get_maxlvt(); 1184 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1185 apic_write(APIC_ESR, 0); 1186 oldvalue = apic_read(APIC_ESR); 1187 1188 /* enables sending errors */ 1189 value = ERROR_APIC_VECTOR; 1190 apic_write(APIC_LVTERR, value); 1191 1192 /* 1193 * spec says clear errors after enabling vector. 1194 */ 1195 if (maxlvt > 3) 1196 apic_write(APIC_ESR, 0); 1197 value = apic_read(APIC_ESR); 1198 if (value != oldvalue) 1199 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1200 "vector: 0x%08x after: 0x%08x\n", 1201 oldvalue, value); 1202} 1203 1204/** 1205 * setup_local_APIC - setup the local APIC 1206 * 1207 * Used to setup local APIC while initializing BSP or bringin up APs. 1208 * Always called with preemption disabled. 1209 */ 1210void setup_local_APIC(void) 1211{ 1212 int cpu = smp_processor_id(); 1213 unsigned int value, queued; 1214 int i, j, acked = 0; 1215 unsigned long long tsc = 0, ntsc; 1216 long long max_loops = cpu_khz ? cpu_khz : 1000000; 1217 1218 if (cpu_has_tsc) 1219 rdtscll(tsc); 1220 1221 if (disable_apic) { 1222 disable_ioapic_support(); 1223 return; 1224 } 1225 1226#ifdef CONFIG_X86_32 1227 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1228 if (lapic_is_integrated() && apic->disable_esr) { 1229 apic_write(APIC_ESR, 0); 1230 apic_write(APIC_ESR, 0); 1231 apic_write(APIC_ESR, 0); 1232 apic_write(APIC_ESR, 0); 1233 } 1234#endif 1235 perf_events_lapic_init(); 1236 1237 /* 1238 * Double-check whether this APIC is really registered. 1239 * This is meaningless in clustered apic mode, so we skip it. 1240 */ 1241 BUG_ON(!apic->apic_id_registered()); 1242 1243 /* 1244 * Intel recommends to set DFR, LDR and TPR before enabling 1245 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1246 * document number 292116). So here it goes... 1247 */ 1248 apic->init_apic_ldr(); 1249 1250#ifdef CONFIG_X86_32 1251 /* 1252 * APIC LDR is initialized. If logical_apicid mapping was 1253 * initialized during get_smp_config(), make sure it matches the 1254 * actual value. 1255 */ 1256 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1257 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1258 /* always use the value from LDR */ 1259 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1260 logical_smp_processor_id(); 1261#endif 1262 1263 /* 1264 * Set Task Priority to 'accept all'. We never change this 1265 * later on. 1266 */ 1267 value = apic_read(APIC_TASKPRI); 1268 value &= ~APIC_TPRI_MASK; 1269 apic_write(APIC_TASKPRI, value); 1270 1271 /* 1272 * After a crash, we no longer service the interrupts and a pending 1273 * interrupt from previous kernel might still have ISR bit set. 1274 * 1275 * Most probably by now CPU has serviced that pending interrupt and 1276 * it might not have done the ack_APIC_irq() because it thought, 1277 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1278 * does not clear the ISR bit and cpu thinks it has already serivced 1279 * the interrupt. Hence a vector might get locked. It was noticed 1280 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1281 */ 1282 do { 1283 queued = 0; 1284 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1285 queued |= apic_read(APIC_IRR + i*0x10); 1286 1287 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1288 value = apic_read(APIC_ISR + i*0x10); 1289 for (j = 31; j >= 0; j--) { 1290 if (value & (1<<j)) { 1291 ack_APIC_irq(); 1292 acked++; 1293 } 1294 } 1295 } 1296 if (acked > 256) { 1297 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 1298 acked); 1299 break; 1300 } 1301 if (queued) { 1302 if (cpu_has_tsc && cpu_khz) { 1303 rdtscll(ntsc); 1304 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1305 } else 1306 max_loops--; 1307 } 1308 } while (queued && max_loops > 0); 1309 WARN_ON(max_loops <= 0); 1310 1311 /* 1312 * Now that we are all set up, enable the APIC 1313 */ 1314 value = apic_read(APIC_SPIV); 1315 value &= ~APIC_VECTOR_MASK; 1316 /* 1317 * Enable APIC 1318 */ 1319 value |= APIC_SPIV_APIC_ENABLED; 1320 1321#ifdef CONFIG_X86_32 1322 /* 1323 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1324 * certain networking cards. If high frequency interrupts are 1325 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1326 * entry is masked/unmasked at a high rate as well then sooner or 1327 * later IOAPIC line gets 'stuck', no more interrupts are received 1328 * from the device. If focus CPU is disabled then the hang goes 1329 * away, oh well :-( 1330 * 1331 * [ This bug can be reproduced easily with a level-triggered 1332 * PCI Ne2000 networking cards and PII/PIII processors, dual 1333 * BX chipset. ] 1334 */ 1335 /* 1336 * Actually disabling the focus CPU check just makes the hang less 1337 * frequent as it makes the interrupt distributon model be more 1338 * like LRU than MRU (the short-term load is more even across CPUs). 1339 * See also the comment in end_level_ioapic_irq(). --macro 1340 */ 1341 1342 /* 1343 * - enable focus processor (bit==0) 1344 * - 64bit mode always use processor focus 1345 * so no need to set it 1346 */ 1347 value &= ~APIC_SPIV_FOCUS_DISABLED; 1348#endif 1349 1350 /* 1351 * Set spurious IRQ vector 1352 */ 1353 value |= SPURIOUS_APIC_VECTOR; 1354 apic_write(APIC_SPIV, value); 1355 1356 /* 1357 * Set up LVT0, LVT1: 1358 * 1359 * set up through-local-APIC on the BP's LINT0. This is not 1360 * strictly necessary in pure symmetric-IO mode, but sometimes 1361 * we delegate interrupts to the 8259A. 1362 */ 1363 /* 1364 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1365 */ 1366 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1367 if (!cpu && (pic_mode || !value)) { 1368 value = APIC_DM_EXTINT; 1369 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1370 } else { 1371 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1372 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1373 } 1374 apic_write(APIC_LVT0, value); 1375 1376 /* 1377 * only the BP should see the LINT1 NMI signal, obviously. 1378 */ 1379 if (!cpu) 1380 value = APIC_DM_NMI; 1381 else 1382 value = APIC_DM_NMI | APIC_LVT_MASKED; 1383 if (!lapic_is_integrated()) /* 82489DX */ 1384 value |= APIC_LVT_LEVEL_TRIGGER; 1385 apic_write(APIC_LVT1, value); 1386 1387#ifdef CONFIG_X86_MCE_INTEL 1388 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1389 if (!cpu) 1390 cmci_recheck(); 1391#endif 1392} 1393 1394static void end_local_APIC_setup(void) 1395{ 1396 lapic_setup_esr(); 1397 1398#ifdef CONFIG_X86_32 1399 { 1400 unsigned int value; 1401 /* Disable the local apic timer */ 1402 value = apic_read(APIC_LVTT); 1403 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1404 apic_write(APIC_LVTT, value); 1405 } 1406#endif 1407 1408 apic_pm_activate(); 1409} 1410 1411/* 1412 * APIC setup function for application processors. Called from smpboot.c 1413 */ 1414void apic_ap_setup(void) 1415{ 1416 setup_local_APIC(); 1417 end_local_APIC_setup(); 1418} 1419 1420#ifdef CONFIG_X86_X2APIC 1421int x2apic_mode; 1422 1423enum { 1424 X2APIC_OFF, 1425 X2APIC_ON, 1426 X2APIC_DISABLED, 1427}; 1428static int x2apic_state; 1429 1430static inline void __x2apic_disable(void) 1431{ 1432 u64 msr; 1433 1434 if (!cpu_has_apic) 1435 return; 1436 1437 rdmsrl(MSR_IA32_APICBASE, msr); 1438 if (!(msr & X2APIC_ENABLE)) 1439 return; 1440 /* Disable xapic and x2apic first and then reenable xapic mode */ 1441 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1442 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1443 printk_once(KERN_INFO "x2apic disabled\n"); 1444} 1445 1446static inline void __x2apic_enable(void) 1447{ 1448 u64 msr; 1449 1450 rdmsrl(MSR_IA32_APICBASE, msr); 1451 if (msr & X2APIC_ENABLE) 1452 return; 1453 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1454 printk_once(KERN_INFO "x2apic enabled\n"); 1455} 1456 1457static int __init setup_nox2apic(char *str) 1458{ 1459 if (x2apic_enabled()) { 1460 int apicid = native_apic_msr_read(APIC_ID); 1461 1462 if (apicid >= 255) { 1463 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1464 apicid); 1465 return 0; 1466 } 1467 pr_warning("x2apic already enabled.\n"); 1468 __x2apic_disable(); 1469 } 1470 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1471 x2apic_state = X2APIC_DISABLED; 1472 x2apic_mode = 0; 1473 return 0; 1474} 1475early_param("nox2apic", setup_nox2apic); 1476 1477/* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1478void x2apic_setup(void) 1479{ 1480 /* 1481 * If x2apic is not in ON state, disable it if already enabled 1482 * from BIOS. 1483 */ 1484 if (x2apic_state != X2APIC_ON) { 1485 __x2apic_disable(); 1486 return; 1487 } 1488 __x2apic_enable(); 1489} 1490 1491static __init void x2apic_disable(void) 1492{ 1493 u32 x2apic_id, state = x2apic_state; 1494 1495 x2apic_mode = 0; 1496 x2apic_state = X2APIC_DISABLED; 1497 1498 if (state != X2APIC_ON) 1499 return; 1500 1501 x2apic_id = read_apic_id(); 1502 if (x2apic_id >= 255) 1503 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1504 1505 __x2apic_disable(); 1506 register_lapic_address(mp_lapic_addr); 1507} 1508 1509static __init void x2apic_enable(void) 1510{ 1511 if (x2apic_state != X2APIC_OFF) 1512 return; 1513 1514 x2apic_mode = 1; 1515 x2apic_state = X2APIC_ON; 1516 __x2apic_enable(); 1517} 1518 1519static __init void try_to_enable_x2apic(int remap_mode) 1520{ 1521 if (x2apic_state == X2APIC_DISABLED) 1522 return; 1523 1524 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1525 /* IR is required if there is APIC ID > 255 even when running 1526 * under KVM 1527 */ 1528 if (max_physical_apicid > 255 || 1529 !hypervisor_x2apic_available()) { 1530 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1531 x2apic_disable(); 1532 return; 1533 } 1534 1535 /* 1536 * without IR all CPUs can be addressed by IOAPIC/MSI 1537 * only in physical mode 1538 */ 1539 x2apic_phys = 1; 1540 } 1541 x2apic_enable(); 1542} 1543 1544void __init check_x2apic(void) 1545{ 1546 if (x2apic_enabled()) { 1547 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1548 x2apic_mode = 1; 1549 x2apic_state = X2APIC_ON; 1550 } else if (!cpu_has_x2apic) { 1551 x2apic_state = X2APIC_DISABLED; 1552 } 1553} 1554#else /* CONFIG_X86_X2APIC */ 1555static int __init validate_x2apic(void) 1556{ 1557 if (!apic_is_x2apic_enabled()) 1558 return 0; 1559 /* 1560 * Checkme: Can we simply turn off x2apic here instead of panic? 1561 */ 1562 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1563} 1564early_initcall(validate_x2apic); 1565 1566static inline void try_to_enable_x2apic(int remap_mode) { } 1567static inline void __x2apic_enable(void) { } 1568#endif /* !CONFIG_X86_X2APIC */ 1569 1570static int __init try_to_enable_IR(void) 1571{ 1572#ifdef CONFIG_X86_IO_APIC 1573 if (!x2apic_enabled() && skip_ioapic_setup) { 1574 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1575 return -1; 1576 } 1577#endif 1578 return irq_remapping_enable(); 1579} 1580 1581void __init enable_IR_x2apic(void) 1582{ 1583 unsigned long flags; 1584 int ret, ir_stat; 1585 1586 ir_stat = irq_remapping_prepare(); 1587 if (ir_stat < 0 && !x2apic_supported()) 1588 return; 1589 1590 ret = save_ioapic_entries(); 1591 if (ret) { 1592 pr_info("Saving IO-APIC state failed: %d\n", ret); 1593 return; 1594 } 1595 1596 local_irq_save(flags); 1597 legacy_pic->mask_all(); 1598 mask_ioapic_entries(); 1599 1600 /* If irq_remapping_prepare() succeded, try to enable it */ 1601 if (ir_stat >= 0) 1602 ir_stat = try_to_enable_IR(); 1603 /* ir_stat contains the remap mode or an error code */ 1604 try_to_enable_x2apic(ir_stat); 1605 1606 if (ir_stat < 0) 1607 restore_ioapic_entries(); 1608 legacy_pic->restore_mask(); 1609 local_irq_restore(flags); 1610} 1611 1612#ifdef CONFIG_X86_64 1613/* 1614 * Detect and enable local APICs on non-SMP boards. 1615 * Original code written by Keir Fraser. 1616 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1617 * not correctly set up (usually the APIC timer won't work etc.) 1618 */ 1619static int __init detect_init_APIC(void) 1620{ 1621 if (!cpu_has_apic) { 1622 pr_info("No local APIC present\n"); 1623 return -1; 1624 } 1625 1626 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1627 return 0; 1628} 1629#else 1630 1631static int __init apic_verify(void) 1632{ 1633 u32 features, h, l; 1634 1635 /* 1636 * The APIC feature bit should now be enabled 1637 * in `cpuid' 1638 */ 1639 features = cpuid_edx(1); 1640 if (!(features & (1 << X86_FEATURE_APIC))) { 1641 pr_warning("Could not enable APIC!\n"); 1642 return -1; 1643 } 1644 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1645 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1646 1647 /* The BIOS may have set up the APIC at some other address */ 1648 if (boot_cpu_data.x86 >= 6) { 1649 rdmsr(MSR_IA32_APICBASE, l, h); 1650 if (l & MSR_IA32_APICBASE_ENABLE) 1651 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1652 } 1653 1654 pr_info("Found and enabled local APIC!\n"); 1655 return 0; 1656} 1657 1658int __init apic_force_enable(unsigned long addr) 1659{ 1660 u32 h, l; 1661 1662 if (disable_apic) 1663 return -1; 1664 1665 /* 1666 * Some BIOSes disable the local APIC in the APIC_BASE 1667 * MSR. This can only be done in software for Intel P6 or later 1668 * and AMD K7 (Model > 1) or later. 1669 */ 1670 if (boot_cpu_data.x86 >= 6) { 1671 rdmsr(MSR_IA32_APICBASE, l, h); 1672 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1673 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1674 l &= ~MSR_IA32_APICBASE_BASE; 1675 l |= MSR_IA32_APICBASE_ENABLE | addr; 1676 wrmsr(MSR_IA32_APICBASE, l, h); 1677 enabled_via_apicbase = 1; 1678 } 1679 } 1680 return apic_verify(); 1681} 1682 1683/* 1684 * Detect and initialize APIC 1685 */ 1686static int __init detect_init_APIC(void) 1687{ 1688 /* Disabled by kernel option? */ 1689 if (disable_apic) 1690 return -1; 1691 1692 switch (boot_cpu_data.x86_vendor) { 1693 case X86_VENDOR_AMD: 1694 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1695 (boot_cpu_data.x86 >= 15)) 1696 break; 1697 goto no_apic; 1698 case X86_VENDOR_INTEL: 1699 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1700 (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1701 break; 1702 goto no_apic; 1703 default: 1704 goto no_apic; 1705 } 1706 1707 if (!cpu_has_apic) { 1708 /* 1709 * Over-ride BIOS and try to enable the local APIC only if 1710 * "lapic" specified. 1711 */ 1712 if (!force_enable_local_apic) { 1713 pr_info("Local APIC disabled by BIOS -- " 1714 "you can enable it with \"lapic\"\n"); 1715 return -1; 1716 } 1717 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1718 return -1; 1719 } else { 1720 if (apic_verify()) 1721 return -1; 1722 } 1723 1724 apic_pm_activate(); 1725 1726 return 0; 1727 1728no_apic: 1729 pr_info("No local APIC present or hardware disabled\n"); 1730 return -1; 1731} 1732#endif 1733 1734/** 1735 * init_apic_mappings - initialize APIC mappings 1736 */ 1737void __init init_apic_mappings(void) 1738{ 1739 unsigned int new_apicid; 1740 1741 if (x2apic_mode) { 1742 boot_cpu_physical_apicid = read_apic_id(); 1743 return; 1744 } 1745 1746 /* If no local APIC can be found return early */ 1747 if (!smp_found_config && detect_init_APIC()) { 1748 /* lets NOP'ify apic operations */ 1749 pr_info("APIC: disable apic facility\n"); 1750 apic_disable(); 1751 } else { 1752 apic_phys = mp_lapic_addr; 1753 1754 /* 1755 * acpi lapic path already maps that address in 1756 * acpi_register_lapic_address() 1757 */ 1758 if (!acpi_lapic && !smp_found_config) 1759 register_lapic_address(apic_phys); 1760 } 1761 1762 /* 1763 * Fetch the APIC ID of the BSP in case we have a 1764 * default configuration (or the MP table is broken). 1765 */ 1766 new_apicid = read_apic_id(); 1767 if (boot_cpu_physical_apicid != new_apicid) { 1768 boot_cpu_physical_apicid = new_apicid; 1769 /* 1770 * yeah -- we lie about apic_version 1771 * in case if apic was disabled via boot option 1772 * but it's not a problem for SMP compiled kernel 1773 * since smp_sanity_check is prepared for such a case 1774 * and disable smp mode 1775 */ 1776 apic_version[new_apicid] = 1777 GET_APIC_VERSION(apic_read(APIC_LVR)); 1778 } 1779} 1780 1781void __init register_lapic_address(unsigned long address) 1782{ 1783 mp_lapic_addr = address; 1784 1785 if (!x2apic_mode) { 1786 set_fixmap_nocache(FIX_APIC_BASE, address); 1787 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1788 APIC_BASE, mp_lapic_addr); 1789 } 1790 if (boot_cpu_physical_apicid == -1U) { 1791 boot_cpu_physical_apicid = read_apic_id(); 1792 apic_version[boot_cpu_physical_apicid] = 1793 GET_APIC_VERSION(apic_read(APIC_LVR)); 1794 } 1795} 1796 1797int apic_version[MAX_LOCAL_APIC]; 1798 1799/* 1800 * Local APIC interrupts 1801 */ 1802 1803/* 1804 * This interrupt should _never_ happen with our APIC/SMP architecture 1805 */ 1806static inline void __smp_spurious_interrupt(u8 vector) 1807{ 1808 u32 v; 1809 1810 /* 1811 * Check if this really is a spurious interrupt and ACK it 1812 * if it is a vectored one. Just in case... 1813 * Spurious interrupts should not be ACKed. 1814 */ 1815 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 1816 if (v & (1 << (vector & 0x1f))) 1817 ack_APIC_irq(); 1818 1819 inc_irq_stat(irq_spurious_count); 1820 1821 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1822 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 1823 "should never happen.\n", vector, smp_processor_id()); 1824} 1825 1826__visible void smp_spurious_interrupt(struct pt_regs *regs) 1827{ 1828 entering_irq(); 1829 __smp_spurious_interrupt(~regs->orig_ax); 1830 exiting_irq(); 1831} 1832 1833__visible void smp_trace_spurious_interrupt(struct pt_regs *regs) 1834{ 1835 u8 vector = ~regs->orig_ax; 1836 1837 entering_irq(); 1838 trace_spurious_apic_entry(vector); 1839 __smp_spurious_interrupt(vector); 1840 trace_spurious_apic_exit(vector); 1841 exiting_irq(); 1842} 1843 1844/* 1845 * This interrupt should never happen with our APIC/SMP architecture 1846 */ 1847static inline void __smp_error_interrupt(struct pt_regs *regs) 1848{ 1849 u32 v; 1850 u32 i = 0; 1851 static const char * const error_interrupt_reason[] = { 1852 "Send CS error", /* APIC Error Bit 0 */ 1853 "Receive CS error", /* APIC Error Bit 1 */ 1854 "Send accept error", /* APIC Error Bit 2 */ 1855 "Receive accept error", /* APIC Error Bit 3 */ 1856 "Redirectable IPI", /* APIC Error Bit 4 */ 1857 "Send illegal vector", /* APIC Error Bit 5 */ 1858 "Received illegal vector", /* APIC Error Bit 6 */ 1859 "Illegal register address", /* APIC Error Bit 7 */ 1860 }; 1861 1862 /* First tickle the hardware, only then report what went on. -- REW */ 1863 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 1864 apic_write(APIC_ESR, 0); 1865 v = apic_read(APIC_ESR); 1866 ack_APIC_irq(); 1867 atomic_inc(&irq_err_count); 1868 1869 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 1870 smp_processor_id(), v); 1871 1872 v &= 0xff; 1873 while (v) { 1874 if (v & 0x1) 1875 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 1876 i++; 1877 v >>= 1; 1878 } 1879 1880 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 1881 1882} 1883 1884__visible void smp_error_interrupt(struct pt_regs *regs) 1885{ 1886 entering_irq(); 1887 __smp_error_interrupt(regs); 1888 exiting_irq(); 1889} 1890 1891__visible void smp_trace_error_interrupt(struct pt_regs *regs) 1892{ 1893 entering_irq(); 1894 trace_error_apic_entry(ERROR_APIC_VECTOR); 1895 __smp_error_interrupt(regs); 1896 trace_error_apic_exit(ERROR_APIC_VECTOR); 1897 exiting_irq(); 1898} 1899 1900/** 1901 * connect_bsp_APIC - attach the APIC to the interrupt system 1902 */ 1903static void __init connect_bsp_APIC(void) 1904{ 1905#ifdef CONFIG_X86_32 1906 if (pic_mode) { 1907 /* 1908 * Do not trust the local APIC being empty at bootup. 1909 */ 1910 clear_local_APIC(); 1911 /* 1912 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1913 * local APIC to INT and NMI lines. 1914 */ 1915 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1916 "enabling APIC mode.\n"); 1917 imcr_pic_to_apic(); 1918 } 1919#endif 1920} 1921 1922/** 1923 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1924 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1925 * 1926 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1927 * APIC is disabled. 1928 */ 1929void disconnect_bsp_APIC(int virt_wire_setup) 1930{ 1931 unsigned int value; 1932 1933#ifdef CONFIG_X86_32 1934 if (pic_mode) { 1935 /* 1936 * Put the board back into PIC mode (has an effect only on 1937 * certain older boards). Note that APIC interrupts, including 1938 * IPIs, won't work beyond this point! The only exception are 1939 * INIT IPIs. 1940 */ 1941 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1942 "entering PIC mode.\n"); 1943 imcr_apic_to_pic(); 1944 return; 1945 } 1946#endif 1947 1948 /* Go back to Virtual Wire compatibility mode */ 1949 1950 /* For the spurious interrupt use vector F, and enable it */ 1951 value = apic_read(APIC_SPIV); 1952 value &= ~APIC_VECTOR_MASK; 1953 value |= APIC_SPIV_APIC_ENABLED; 1954 value |= 0xf; 1955 apic_write(APIC_SPIV, value); 1956 1957 if (!virt_wire_setup) { 1958 /* 1959 * For LVT0 make it edge triggered, active high, 1960 * external and enabled 1961 */ 1962 value = apic_read(APIC_LVT0); 1963 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1964 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1965 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1966 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1967 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1968 apic_write(APIC_LVT0, value); 1969 } else { 1970 /* Disable LVT0 */ 1971 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1972 } 1973 1974 /* 1975 * For LVT1 make it edge triggered, active high, 1976 * nmi and enabled 1977 */ 1978 value = apic_read(APIC_LVT1); 1979 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1980 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1981 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1982 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1983 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1984 apic_write(APIC_LVT1, value); 1985} 1986 1987int generic_processor_info(int apicid, int version) 1988{ 1989 int cpu, max = nr_cpu_ids; 1990 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 1991 phys_cpu_present_map); 1992 1993 /* 1994 * boot_cpu_physical_apicid is designed to have the apicid 1995 * returned by read_apic_id(), i.e, the apicid of the 1996 * currently booting-up processor. However, on some platforms, 1997 * it is temporarily modified by the apicid reported as BSP 1998 * through MP table. Concretely: 1999 * 2000 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2001 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2002 * 2003 * This function is executed with the modified 2004 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2005 * parameter doesn't work to disable APs on kdump 2nd kernel. 2006 * 2007 * Since fixing handling of boot_cpu_physical_apicid requires 2008 * another discussion and tests on each platform, we leave it 2009 * for now and here we use read_apic_id() directly in this 2010 * function, generic_processor_info(). 2011 */ 2012 if (disabled_cpu_apicid != BAD_APICID && 2013 disabled_cpu_apicid != read_apic_id() && 2014 disabled_cpu_apicid == apicid) { 2015 int thiscpu = num_processors + disabled_cpus; 2016 2017 pr_warning("APIC: Disabling requested cpu." 2018 " Processor %d/0x%x ignored.\n", 2019 thiscpu, apicid); 2020 2021 disabled_cpus++; 2022 return -ENODEV; 2023 } 2024 2025 /* 2026 * If boot cpu has not been detected yet, then only allow upto 2027 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2028 */ 2029 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2030 apicid != boot_cpu_physical_apicid) { 2031 int thiscpu = max + disabled_cpus - 1; 2032 2033 pr_warning( 2034 "ACPI: NR_CPUS/possible_cpus limit of %i almost" 2035 " reached. Keeping one slot for boot cpu." 2036 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2037 2038 disabled_cpus++; 2039 return -ENODEV; 2040 } 2041 2042 if (num_processors >= nr_cpu_ids) { 2043 int thiscpu = max + disabled_cpus; 2044 2045 pr_warning( 2046 "ACPI: NR_CPUS/possible_cpus limit of %i reached." 2047 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2048 2049 disabled_cpus++; 2050 return -EINVAL; 2051 } 2052 2053 num_processors++; 2054 if (apicid == boot_cpu_physical_apicid) { 2055 /* 2056 * x86_bios_cpu_apicid is required to have processors listed 2057 * in same order as logical cpu numbers. Hence the first 2058 * entry is BSP, and so on. 2059 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2060 * for BSP. 2061 */ 2062 cpu = 0; 2063 } else 2064 cpu = cpumask_next_zero(-1, cpu_present_mask); 2065 2066 /* 2067 * Validate version 2068 */ 2069 if (version == 0x0) { 2070 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2071 cpu, apicid); 2072 version = 0x10; 2073 } 2074 apic_version[apicid] = version; 2075 2076 if (version != apic_version[boot_cpu_physical_apicid]) { 2077 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2078 apic_version[boot_cpu_physical_apicid], cpu, version); 2079 } 2080 2081 physid_set(apicid, phys_cpu_present_map); 2082 if (apicid > max_physical_apicid) 2083 max_physical_apicid = apicid; 2084 2085#if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2086 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2087 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2088#endif 2089#ifdef CONFIG_X86_32 2090 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2091 apic->x86_32_early_logical_apicid(cpu); 2092#endif 2093 set_cpu_possible(cpu, true); 2094 set_cpu_present(cpu, true); 2095 2096 return cpu; 2097} 2098 2099int hard_smp_processor_id(void) 2100{ 2101 return read_apic_id(); 2102} 2103 2104void default_init_apic_ldr(void) 2105{ 2106 unsigned long val; 2107 2108 apic_write(APIC_DFR, APIC_DFR_VALUE); 2109 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2110 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2111 apic_write(APIC_LDR, val); 2112} 2113 2114int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 2115 const struct cpumask *andmask, 2116 unsigned int *apicid) 2117{ 2118 unsigned int cpu; 2119 2120 for_each_cpu_and(cpu, cpumask, andmask) { 2121 if (cpumask_test_cpu(cpu, cpu_online_mask)) 2122 break; 2123 } 2124 2125 if (likely(cpu < nr_cpu_ids)) { 2126 *apicid = per_cpu(x86_cpu_to_apicid, cpu); 2127 return 0; 2128 } 2129 2130 return -EINVAL; 2131} 2132 2133/* 2134 * Override the generic EOI implementation with an optimized version. 2135 * Only called during early boot when only one CPU is active and with 2136 * interrupts disabled, so we know this does not race with actual APIC driver 2137 * use. 2138 */ 2139void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2140{ 2141 struct apic **drv; 2142 2143 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2144 /* Should happen once for each apic */ 2145 WARN_ON((*drv)->eoi_write == eoi_write); 2146 (*drv)->eoi_write = eoi_write; 2147 } 2148} 2149 2150static void __init apic_bsp_up_setup(void) 2151{ 2152#ifdef CONFIG_X86_64 2153 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 2154#else 2155 /* 2156 * Hack: In case of kdump, after a crash, kernel might be booting 2157 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2158 * might be zero if read from MP tables. Get it from LAPIC. 2159 */ 2160# ifdef CONFIG_CRASH_DUMP 2161 boot_cpu_physical_apicid = read_apic_id(); 2162# endif 2163#endif 2164 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2165} 2166 2167/** 2168 * apic_bsp_setup - Setup function for local apic and io-apic 2169 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2170 * 2171 * Returns: 2172 * apic_id of BSP APIC 2173 */ 2174int __init apic_bsp_setup(bool upmode) 2175{ 2176 int id; 2177 2178 connect_bsp_APIC(); 2179 if (upmode) 2180 apic_bsp_up_setup(); 2181 setup_local_APIC(); 2182 2183 if (x2apic_mode) 2184 id = apic_read(APIC_LDR); 2185 else 2186 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 2187 2188 enable_IO_APIC(); 2189 end_local_APIC_setup(); 2190 irq_remap_enable_fault_handling(); 2191 setup_IO_APIC(); 2192 /* Setup local timer */ 2193 x86_init.timers.setup_percpu_clockev(); 2194 return id; 2195} 2196 2197/* 2198 * This initializes the IO-APIC and APIC hardware if this is 2199 * a UP kernel. 2200 */ 2201int __init APIC_init_uniprocessor(void) 2202{ 2203 if (disable_apic) { 2204 pr_info("Apic disabled\n"); 2205 return -1; 2206 } 2207#ifdef CONFIG_X86_64 2208 if (!cpu_has_apic) { 2209 disable_apic = 1; 2210 pr_info("Apic disabled by BIOS\n"); 2211 return -1; 2212 } 2213#else 2214 if (!smp_found_config && !cpu_has_apic) 2215 return -1; 2216 2217 /* 2218 * Complain if the BIOS pretends there is one. 2219 */ 2220 if (!cpu_has_apic && 2221 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 2222 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 2223 boot_cpu_physical_apicid); 2224 return -1; 2225 } 2226#endif 2227 2228 if (!smp_found_config) 2229 disable_ioapic_support(); 2230 2231 default_setup_apic_routing(); 2232 apic_bsp_setup(true); 2233 return 0; 2234} 2235 2236#ifdef CONFIG_UP_LATE_INIT 2237void __init up_late_init(void) 2238{ 2239 APIC_init_uniprocessor(); 2240} 2241#endif 2242 2243/* 2244 * Power management 2245 */ 2246#ifdef CONFIG_PM 2247 2248static struct { 2249 /* 2250 * 'active' is true if the local APIC was enabled by us and 2251 * not the BIOS; this signifies that we are also responsible 2252 * for disabling it before entering apm/acpi suspend 2253 */ 2254 int active; 2255 /* r/w apic fields */ 2256 unsigned int apic_id; 2257 unsigned int apic_taskpri; 2258 unsigned int apic_ldr; 2259 unsigned int apic_dfr; 2260 unsigned int apic_spiv; 2261 unsigned int apic_lvtt; 2262 unsigned int apic_lvtpc; 2263 unsigned int apic_lvt0; 2264 unsigned int apic_lvt1; 2265 unsigned int apic_lvterr; 2266 unsigned int apic_tmict; 2267 unsigned int apic_tdcr; 2268 unsigned int apic_thmr; 2269} apic_pm_state; 2270 2271static int lapic_suspend(void) 2272{ 2273 unsigned long flags; 2274 int maxlvt; 2275 2276 if (!apic_pm_state.active) 2277 return 0; 2278 2279 maxlvt = lapic_get_maxlvt(); 2280 2281 apic_pm_state.apic_id = apic_read(APIC_ID); 2282 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2283 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2284 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2285 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2286 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2287 if (maxlvt >= 4) 2288 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2289 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2290 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2291 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2292 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2293 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2294#ifdef CONFIG_X86_THERMAL_VECTOR 2295 if (maxlvt >= 5) 2296 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2297#endif 2298 2299 local_irq_save(flags); 2300 disable_local_APIC(); 2301 2302 irq_remapping_disable(); 2303 2304 local_irq_restore(flags); 2305 return 0; 2306} 2307 2308static void lapic_resume(void) 2309{ 2310 unsigned int l, h; 2311 unsigned long flags; 2312 int maxlvt; 2313 2314 if (!apic_pm_state.active) 2315 return; 2316 2317 local_irq_save(flags); 2318 2319 /* 2320 * IO-APIC and PIC have their own resume routines. 2321 * We just mask them here to make sure the interrupt 2322 * subsystem is completely quiet while we enable x2apic 2323 * and interrupt-remapping. 2324 */ 2325 mask_ioapic_entries(); 2326 legacy_pic->mask_all(); 2327 2328 if (x2apic_mode) { 2329 __x2apic_enable(); 2330 } else { 2331 /* 2332 * Make sure the APICBASE points to the right address 2333 * 2334 * FIXME! This will be wrong if we ever support suspend on 2335 * SMP! We'll need to do this as part of the CPU restore! 2336 */ 2337 if (boot_cpu_data.x86 >= 6) { 2338 rdmsr(MSR_IA32_APICBASE, l, h); 2339 l &= ~MSR_IA32_APICBASE_BASE; 2340 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2341 wrmsr(MSR_IA32_APICBASE, l, h); 2342 } 2343 } 2344 2345 maxlvt = lapic_get_maxlvt(); 2346 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2347 apic_write(APIC_ID, apic_pm_state.apic_id); 2348 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2349 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2350 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2351 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2352 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2353 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2354#if defined(CONFIG_X86_MCE_INTEL) 2355 if (maxlvt >= 5) 2356 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2357#endif 2358 if (maxlvt >= 4) 2359 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2360 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2361 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2362 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2363 apic_write(APIC_ESR, 0); 2364 apic_read(APIC_ESR); 2365 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2366 apic_write(APIC_ESR, 0); 2367 apic_read(APIC_ESR); 2368 2369 irq_remapping_reenable(x2apic_mode); 2370 2371 local_irq_restore(flags); 2372} 2373 2374/* 2375 * This device has no shutdown method - fully functioning local APICs 2376 * are needed on every CPU up until machine_halt/restart/poweroff. 2377 */ 2378 2379static struct syscore_ops lapic_syscore_ops = { 2380 .resume = lapic_resume, 2381 .suspend = lapic_suspend, 2382}; 2383 2384static void apic_pm_activate(void) 2385{ 2386 apic_pm_state.active = 1; 2387} 2388 2389static int __init init_lapic_sysfs(void) 2390{ 2391 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2392 if (cpu_has_apic) 2393 register_syscore_ops(&lapic_syscore_ops); 2394 2395 return 0; 2396} 2397 2398/* local apic needs to resume before other devices access its registers. */ 2399core_initcall(init_lapic_sysfs); 2400 2401#else /* CONFIG_PM */ 2402 2403static void apic_pm_activate(void) { } 2404 2405#endif /* CONFIG_PM */ 2406 2407#ifdef CONFIG_X86_64 2408 2409static int multi_checked; 2410static int multi; 2411 2412static int set_multi(const struct dmi_system_id *d) 2413{ 2414 if (multi) 2415 return 0; 2416 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2417 multi = 1; 2418 return 0; 2419} 2420 2421static const struct dmi_system_id multi_dmi_table[] = { 2422 { 2423 .callback = set_multi, 2424 .ident = "IBM System Summit2", 2425 .matches = { 2426 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2427 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2428 }, 2429 }, 2430 {} 2431}; 2432 2433static void dmi_check_multi(void) 2434{ 2435 if (multi_checked) 2436 return; 2437 2438 dmi_check_system(multi_dmi_table); 2439 multi_checked = 1; 2440} 2441 2442/* 2443 * apic_is_clustered_box() -- Check if we can expect good TSC 2444 * 2445 * Thus far, the major user of this is IBM's Summit2 series: 2446 * Clustered boxes may have unsynced TSC problems if they are 2447 * multi-chassis. 2448 * Use DMI to check them 2449 */ 2450int apic_is_clustered_box(void) 2451{ 2452 dmi_check_multi(); 2453 return multi; 2454} 2455#endif 2456 2457/* 2458 * APIC command line parameters 2459 */ 2460static int __init setup_disableapic(char *arg) 2461{ 2462 disable_apic = 1; 2463 setup_clear_cpu_cap(X86_FEATURE_APIC); 2464 return 0; 2465} 2466early_param("disableapic", setup_disableapic); 2467 2468/* same as disableapic, for compatibility */ 2469static int __init setup_nolapic(char *arg) 2470{ 2471 return setup_disableapic(arg); 2472} 2473early_param("nolapic", setup_nolapic); 2474 2475static int __init parse_lapic_timer_c2_ok(char *arg) 2476{ 2477 local_apic_timer_c2_ok = 1; 2478 return 0; 2479} 2480early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2481 2482static int __init parse_disable_apic_timer(char *arg) 2483{ 2484 disable_apic_timer = 1; 2485 return 0; 2486} 2487early_param("noapictimer", parse_disable_apic_timer); 2488 2489static int __init parse_nolapic_timer(char *arg) 2490{ 2491 disable_apic_timer = 1; 2492 return 0; 2493} 2494early_param("nolapic_timer", parse_nolapic_timer); 2495 2496static int __init apic_set_verbosity(char *arg) 2497{ 2498 if (!arg) { 2499#ifdef CONFIG_X86_64 2500 skip_ioapic_setup = 0; 2501 return 0; 2502#endif 2503 return -EINVAL; 2504 } 2505 2506 if (strcmp("debug", arg) == 0) 2507 apic_verbosity = APIC_DEBUG; 2508 else if (strcmp("verbose", arg) == 0) 2509 apic_verbosity = APIC_VERBOSE; 2510 else { 2511 pr_warning("APIC Verbosity level %s not recognised" 2512 " use apic=verbose or apic=debug\n", arg); 2513 return -EINVAL; 2514 } 2515 2516 return 0; 2517} 2518early_param("apic", apic_set_verbosity); 2519 2520static int __init lapic_insert_resource(void) 2521{ 2522 if (!apic_phys) 2523 return -1; 2524 2525 /* Put local APIC into the resource map. */ 2526 lapic_resource.start = apic_phys; 2527 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2528 insert_resource(&iomem_resource, &lapic_resource); 2529 2530 return 0; 2531} 2532 2533/* 2534 * need call insert after e820_reserve_resources() 2535 * that is using request_resource 2536 */ 2537late_initcall(lapic_insert_resource); 2538 2539static int __init apic_set_disabled_cpu_apicid(char *arg) 2540{ 2541 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2542 return -EINVAL; 2543 2544 return 0; 2545} 2546early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2547