1#ifndef __KVM_X86_LAPIC_H 2#define __KVM_X86_LAPIC_H 3 4#include <kvm/iodev.h> 5 6#include <linux/kvm_host.h> 7 8#define KVM_APIC_INIT 0 9#define KVM_APIC_SIPI 1 10 11struct kvm_timer { 12 struct hrtimer timer; 13 s64 period; /* unit: ns */ 14 u32 timer_mode; 15 u32 timer_mode_mask; 16 u64 tscdeadline; 17 u64 expired_tscdeadline; 18 atomic_t pending; /* accumulated triggered timers */ 19}; 20 21struct kvm_lapic { 22 unsigned long base_address; 23 struct kvm_io_device dev; 24 struct kvm_timer lapic_timer; 25 u32 divide_count; 26 struct kvm_vcpu *vcpu; 27 bool sw_enabled; 28 bool irr_pending; 29 /* Number of bits set in ISR. */ 30 s16 isr_count; 31 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ 32 int highest_isr_cache; 33 /** 34 * APIC register page. The layout matches the register layout seen by 35 * the guest 1:1, because it is accessed by the vmx microcode. 36 * Note: Only one register, the TPR, is used by the microcode. 37 */ 38 void *regs; 39 gpa_t vapic_addr; 40 struct gfn_to_hva_cache vapic_cache; 41 unsigned long pending_events; 42 unsigned int sipi_vector; 43}; 44int kvm_create_lapic(struct kvm_vcpu *vcpu); 45void kvm_free_lapic(struct kvm_vcpu *vcpu); 46 47int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); 48int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); 49int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu); 50void kvm_apic_accept_events(struct kvm_vcpu *vcpu); 51void kvm_lapic_reset(struct kvm_vcpu *vcpu); 52u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); 53void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); 54void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); 55void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value); 56u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu); 57void kvm_apic_set_version(struct kvm_vcpu *vcpu); 58 59void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr); 60void __kvm_apic_update_irr(u32 *pir, void *regs); 61void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir); 62int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, 63 unsigned long *dest_map); 64int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); 65 66bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, 67 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map); 68 69u64 kvm_get_apic_base(struct kvm_vcpu *vcpu); 70int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 71void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, 72 struct kvm_lapic_state *s); 73int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); 74 75u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu); 76void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data); 77 78void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset); 79void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector); 80 81int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); 82void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); 83void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); 84 85int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 86int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 87 88int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 89int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 90 91static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu) 92{ 93 return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE; 94} 95 96int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data); 97void kvm_lapic_init(void); 98 99static inline u32 kvm_apic_get_reg(struct kvm_lapic *apic, int reg_off) 100{ 101 return *((u32 *) (apic->regs + reg_off)); 102} 103 104extern struct static_key kvm_no_apic_vcpu; 105 106static inline bool kvm_vcpu_has_lapic(struct kvm_vcpu *vcpu) 107{ 108 if (static_key_false(&kvm_no_apic_vcpu)) 109 return vcpu->arch.apic; 110 return true; 111} 112 113extern struct static_key_deferred apic_hw_disabled; 114 115static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic) 116{ 117 if (static_key_false(&apic_hw_disabled.key)) 118 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; 119 return MSR_IA32_APICBASE_ENABLE; 120} 121 122extern struct static_key_deferred apic_sw_disabled; 123 124static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic) 125{ 126 if (static_key_false(&apic_sw_disabled.key)) 127 return apic->sw_enabled; 128 return true; 129} 130 131static inline bool kvm_apic_present(struct kvm_vcpu *vcpu) 132{ 133 return kvm_vcpu_has_lapic(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic); 134} 135 136static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu) 137{ 138 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic); 139} 140 141static inline int apic_x2apic_mode(struct kvm_lapic *apic) 142{ 143 return apic->vcpu->arch.apic_base & X2APIC_ENABLE; 144} 145 146static inline bool kvm_apic_vid_enabled(struct kvm *kvm) 147{ 148 return kvm_x86_ops->vm_has_apicv(kvm); 149} 150 151static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu) 152{ 153 return kvm_vcpu_has_lapic(vcpu) && vcpu->arch.apic->pending_events; 154} 155 156bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); 157 158void wait_lapic_expire(struct kvm_vcpu *vcpu); 159 160#endif 161