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Searched refs:hwc (Results 1 – 52 of 52) sorted by relevance

/linux-4.1.27/arch/alpha/kernel/
Dperf_event.c252 struct hw_perf_event *hwc, int idx) in alpha_perf_event_set_period() argument
254 long left = local64_read(&hwc->period_left); in alpha_perf_event_set_period()
255 long period = hwc->sample_period; in alpha_perf_event_set_period()
260 local64_set(&hwc->period_left, left); in alpha_perf_event_set_period()
261 hwc->last_period = period; in alpha_perf_event_set_period()
267 local64_set(&hwc->period_left, left); in alpha_perf_event_set_period()
268 hwc->last_period = period; in alpha_perf_event_set_period()
282 local64_set(&hwc->prev_count, (unsigned long)(-left)); in alpha_perf_event_set_period()
307 struct hw_perf_event *hwc, int idx, long ovf) in alpha_perf_event_update() argument
313 prev_raw_count = local64_read(&hwc->prev_count); in alpha_perf_event_update()
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/linux-4.1.27/arch/s390/include/asm/
Dperf_event.h64 #define OVERFLOW_REG(hwc) ((hwc)->extra_reg.config) argument
65 #define SFB_ALLOC_REG(hwc) ((hwc)->extra_reg.alloc) argument
66 #define RAWSAMPLE_REG(hwc) ((hwc)->config) argument
67 #define TEAR_REG(hwc) ((hwc)->last_tag) argument
68 #define SAMPL_RATE(hwc) ((hwc)->event_base) argument
69 #define SAMPL_FLAGS(hwc) ((hwc)->config_base) argument
70 #define SAMPL_DIAG_MODE(hwc) (SAMPL_FLAGS(hwc) & PERF_CPUM_SF_DIAG_MODE) argument
71 #define SDB_FULL_BLOCKS(hwc) (SAMPL_FLAGS(hwc) & PERF_CPUM_SF_FULL_BLOCKS) argument
/linux-4.1.27/arch/metag/kernel/perf/
Dperf_event.c190 struct hw_perf_event *hwc, int idx) in metag_pmu_event_update() argument
205 prev_raw_count = local64_read(&hwc->prev_count); in metag_pmu_event_update()
208 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in metag_pmu_event_update()
218 local64_sub(delta, &hwc->period_left); in metag_pmu_event_update()
222 struct hw_perf_event *hwc, int idx) in metag_pmu_event_set_period() argument
224 s64 left = local64_read(&hwc->period_left); in metag_pmu_event_set_period()
225 s64 period = hwc->sample_period; in metag_pmu_event_set_period()
229 if (unlikely(period != hwc->last_period)) in metag_pmu_event_set_period()
230 left += period - hwc->last_period; in metag_pmu_event_set_period()
234 local64_set(&hwc->period_left, left); in metag_pmu_event_set_period()
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/linux-4.1.27/arch/x86/kernel/cpu/
Dperf_event_amd_ibs.c73 perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *hw_period) in perf_event_set_period() argument
75 s64 left = local64_read(&hwc->period_left); in perf_event_set_period()
76 s64 period = hwc->sample_period; in perf_event_set_period()
84 local64_set(&hwc->period_left, left); in perf_event_set_period()
85 hwc->last_period = period; in perf_event_set_period()
91 local64_set(&hwc->period_left, left); in perf_event_set_period()
92 hwc->last_period = period; in perf_event_set_period()
118 struct hw_perf_event *hwc = &event->hw; in perf_event_try_update() local
130 prev_raw_count = local64_read(&hwc->prev_count); in perf_event_try_update()
131 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in perf_event_try_update()
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Dperf_event_amd_uncore.c76 struct hw_perf_event *hwc = &event->hw; in amd_uncore_read() local
85 prev = local64_read(&hwc->prev_count); in amd_uncore_read()
86 rdpmcl(hwc->event_base_rdpmc, new); in amd_uncore_read()
87 local64_set(&hwc->prev_count, new); in amd_uncore_read()
95 struct hw_perf_event *hwc = &event->hw; in amd_uncore_start() local
98 wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count)); in amd_uncore_start()
100 hwc->state = 0; in amd_uncore_start()
101 wrmsrl(hwc->config_base, (hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE)); in amd_uncore_start()
107 struct hw_perf_event *hwc = &event->hw; in amd_uncore_stop() local
109 wrmsrl(hwc->config_base, hwc->config); in amd_uncore_stop()
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Dperf_event_intel_uncore_nhmex.c241 struct hw_perf_event *hwc = &event->hw; in nhmex_uncore_msr_enable_event() local
243 if (hwc->idx >= UNCORE_PMC_IDX_FIXED) in nhmex_uncore_msr_enable_event()
244 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
246 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_uncore_msr_enable_event()
248 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
345 struct hw_perf_event *hwc = &event->hw; in nhmex_bbox_hw_config() local
346 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in nhmex_bbox_hw_config()
347 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; in nhmex_bbox_hw_config()
350 ctr = (hwc->config & NHMEX_B_PMON_CTR_MASK) >> in nhmex_bbox_hw_config()
352 ev_sel = (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK) >> in nhmex_bbox_hw_config()
[all …]
Dperf_event.c66 struct hw_perf_event *hwc = &event->hw; in x86_perf_event_update() local
69 int idx = hwc->idx; in x86_perf_event_update()
83 prev_raw_count = local64_read(&hwc->prev_count); in x86_perf_event_update()
84 rdpmcl(hwc->event_base_rdpmc, new_raw_count); in x86_perf_event_update()
86 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in x86_perf_event_update()
102 local64_sub(delta, &hwc->period_left); in x86_perf_event_update()
290 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) in set_ext_hw_attr() argument
318 hwc->config |= val; in set_ext_hw_attr()
385 struct hw_perf_event *hwc = &event->hw; in x86_setup_perfctr() local
389 hwc->sample_period = x86_pmu.max_period; in x86_setup_perfctr()
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Dperf_event_intel_uncore_snb.c70 struct hw_perf_event *hwc = &event->hw; in snb_uncore_msr_enable_event() local
72 if (hwc->idx < UNCORE_PMC_IDX_FIXED) in snb_uncore_msr_enable_event()
73 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); in snb_uncore_msr_enable_event()
75 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN); in snb_uncore_msr_enable_event()
227 struct hw_perf_event *hwc = &event->hw; in snb_uncore_imc_read_counter() local
229 return (u64)*(unsigned int *)(box->io_addr + hwc->event_base); in snb_uncore_imc_read_counter()
241 struct hw_perf_event *hwc = &event->hw; in snb_uncore_imc_event_init() local
254 if (hwc->sample_period) in snb_uncore_imc_event_init()
342 struct hw_perf_event *hwc = &event->hw; in snb_uncore_imc_event_stop() local
344 if (!(hwc->state & PERF_HES_STOPPED)) { in snb_uncore_imc_event_stop()
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Dperf_event_p4.c855 static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc) in p4_pmu_clear_cccr_ovf() argument
860 rdmsrl(hwc->config_base, v); in p4_pmu_clear_cccr_ovf()
862 wrmsrl(hwc->config_base, v & ~P4_CCCR_OVF); in p4_pmu_clear_cccr_ovf()
873 rdmsrl(hwc->event_base, v); in p4_pmu_clear_cccr_ovf()
905 struct hw_perf_event *hwc = &event->hw; in p4_pmu_disable_event() local
912 (void)wrmsrl_safe(hwc->config_base, in p4_pmu_disable_event()
913 p4_config_unpack_cccr(hwc->config) & ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED); in p4_pmu_disable_event()
951 struct hw_perf_event *hwc = &event->hw; in p4_pmu_enable_event() local
952 int thread = p4_ht_config_thread(hwc->config); in p4_pmu_enable_event()
953 u64 escr_conf = p4_config_unpack_escr(p4_clear_ht_bit(hwc->config)); in p4_pmu_enable_event()
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Dperf_event_amd_iommu.c199 struct hw_perf_event *hwc = &event->hw; in perf_iommu_event_init() local
244 hwc->config = config; in perf_iommu_event_init()
245 hwc->extra_reg.config = config1; in perf_iommu_event_init()
294 struct hw_perf_event *hwc = &event->hw; in perf_iommu_start() local
297 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) in perf_iommu_start()
300 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); in perf_iommu_start()
301 hwc->state = 0; in perf_iommu_start()
304 u64 prev_raw_count = local64_read(&hwc->prev_count); in perf_iommu_start()
320 struct hw_perf_event *hwc = &event->hw; in perf_iommu_read() local
330 prev_raw_count = local64_read(&hwc->prev_count); in perf_iommu_read()
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Dperf_event_intel_uncore.c158 struct hw_perf_event *hwc = &event->hw; in uncore_assign_hw_event() local
160 hwc->idx = idx; in uncore_assign_hw_event()
161 hwc->last_tag = ++box->tags[idx]; in uncore_assign_hw_event()
163 if (hwc->idx == UNCORE_PMC_IDX_FIXED) { in uncore_assign_hw_event()
164 hwc->event_base = uncore_fixed_ctr(box); in uncore_assign_hw_event()
165 hwc->config_base = uncore_fixed_ctl(box); in uncore_assign_hw_event()
169 hwc->config_base = uncore_event_ctl(box, hwc->idx); in uncore_assign_hw_event()
170 hwc->event_base = uncore_perf_ctr(box, hwc->idx); in uncore_assign_hw_event()
363 struct hw_perf_event *hwc; in uncore_assign_events() local
376 hwc = &box->event_list[i]->hw; in uncore_assign_events()
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Dperf_event_intel_uncore_snbep.c290 struct hw_perf_event *hwc = &event->hw; in snbep_uncore_pci_enable_event() local
292 pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); in snbep_uncore_pci_enable_event()
298 struct hw_perf_event *hwc = &event->hw; in snbep_uncore_pci_disable_event() local
300 pci_write_config_dword(pdev, hwc->config_base, hwc->config); in snbep_uncore_pci_disable_event()
306 struct hw_perf_event *hwc = &event->hw; in snbep_uncore_pci_read_counter() local
309 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count); in snbep_uncore_pci_read_counter()
310 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1); in snbep_uncore_pci_read_counter()
350 struct hw_perf_event *hwc = &event->hw; in snbep_uncore_msr_enable_event() local
351 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in snbep_uncore_msr_enable_event()
356 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); in snbep_uncore_msr_enable_event()
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Dperf_event_amd.c197 static inline unsigned int amd_get_event_code(struct hw_perf_event *hwc) in amd_get_event_code() argument
199 return ((hwc->config >> 24) & 0x0f00) | (hwc->config & 0x00ff); in amd_get_event_code()
202 static inline int amd_is_nb_event(struct hw_perf_event *hwc) in amd_is_nb_event() argument
204 return (hwc->config & 0xe0) == 0xe0; in amd_is_nb_event()
295 struct hw_perf_event *hwc = &event->hw; in __amd_get_nb_event_constraints() local
317 if (new == -1 || hwc->idx == idx) in __amd_get_nb_event_constraints()
545 struct hw_perf_event *hwc = &event->hw; in amd_get_event_constraints_f15h() local
546 unsigned int event_code = amd_get_event_code(hwc); in amd_get_event_constraints_f15h()
552 if (!(hwc->config & 0x0000F000ULL)) in amd_get_event_constraints_f15h()
554 if (!(hwc->config & 0x00000F00ULL)) in amd_get_event_constraints_f15h()
[all …]
Dperf_event_knc.c178 struct hw_perf_event *hwc = &event->hw; in knc_pmu_disable_event() local
181 val = hwc->config; in knc_pmu_disable_event()
184 (void)wrmsrl_safe(hwc->config_base + hwc->idx, val); in knc_pmu_disable_event()
189 struct hw_perf_event *hwc = &event->hw; in knc_pmu_enable_event() local
192 val = hwc->config; in knc_pmu_enable_event()
195 (void)wrmsrl_safe(hwc->config_base + hwc->idx, val); in knc_pmu_enable_event()
Dperf_event_p6.c160 struct hw_perf_event *hwc = &event->hw; in p6_pmu_disable_event() local
163 (void)wrmsrl_safe(hwc->config_base, val); in p6_pmu_disable_event()
168 struct hw_perf_event *hwc = &event->hw; in p6_pmu_enable_event() local
171 val = hwc->config; in p6_pmu_enable_event()
180 (void)wrmsrl_safe(hwc->config_base, val); in p6_pmu_enable_event()
Dperf_event_intel_rapl.c172 struct hw_perf_event *hwc = &event->hw; in rapl_event_update() local
178 prev_raw_count = local64_read(&hwc->prev_count); in rapl_event_update()
181 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in rapl_event_update()
277 struct hw_perf_event *hwc = &event->hw; in rapl_pmu_event_stop() local
283 if (!(hwc->state & PERF_HES_STOPPED)) { in rapl_pmu_event_stop()
291 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); in rapl_pmu_event_stop()
292 hwc->state |= PERF_HES_STOPPED; in rapl_pmu_event_stop()
296 if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { in rapl_pmu_event_stop()
302 hwc->state |= PERF_HES_UPTODATE; in rapl_pmu_event_stop()
311 struct hw_perf_event *hwc = &event->hw; in rapl_pmu_event_add() local
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Dperf_event_intel.c1390 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc) in intel_pmu_disable_fixed() argument
1392 int idx = hwc->idx - INTEL_PMC_IDX_FIXED; in intel_pmu_disable_fixed()
1397 rdmsrl(hwc->config_base, ctrl_val); in intel_pmu_disable_fixed()
1399 wrmsrl(hwc->config_base, ctrl_val); in intel_pmu_disable_fixed()
1409 struct hw_perf_event *hwc = &event->hw; in intel_pmu_disable_event() local
1412 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { in intel_pmu_disable_event()
1418 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx); in intel_pmu_disable_event()
1419 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx); in intel_pmu_disable_event()
1420 cpuc->intel_cp_status &= ~(1ull << hwc->idx); in intel_pmu_disable_event()
1429 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { in intel_pmu_disable_event()
[all …]
Dperf_event.h718 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, in __x86_pmu_enable_event() argument
723 if (hwc->extra_reg.reg) in __x86_pmu_enable_event()
724 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); in __x86_pmu_enable_event()
725 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); in __x86_pmu_enable_event()
738 struct hw_perf_event *hwc = &event->hw; in x86_pmu_disable_event() local
740 wrmsrl(hwc->config_base, hwc->config); in x86_pmu_disable_event()
Dperf_event_intel_ds.c690 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_enable() local
692 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; in intel_pmu_pebs_enable()
694 cpuc->pebs_enabled |= 1ULL << hwc->idx; in intel_pmu_pebs_enable()
697 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32); in intel_pmu_pebs_enable()
705 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_disable() local
707 cpuc->pebs_enabled &= ~(1ULL << hwc->idx); in intel_pmu_pebs_disable()
710 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32)); in intel_pmu_pebs_disable()
717 hwc->config |= ARCH_PERFMON_EVENTSEL_INT; in intel_pmu_pebs_disable()
Dperf_event_intel_pt.c999 struct hw_perf_event *hwc = &event->hw; in pt_event_add() local
1020 if (hwc->state == PERF_HES_STOPPED) in pt_event_add()
1023 hwc->state = PERF_HES_STOPPED; in pt_event_add()
1031 hwc->state = PERF_HES_STOPPED; in pt_event_add()
Dperf_event_intel_bts.c448 struct hw_perf_event *hwc = &event->hw; in bts_event_add() local
475 if (hwc->state & PERF_HES_STOPPED) { in bts_event_add()
/linux-4.1.27/arch/arm/kernel/
Dperf_event.c100 struct hw_perf_event *hwc = &event->hw; in armpmu_event_set_period() local
101 s64 left = local64_read(&hwc->period_left); in armpmu_event_set_period()
102 s64 period = hwc->sample_period; in armpmu_event_set_period()
107 local64_set(&hwc->period_left, left); in armpmu_event_set_period()
108 hwc->last_period = period; in armpmu_event_set_period()
114 local64_set(&hwc->period_left, left); in armpmu_event_set_period()
115 hwc->last_period = period; in armpmu_event_set_period()
128 local64_set(&hwc->prev_count, (u64)-left); in armpmu_event_set_period()
140 struct hw_perf_event *hwc = &event->hw; in armpmu_event_update() local
144 prev_raw_count = local64_read(&hwc->prev_count); in armpmu_event_update()
[all …]
Dperf_event_xscale.c167 struct hw_perf_event *hwc; in xscale1pmu_handle_irq() local
175 hwc = &event->hw; in xscale1pmu_handle_irq()
177 perf_sample_data_init(&data, 0, hwc->last_period); in xscale1pmu_handle_irq()
200 struct hw_perf_event *hwc = &event->hw; in xscale1pmu_enable_event() local
202 int idx = hwc->idx; in xscale1pmu_enable_event()
211 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) | in xscale1pmu_enable_event()
216 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) | in xscale1pmu_enable_event()
236 struct hw_perf_event *hwc = &event->hw; in xscale1pmu_disable_event() local
238 int idx = hwc->idx; in xscale1pmu_disable_event()
270 struct hw_perf_event *hwc = &event->hw; in xscale1pmu_get_event_idx() local
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Dperf_event_v7.c637 struct hw_perf_event *hwc = &event->hw; in armv7pmu_read_counter() local
638 int idx = hwc->idx; in armv7pmu_read_counter()
657 struct hw_perf_event *hwc = &event->hw; in armv7pmu_write_counter() local
658 int idx = hwc->idx; in armv7pmu_write_counter()
762 struct hw_perf_event *hwc = &event->hw; in armv7pmu_enable_event() local
765 int idx = hwc->idx; in armv7pmu_enable_event()
790 armv7_pmnc_write_evtsel(idx, hwc->config_base); in armv7pmu_enable_event()
808 struct hw_perf_event *hwc = &event->hw; in armv7pmu_disable_event() local
811 int idx = hwc->idx; in armv7pmu_disable_event()
864 struct hw_perf_event *hwc; in armv7pmu_handle_irq() local
[all …]
Dperf_event_v6.c229 struct hw_perf_event *hwc = &event->hw; in armv6pmu_read_counter() local
230 int counter = hwc->idx; in armv6pmu_read_counter()
247 struct hw_perf_event *hwc = &event->hw; in armv6pmu_write_counter() local
248 int counter = hwc->idx; in armv6pmu_write_counter()
264 struct hw_perf_event *hwc = &event->hw; in armv6pmu_enable_event() local
266 int idx = hwc->idx; in armv6pmu_enable_event()
273 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) | in armv6pmu_enable_event()
277 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) | in armv6pmu_enable_event()
321 struct hw_perf_event *hwc; in armv6pmu_handle_irq() local
334 hwc = &event->hw; in armv6pmu_handle_irq()
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/linux-4.1.27/arch/s390/kernel/
Dperf_cpum_cf.c103 static int validate_event(const struct hw_perf_event *hwc) in validate_event() argument
105 switch (hwc->config_base) { in validate_event()
111 if ((hwc->config >= 6 && hwc->config <= 31) || in validate_event()
112 (hwc->config >= 38 && hwc->config <= 63) || in validate_event()
113 (hwc->config >= 80 && hwc->config <= 127)) in validate_event()
123 static int validate_ctr_version(const struct hw_perf_event *hwc) in validate_ctr_version() argument
131 switch (hwc->config_base) { in validate_ctr_version()
141 if ((cpuhw->info.csvn == 1 && hwc->config > 159) || in validate_ctr_version()
142 (cpuhw->info.csvn == 2 && hwc->config > 175) || in validate_ctr_version()
143 (cpuhw->info.csvn > 2 && hwc->config > 255)) in validate_ctr_version()
[all …]
Dperf_cpum_sf.c308 static unsigned long sfb_max_limit(struct hw_perf_event *hwc) in sfb_max_limit() argument
310 return SAMPL_DIAG_MODE(hwc) ? CPUM_SF_MAX_SDB * CPUM_SF_SDB_DIAG_FACTOR in sfb_max_limit()
315 struct hw_perf_event *hwc) in sfb_pending_allocs() argument
318 return SFB_ALLOC_REG(hwc); in sfb_pending_allocs()
319 if (SFB_ALLOC_REG(hwc) > sfb->num_sdb) in sfb_pending_allocs()
320 return SFB_ALLOC_REG(hwc) - sfb->num_sdb; in sfb_pending_allocs()
325 struct hw_perf_event *hwc) in sfb_has_pending_allocs() argument
327 return sfb_pending_allocs(sfb, hwc) > 0; in sfb_has_pending_allocs()
330 static void sfb_account_allocs(unsigned long num, struct hw_perf_event *hwc) in sfb_account_allocs() argument
333 num = min_t(unsigned long, num, sfb_max_limit(hwc) - SFB_ALLOC_REG(hwc)); in sfb_account_allocs()
[all …]
/linux-4.1.27/arch/tile/kernel/
Dperf_event.c412 struct hw_perf_event *hwc = &event->hw; in tile_pmu_enable_event() local
414 int shift, idx = hwc->idx; in tile_pmu_enable_event()
447 cfg |= hwc->config << shift; in tile_pmu_enable_event()
461 struct hw_perf_event *hwc = &event->hw; in tile_pmu_disable_event() local
463 int idx = hwc->idx; in tile_pmu_disable_event()
504 struct hw_perf_event *hwc = &event->hw; in tile_perf_event_update() local
508 int idx = hwc->idx; in tile_perf_event_update()
519 prev_raw_count = local64_read(&hwc->prev_count); in tile_perf_event_update()
522 oldval = local64_cmpxchg(&hwc->prev_count, prev_raw_count, in tile_perf_event_update()
539 local64_sub(delta, &hwc->period_left); in tile_perf_event_update()
[all …]
/linux-4.1.27/arch/blackfin/kernel/
Dperf_event.c195 static void bfin_pfmon_disable(struct hw_perf_event *hwc, int idx) in bfin_pfmon_disable() argument
200 static void bfin_pfmon_enable(struct hw_perf_event *hwc, int idx) in bfin_pfmon_enable() argument
208 val |= (hwc->config << (PFMON1_P - PFMON0_P)); in bfin_pfmon_enable()
209 val |= (hwc->config & PFCNT0) << (PFCNT1_P - PFCNT0_P); in bfin_pfmon_enable()
213 val |= hwc->config; in bfin_pfmon_enable()
261 struct hw_perf_event *hwc, int idx) in bfin_perf_event_update() argument
280 prev_raw_count = local64_read(&hwc->prev_count); in bfin_perf_event_update()
283 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in bfin_perf_event_update()
304 struct hw_perf_event *hwc = &event->hw; in bfin_pmu_stop() local
305 int idx = hwc->idx; in bfin_pmu_stop()
[all …]
/linux-4.1.27/arch/arm64/kernel/
Dperf_event.c152 struct hw_perf_event *hwc, in armpmu_event_set_period() argument
156 s64 left = local64_read(&hwc->period_left); in armpmu_event_set_period()
157 s64 period = hwc->sample_period; in armpmu_event_set_period()
162 local64_set(&hwc->period_left, left); in armpmu_event_set_period()
163 hwc->last_period = period; in armpmu_event_set_period()
169 local64_set(&hwc->period_left, left); in armpmu_event_set_period()
170 hwc->last_period = period; in armpmu_event_set_period()
183 local64_set(&hwc->prev_count, (u64)-left); in armpmu_event_set_period()
194 struct hw_perf_event *hwc, in armpmu_event_update() argument
201 prev_raw_count = local64_read(&hwc->prev_count); in armpmu_event_update()
[all …]
/linux-4.1.27/arch/arc/kernel/
Dperf_event.c89 struct hw_perf_event *hwc, int idx) in arc_perf_event_update() argument
95 prev_raw_count = local64_read(&hwc->prev_count); in arc_perf_event_update()
97 } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in arc_perf_event_update()
104 local64_sub(delta, &hwc->period_left); in arc_perf_event_update()
142 struct hw_perf_event *hwc = &event->hw; in arc_pmu_event_init() local
151 hwc->config = arc_pmu->ev_hw_idx[event->attr.config]; in arc_pmu_event_init()
153 (int) event->attr.config, (int) hwc->config, in arc_pmu_event_init()
160 hwc->config = arc_pmu->ev_hw_idx[ret]; in arc_pmu_event_init()
190 struct hw_perf_event *hwc = &event->hw; in arc_pmu_start() local
191 int idx = hwc->idx; in arc_pmu_start()
[all …]
/linux-4.1.27/arch/mips/kernel/
Dperf_event_mipsxx.c312 struct hw_perf_event *hwc) in mipsxx_pmu_alloc_counter() argument
320 unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff; in mipsxx_pmu_alloc_counter()
376 struct hw_perf_event *hwc, in mipspmu_event_set_period() argument
379 u64 left = local64_read(&hwc->period_left); in mipspmu_event_set_period()
380 u64 period = hwc->sample_period; in mipspmu_event_set_period()
386 local64_set(&hwc->period_left, left); in mipspmu_event_set_period()
387 hwc->last_period = period; in mipspmu_event_set_period()
392 local64_set(&hwc->period_left, left); in mipspmu_event_set_period()
393 hwc->last_period = period; in mipspmu_event_set_period()
399 local64_set(&hwc->period_left, left); in mipspmu_event_set_period()
[all …]
/linux-4.1.27/arch/sh/kernel/
Dperf_event.c124 struct hw_perf_event *hwc = &event->hw; in __hw_perf_event_init() local
174 hwc->config |= config; in __hw_perf_event_init()
180 struct hw_perf_event *hwc, int idx) in sh_perf_event_update() argument
199 prev_raw_count = local64_read(&hwc->prev_count); in sh_perf_event_update()
202 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in sh_perf_event_update()
223 struct hw_perf_event *hwc = &event->hw; in sh_pmu_stop() local
224 int idx = hwc->idx; in sh_pmu_stop()
227 sh_pmu->disable(hwc, idx); in sh_pmu_stop()
241 struct hw_perf_event *hwc = &event->hw; in sh_pmu_start() local
242 int idx = hwc->idx; in sh_pmu_start()
[all …]
/linux-4.1.27/drivers/bus/
Darm-cci.c391 struct hw_perf_event *hwc = &event->hw; in pmu_event_update() local
395 prev_raw_count = local64_read(&hwc->prev_count); in pmu_event_update()
397 } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in pmu_event_update()
414 struct hw_perf_event *hwc = &event->hw; in pmu_event_set_period() local
422 local64_set(&hwc->prev_count, val); in pmu_event_set_period()
530 struct hw_perf_event *hwc = &event->hw; in cci_pmu_start() local
531 int idx = hwc->idx; in cci_pmu_start()
539 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); in cci_pmu_start()
541 hwc->state = 0; in cci_pmu_start()
552 pmu_set_event(idx, hwc->config_base); in cci_pmu_start()
[all …]
/linux-4.1.27/arch/sparc/kernel/
Dperf_event.c825 static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, in… in sparc_pmu_enable_event() argument
843 static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, i… in sparc_pmu_disable_event() argument
862 struct hw_perf_event *hwc, int idx) in sparc_perf_event_update() argument
869 prev_raw_count = local64_read(&hwc->prev_count); in sparc_perf_event_update()
872 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in sparc_perf_event_update()
880 local64_sub(delta, &hwc->period_left); in sparc_perf_event_update()
886 struct hw_perf_event *hwc, int idx) in sparc_perf_event_set_period() argument
888 s64 left = local64_read(&hwc->period_left); in sparc_perf_event_set_period()
889 s64 period = hwc->sample_period; in sparc_perf_event_set_period()
894 local64_set(&hwc->period_left, left); in sparc_perf_event_set_period()
[all …]
/linux-4.1.27/arch/arm64/include/asm/
Dpmu.h53 struct hw_perf_event *hwc);
75 struct hw_perf_event *hwc,
79 struct hw_perf_event *hwc,
/linux-4.1.27/arch/sh/kernel/cpu/sh4a/
Dperf_event.c235 static void sh4a_pmu_disable(struct hw_perf_event *hwc, int idx) in sh4a_pmu_disable() argument
244 static void sh4a_pmu_enable(struct hw_perf_event *hwc, int idx) in sh4a_pmu_enable() argument
254 tmp |= (hwc->config << 6) | CCBR_CMDS | CCBR_PPCE; in sh4a_pmu_enable()
/linux-4.1.27/arch/sh/kernel/cpu/sh4/
Dperf_event.c211 static void sh7750_pmu_disable(struct hw_perf_event *hwc, int idx) in sh7750_pmu_disable() argument
220 static void sh7750_pmu_enable(struct hw_perf_event *hwc, int idx) in sh7750_pmu_enable() argument
223 __raw_writew(hwc->config | PMCR_PMEN | PMCR_PMST, PMCR(idx)); in sh7750_pmu_enable()
/linux-4.1.27/kernel/events/
Dcore.c2934 struct hw_perf_event *hwc = &event->hw; in perf_adjust_period() local
2940 delta = (s64)(period - hwc->sample_period); in perf_adjust_period()
2943 sample_period = hwc->sample_period + delta; in perf_adjust_period()
2948 hwc->sample_period = sample_period; in perf_adjust_period()
2950 if (local64_read(&hwc->period_left) > 8*sample_period) { in perf_adjust_period()
2954 local64_set(&hwc->period_left, 0); in perf_adjust_period()
2970 struct hw_perf_event *hwc; in perf_adjust_freq_unthr_context() local
2994 hwc = &event->hw; in perf_adjust_freq_unthr_context()
2996 if (hwc->interrupts == MAX_INTERRUPTS) { in perf_adjust_freq_unthr_context()
2997 hwc->interrupts = 0; in perf_adjust_freq_unthr_context()
[all …]
/linux-4.1.27/drivers/video/fbdev/
Dau1200fb.c877 lcd->hwc.cursorctrl = 0; in au1200_setpanel()
878 lcd->hwc.cursorpos = 0; in au1200_setpanel()
879 lcd->hwc.cursorcolor0 = 0; in au1200_setpanel()
880 lcd->hwc.cursorcolor1 = 0; in au1200_setpanel()
881 lcd->hwc.cursorcolor2 = 0; in au1200_setpanel()
882 lcd->hwc.cursorcolor3 = 0; in au1200_setpanel()
926 D(lcd->hwc.cursorctrl); in au1200_setpanel()
927 D(lcd->hwc.cursorpos); in au1200_setpanel()
928 D(lcd->hwc.cursorcolor0); in au1200_setpanel()
929 D(lcd->hwc.cursorcolor1); in au1200_setpanel()
[all …]
Dau1200fb.h59 } hwc; member
345 } hwc; member
Dpxa168fb.h308 #define CFG_CSB_256x32(hwc) ((hwc) << 15) /* HWC */ argument
/linux-4.1.27/arch/powerpc/perf/
Dmpc7450-pmu.c263 static int mpc7450_compute_mmcr(u64 event[], int n_ev, unsigned int hwc[], in mpc7450_compute_mmcr() argument
318 hwc[event_index[class][i]] = pmc - 1; in mpc7450_compute_mmcr()
Dpower7-pmu.c248 unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[]) in power7_compute_mmcr() argument
300 hwc[i] = pmc; in power7_compute_mmcr()
Dpower6-pmu.c178 unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[]) in p6_compute_mmcr() argument
211 hwc[i] = pmc; in p6_compute_mmcr()
Dppc970-pmu.c260 unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[]) in p970_compute_mmcr() argument
381 hwc[i] = pmc; in p970_compute_mmcr()
Dpower4-pmu.c359 unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[]) in p4_compute_mmcr() argument
509 hwc[i] = pmc; in p4_compute_mmcr()
Dpower5-pmu.c386 unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[]) in power5_compute_mmcr() argument
531 hwc[i] = pmc; in power5_compute_mmcr()
Dpower5+-pmu.c455 unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[]) in power5p_compute_mmcr() argument
589 hwc[i] = pmc; in power5p_compute_mmcr()
Dpower8-pmu.c402 unsigned int hwc[], unsigned long mmcr[], in power8_compute_mmcr() argument
495 hwc[i] = pmc - 1; in power8_compute_mmcr()
/linux-4.1.27/arch/powerpc/include/asm/
Dperf_event_server.h35 unsigned int hwc[], unsigned long mmcr[],
/linux-4.1.27/drivers/video/fbdev/mmp/hw/
Dmmp_ctrl.h548 #define CFG_CSB_256x32(hwc) ((hwc)<<15) /* HWC */ argument