391 	struct hw_perf_event *hwc = &event->hw;  in pmu_event_update()  local
395 		prev_raw_count = local64_read(&hwc->prev_count);  in pmu_event_update()
397 	} while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,  in pmu_event_update()
414 	struct hw_perf_event *hwc = &event->hw;  in pmu_event_set_period()  local
422 	local64_set(&hwc->prev_count, val);  in pmu_event_set_period()
530 	struct hw_perf_event *hwc = &event->hw;  in cci_pmu_start()  local
531 	int idx = hwc->idx;  in cci_pmu_start()
539 		WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));  in cci_pmu_start()
541 	hwc->state = 0;  in cci_pmu_start()
552 		pmu_set_event(idx, hwc->config_base);  in cci_pmu_start()
563 	struct hw_perf_event *hwc = &event->hw;  in cci_pmu_stop()  local
564 	int idx = hwc->idx;  in cci_pmu_stop()
566 	if (hwc->state & PERF_HES_STOPPED)  in cci_pmu_stop()
580 	hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;  in cci_pmu_stop()
587 	struct hw_perf_event *hwc = &event->hw;  in cci_pmu_add()  local
603 	hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;  in cci_pmu_add()
619 	struct hw_perf_event *hwc = &event->hw;  in cci_pmu_del()  local
620 	int idx = hwc->idx;  in cci_pmu_del()
683 	struct hw_perf_event *hwc = &event->hw;  in __hw_perf_event_init()  local
699 	hwc->idx		= -1;  in __hw_perf_event_init()
700 	hwc->config_base	= 0;  in __hw_perf_event_init()
701 	hwc->config		= 0;  in __hw_perf_event_init()
702 	hwc->event_base		= 0;  in __hw_perf_event_init()
707 	hwc->config_base	    |= (unsigned long)mapping;  in __hw_perf_event_init()
714 	hwc->sample_period  = CCI_PMU_CNTR_MASK >> 1;  in __hw_perf_event_init()
715 	hwc->last_period    = hwc->sample_period;  in __hw_perf_event_init()
716 	local64_set(&hwc->period_left, hwc->sample_period);  in __hw_perf_event_init()