1/* Performance event support for sparc64. 2 * 3 * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net> 4 * 5 * This code is based almost entirely upon the x86 perf event 6 * code, which is: 7 * 8 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 9 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 10 * Copyright (C) 2009 Jaswinder Singh Rajput 11 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 12 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> 13 */ 14 15#include <linux/perf_event.h> 16#include <linux/kprobes.h> 17#include <linux/ftrace.h> 18#include <linux/kernel.h> 19#include <linux/kdebug.h> 20#include <linux/mutex.h> 21 22#include <asm/stacktrace.h> 23#include <asm/cpudata.h> 24#include <asm/uaccess.h> 25#include <linux/atomic.h> 26#include <asm/nmi.h> 27#include <asm/pcr.h> 28#include <asm/cacheflush.h> 29 30#include "kernel.h" 31#include "kstack.h" 32 33/* Two classes of sparc64 chips currently exist. All of which have 34 * 32-bit counters which can generate overflow interrupts on the 35 * transition from 0xffffffff to 0. 36 * 37 * All chips upto and including SPARC-T3 have two performance 38 * counters. The two 32-bit counters are accessed in one go using a 39 * single 64-bit register. 40 * 41 * On these older chips both counters are controlled using a single 42 * control register. The only way to stop all sampling is to clear 43 * all of the context (user, supervisor, hypervisor) sampling enable 44 * bits. But these bits apply to both counters, thus the two counters 45 * can't be enabled/disabled individually. 46 * 47 * Furthermore, the control register on these older chips have two 48 * event fields, one for each of the two counters. It's thus nearly 49 * impossible to have one counter going while keeping the other one 50 * stopped. Therefore it is possible to get overflow interrupts for 51 * counters not currently "in use" and that condition must be checked 52 * in the overflow interrupt handler. 53 * 54 * So we use a hack, in that we program inactive counters with the 55 * "sw_count0" and "sw_count1" events. These count how many times 56 * the instruction "sethi %hi(0xfc000), %g0" is executed. It's an 57 * unusual way to encode a NOP and therefore will not trigger in 58 * normal code. 59 * 60 * Starting with SPARC-T4 we have one control register per counter. 61 * And the counters are stored in individual registers. The registers 62 * for the counters are 64-bit but only a 32-bit counter is 63 * implemented. The event selections on SPARC-T4 lack any 64 * restrictions, therefore we can elide all of the complicated 65 * conflict resolution code we have for SPARC-T3 and earlier chips. 66 */ 67 68#define MAX_HWEVENTS 4 69#define MAX_PCRS 4 70#define MAX_PERIOD ((1UL << 32) - 1) 71 72#define PIC_UPPER_INDEX 0 73#define PIC_LOWER_INDEX 1 74#define PIC_NO_INDEX -1 75 76struct cpu_hw_events { 77 /* Number of events currently scheduled onto this cpu. 78 * This tells how many entries in the arrays below 79 * are valid. 80 */ 81 int n_events; 82 83 /* Number of new events added since the last hw_perf_disable(). 84 * This works because the perf event layer always adds new 85 * events inside of a perf_{disable,enable}() sequence. 86 */ 87 int n_added; 88 89 /* Array of events current scheduled on this cpu. */ 90 struct perf_event *event[MAX_HWEVENTS]; 91 92 /* Array of encoded longs, specifying the %pcr register 93 * encoding and the mask of PIC counters this even can 94 * be scheduled on. See perf_event_encode() et al. 95 */ 96 unsigned long events[MAX_HWEVENTS]; 97 98 /* The current counter index assigned to an event. When the 99 * event hasn't been programmed into the cpu yet, this will 100 * hold PIC_NO_INDEX. The event->hw.idx value tells us where 101 * we ought to schedule the event. 102 */ 103 int current_idx[MAX_HWEVENTS]; 104 105 /* Software copy of %pcr register(s) on this cpu. */ 106 u64 pcr[MAX_HWEVENTS]; 107 108 /* Enabled/disable state. */ 109 int enabled; 110 111 unsigned int group_flag; 112}; 113static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, }; 114 115/* An event map describes the characteristics of a performance 116 * counter event. In particular it gives the encoding as well as 117 * a mask telling which counters the event can be measured on. 118 * 119 * The mask is unused on SPARC-T4 and later. 120 */ 121struct perf_event_map { 122 u16 encoding; 123 u8 pic_mask; 124#define PIC_NONE 0x00 125#define PIC_UPPER 0x01 126#define PIC_LOWER 0x02 127}; 128 129/* Encode a perf_event_map entry into a long. */ 130static unsigned long perf_event_encode(const struct perf_event_map *pmap) 131{ 132 return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask; 133} 134 135static u8 perf_event_get_msk(unsigned long val) 136{ 137 return val & 0xff; 138} 139 140static u64 perf_event_get_enc(unsigned long val) 141{ 142 return val >> 16; 143} 144 145#define C(x) PERF_COUNT_HW_CACHE_##x 146 147#define CACHE_OP_UNSUPPORTED 0xfffe 148#define CACHE_OP_NONSENSE 0xffff 149 150typedef struct perf_event_map cache_map_t 151 [PERF_COUNT_HW_CACHE_MAX] 152 [PERF_COUNT_HW_CACHE_OP_MAX] 153 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 154 155struct sparc_pmu { 156 const struct perf_event_map *(*event_map)(int); 157 const cache_map_t *cache_map; 158 int max_events; 159 u32 (*read_pmc)(int); 160 void (*write_pmc)(int, u64); 161 int upper_shift; 162 int lower_shift; 163 int event_mask; 164 int user_bit; 165 int priv_bit; 166 int hv_bit; 167 int irq_bit; 168 int upper_nop; 169 int lower_nop; 170 unsigned int flags; 171#define SPARC_PMU_ALL_EXCLUDES_SAME 0x00000001 172#define SPARC_PMU_HAS_CONFLICTS 0x00000002 173 int max_hw_events; 174 int num_pcrs; 175 int num_pic_regs; 176}; 177 178static u32 sparc_default_read_pmc(int idx) 179{ 180 u64 val; 181 182 val = pcr_ops->read_pic(0); 183 if (idx == PIC_UPPER_INDEX) 184 val >>= 32; 185 186 return val & 0xffffffff; 187} 188 189static void sparc_default_write_pmc(int idx, u64 val) 190{ 191 u64 shift, mask, pic; 192 193 shift = 0; 194 if (idx == PIC_UPPER_INDEX) 195 shift = 32; 196 197 mask = ((u64) 0xffffffff) << shift; 198 val <<= shift; 199 200 pic = pcr_ops->read_pic(0); 201 pic &= ~mask; 202 pic |= val; 203 pcr_ops->write_pic(0, pic); 204} 205 206static const struct perf_event_map ultra3_perfmon_event_map[] = { 207 [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER }, 208 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER }, 209 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER }, 210 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER }, 211}; 212 213static const struct perf_event_map *ultra3_event_map(int event_id) 214{ 215 return &ultra3_perfmon_event_map[event_id]; 216} 217 218static const cache_map_t ultra3_cache_map = { 219[C(L1D)] = { 220 [C(OP_READ)] = { 221 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, }, 222 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, }, 223 }, 224 [C(OP_WRITE)] = { 225 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER }, 226 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER }, 227 }, 228 [C(OP_PREFETCH)] = { 229 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 230 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 231 }, 232}, 233[C(L1I)] = { 234 [C(OP_READ)] = { 235 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, }, 236 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, }, 237 }, 238 [ C(OP_WRITE) ] = { 239 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, 240 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, 241 }, 242 [ C(OP_PREFETCH) ] = { 243 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 244 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 245 }, 246}, 247[C(LL)] = { 248 [C(OP_READ)] = { 249 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, }, 250 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, }, 251 }, 252 [C(OP_WRITE)] = { 253 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER }, 254 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER }, 255 }, 256 [C(OP_PREFETCH)] = { 257 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 258 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 259 }, 260}, 261[C(DTLB)] = { 262 [C(OP_READ)] = { 263 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 264 [C(RESULT_MISS)] = { 0x12, PIC_UPPER, }, 265 }, 266 [ C(OP_WRITE) ] = { 267 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 268 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 269 }, 270 [ C(OP_PREFETCH) ] = { 271 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 272 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 273 }, 274}, 275[C(ITLB)] = { 276 [C(OP_READ)] = { 277 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 278 [C(RESULT_MISS)] = { 0x11, PIC_UPPER, }, 279 }, 280 [ C(OP_WRITE) ] = { 281 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 282 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 283 }, 284 [ C(OP_PREFETCH) ] = { 285 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 286 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 287 }, 288}, 289[C(BPU)] = { 290 [C(OP_READ)] = { 291 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 292 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 293 }, 294 [ C(OP_WRITE) ] = { 295 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 296 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 297 }, 298 [ C(OP_PREFETCH) ] = { 299 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 300 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 301 }, 302}, 303[C(NODE)] = { 304 [C(OP_READ)] = { 305 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 306 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 307 }, 308 [ C(OP_WRITE) ] = { 309 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 310 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 311 }, 312 [ C(OP_PREFETCH) ] = { 313 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 314 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 315 }, 316}, 317}; 318 319static const struct sparc_pmu ultra3_pmu = { 320 .event_map = ultra3_event_map, 321 .cache_map = &ultra3_cache_map, 322 .max_events = ARRAY_SIZE(ultra3_perfmon_event_map), 323 .read_pmc = sparc_default_read_pmc, 324 .write_pmc = sparc_default_write_pmc, 325 .upper_shift = 11, 326 .lower_shift = 4, 327 .event_mask = 0x3f, 328 .user_bit = PCR_UTRACE, 329 .priv_bit = PCR_STRACE, 330 .upper_nop = 0x1c, 331 .lower_nop = 0x14, 332 .flags = (SPARC_PMU_ALL_EXCLUDES_SAME | 333 SPARC_PMU_HAS_CONFLICTS), 334 .max_hw_events = 2, 335 .num_pcrs = 1, 336 .num_pic_regs = 1, 337}; 338 339/* Niagara1 is very limited. The upper PIC is hard-locked to count 340 * only instructions, so it is free running which creates all kinds of 341 * problems. Some hardware designs make one wonder if the creator 342 * even looked at how this stuff gets used by software. 343 */ 344static const struct perf_event_map niagara1_perfmon_event_map[] = { 345 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER }, 346 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER }, 347 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE }, 348 [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER }, 349}; 350 351static const struct perf_event_map *niagara1_event_map(int event_id) 352{ 353 return &niagara1_perfmon_event_map[event_id]; 354} 355 356static const cache_map_t niagara1_cache_map = { 357[C(L1D)] = { 358 [C(OP_READ)] = { 359 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 360 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, }, 361 }, 362 [C(OP_WRITE)] = { 363 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 364 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, }, 365 }, 366 [C(OP_PREFETCH)] = { 367 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 368 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 369 }, 370}, 371[C(L1I)] = { 372 [C(OP_READ)] = { 373 [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER }, 374 [C(RESULT_MISS)] = { 0x02, PIC_LOWER, }, 375 }, 376 [ C(OP_WRITE) ] = { 377 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, 378 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, 379 }, 380 [ C(OP_PREFETCH) ] = { 381 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 382 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 383 }, 384}, 385[C(LL)] = { 386 [C(OP_READ)] = { 387 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 388 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, }, 389 }, 390 [C(OP_WRITE)] = { 391 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 392 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, }, 393 }, 394 [C(OP_PREFETCH)] = { 395 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 396 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 397 }, 398}, 399[C(DTLB)] = { 400 [C(OP_READ)] = { 401 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 402 [C(RESULT_MISS)] = { 0x05, PIC_LOWER, }, 403 }, 404 [ C(OP_WRITE) ] = { 405 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 406 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 407 }, 408 [ C(OP_PREFETCH) ] = { 409 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 410 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 411 }, 412}, 413[C(ITLB)] = { 414 [C(OP_READ)] = { 415 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 416 [C(RESULT_MISS)] = { 0x04, PIC_LOWER, }, 417 }, 418 [ C(OP_WRITE) ] = { 419 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 420 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 421 }, 422 [ C(OP_PREFETCH) ] = { 423 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 424 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 425 }, 426}, 427[C(BPU)] = { 428 [C(OP_READ)] = { 429 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 430 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 431 }, 432 [ C(OP_WRITE) ] = { 433 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 434 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 435 }, 436 [ C(OP_PREFETCH) ] = { 437 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 438 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 439 }, 440}, 441[C(NODE)] = { 442 [C(OP_READ)] = { 443 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 444 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 445 }, 446 [ C(OP_WRITE) ] = { 447 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 448 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 449 }, 450 [ C(OP_PREFETCH) ] = { 451 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 452 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 453 }, 454}, 455}; 456 457static const struct sparc_pmu niagara1_pmu = { 458 .event_map = niagara1_event_map, 459 .cache_map = &niagara1_cache_map, 460 .max_events = ARRAY_SIZE(niagara1_perfmon_event_map), 461 .read_pmc = sparc_default_read_pmc, 462 .write_pmc = sparc_default_write_pmc, 463 .upper_shift = 0, 464 .lower_shift = 4, 465 .event_mask = 0x7, 466 .user_bit = PCR_UTRACE, 467 .priv_bit = PCR_STRACE, 468 .upper_nop = 0x0, 469 .lower_nop = 0x0, 470 .flags = (SPARC_PMU_ALL_EXCLUDES_SAME | 471 SPARC_PMU_HAS_CONFLICTS), 472 .max_hw_events = 2, 473 .num_pcrs = 1, 474 .num_pic_regs = 1, 475}; 476 477static const struct perf_event_map niagara2_perfmon_event_map[] = { 478 [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER }, 479 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER }, 480 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER }, 481 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER }, 482 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER }, 483 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER }, 484}; 485 486static const struct perf_event_map *niagara2_event_map(int event_id) 487{ 488 return &niagara2_perfmon_event_map[event_id]; 489} 490 491static const cache_map_t niagara2_cache_map = { 492[C(L1D)] = { 493 [C(OP_READ)] = { 494 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, }, 495 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, }, 496 }, 497 [C(OP_WRITE)] = { 498 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, }, 499 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, }, 500 }, 501 [C(OP_PREFETCH)] = { 502 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 503 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 504 }, 505}, 506[C(L1I)] = { 507 [C(OP_READ)] = { 508 [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, }, 509 [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, }, 510 }, 511 [ C(OP_WRITE) ] = { 512 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, 513 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, 514 }, 515 [ C(OP_PREFETCH) ] = { 516 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 517 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 518 }, 519}, 520[C(LL)] = { 521 [C(OP_READ)] = { 522 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, }, 523 [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, }, 524 }, 525 [C(OP_WRITE)] = { 526 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, }, 527 [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, }, 528 }, 529 [C(OP_PREFETCH)] = { 530 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 531 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 532 }, 533}, 534[C(DTLB)] = { 535 [C(OP_READ)] = { 536 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 537 [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, }, 538 }, 539 [ C(OP_WRITE) ] = { 540 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 541 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 542 }, 543 [ C(OP_PREFETCH) ] = { 544 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 545 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 546 }, 547}, 548[C(ITLB)] = { 549 [C(OP_READ)] = { 550 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 551 [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, }, 552 }, 553 [ C(OP_WRITE) ] = { 554 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 555 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 556 }, 557 [ C(OP_PREFETCH) ] = { 558 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 559 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 560 }, 561}, 562[C(BPU)] = { 563 [C(OP_READ)] = { 564 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 565 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 566 }, 567 [ C(OP_WRITE) ] = { 568 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 569 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 570 }, 571 [ C(OP_PREFETCH) ] = { 572 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 573 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 574 }, 575}, 576[C(NODE)] = { 577 [C(OP_READ)] = { 578 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 579 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 580 }, 581 [ C(OP_WRITE) ] = { 582 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 583 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 584 }, 585 [ C(OP_PREFETCH) ] = { 586 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 587 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 588 }, 589}, 590}; 591 592static const struct sparc_pmu niagara2_pmu = { 593 .event_map = niagara2_event_map, 594 .cache_map = &niagara2_cache_map, 595 .max_events = ARRAY_SIZE(niagara2_perfmon_event_map), 596 .read_pmc = sparc_default_read_pmc, 597 .write_pmc = sparc_default_write_pmc, 598 .upper_shift = 19, 599 .lower_shift = 6, 600 .event_mask = 0xfff, 601 .user_bit = PCR_UTRACE, 602 .priv_bit = PCR_STRACE, 603 .hv_bit = PCR_N2_HTRACE, 604 .irq_bit = 0x30, 605 .upper_nop = 0x220, 606 .lower_nop = 0x220, 607 .flags = (SPARC_PMU_ALL_EXCLUDES_SAME | 608 SPARC_PMU_HAS_CONFLICTS), 609 .max_hw_events = 2, 610 .num_pcrs = 1, 611 .num_pic_regs = 1, 612}; 613 614static const struct perf_event_map niagara4_perfmon_event_map[] = { 615 [PERF_COUNT_HW_CPU_CYCLES] = { (26 << 6) }, 616 [PERF_COUNT_HW_INSTRUCTIONS] = { (3 << 6) | 0x3f }, 617 [PERF_COUNT_HW_CACHE_REFERENCES] = { (3 << 6) | 0x04 }, 618 [PERF_COUNT_HW_CACHE_MISSES] = { (16 << 6) | 0x07 }, 619 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { (4 << 6) | 0x01 }, 620 [PERF_COUNT_HW_BRANCH_MISSES] = { (25 << 6) | 0x0f }, 621}; 622 623static const struct perf_event_map *niagara4_event_map(int event_id) 624{ 625 return &niagara4_perfmon_event_map[event_id]; 626} 627 628static const cache_map_t niagara4_cache_map = { 629[C(L1D)] = { 630 [C(OP_READ)] = { 631 [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 }, 632 [C(RESULT_MISS)] = { (16 << 6) | 0x07 }, 633 }, 634 [C(OP_WRITE)] = { 635 [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 }, 636 [C(RESULT_MISS)] = { (16 << 6) | 0x07 }, 637 }, 638 [C(OP_PREFETCH)] = { 639 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 640 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 641 }, 642}, 643[C(L1I)] = { 644 [C(OP_READ)] = { 645 [C(RESULT_ACCESS)] = { (3 << 6) | 0x3f }, 646 [C(RESULT_MISS)] = { (11 << 6) | 0x03 }, 647 }, 648 [ C(OP_WRITE) ] = { 649 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, 650 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, 651 }, 652 [ C(OP_PREFETCH) ] = { 653 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 654 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 655 }, 656}, 657[C(LL)] = { 658 [C(OP_READ)] = { 659 [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 }, 660 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 661 }, 662 [C(OP_WRITE)] = { 663 [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 }, 664 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 665 }, 666 [C(OP_PREFETCH)] = { 667 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 668 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 669 }, 670}, 671[C(DTLB)] = { 672 [C(OP_READ)] = { 673 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 674 [C(RESULT_MISS)] = { (17 << 6) | 0x3f }, 675 }, 676 [ C(OP_WRITE) ] = { 677 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 678 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 679 }, 680 [ C(OP_PREFETCH) ] = { 681 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 682 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 683 }, 684}, 685[C(ITLB)] = { 686 [C(OP_READ)] = { 687 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 688 [C(RESULT_MISS)] = { (6 << 6) | 0x3f }, 689 }, 690 [ C(OP_WRITE) ] = { 691 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 692 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 693 }, 694 [ C(OP_PREFETCH) ] = { 695 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 696 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 697 }, 698}, 699[C(BPU)] = { 700 [C(OP_READ)] = { 701 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 702 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 703 }, 704 [ C(OP_WRITE) ] = { 705 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 706 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 707 }, 708 [ C(OP_PREFETCH) ] = { 709 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 710 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 711 }, 712}, 713[C(NODE)] = { 714 [C(OP_READ)] = { 715 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 716 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 717 }, 718 [ C(OP_WRITE) ] = { 719 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 720 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 721 }, 722 [ C(OP_PREFETCH) ] = { 723 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 724 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 725 }, 726}, 727}; 728 729static u32 sparc_vt_read_pmc(int idx) 730{ 731 u64 val = pcr_ops->read_pic(idx); 732 733 return val & 0xffffffff; 734} 735 736static void sparc_vt_write_pmc(int idx, u64 val) 737{ 738 u64 pcr; 739 740 pcr = pcr_ops->read_pcr(idx); 741 /* ensure ov and ntc are reset */ 742 pcr &= ~(PCR_N4_OV | PCR_N4_NTC); 743 744 pcr_ops->write_pic(idx, val & 0xffffffff); 745 746 pcr_ops->write_pcr(idx, pcr); 747} 748 749static const struct sparc_pmu niagara4_pmu = { 750 .event_map = niagara4_event_map, 751 .cache_map = &niagara4_cache_map, 752 .max_events = ARRAY_SIZE(niagara4_perfmon_event_map), 753 .read_pmc = sparc_vt_read_pmc, 754 .write_pmc = sparc_vt_write_pmc, 755 .upper_shift = 5, 756 .lower_shift = 5, 757 .event_mask = 0x7ff, 758 .user_bit = PCR_N4_UTRACE, 759 .priv_bit = PCR_N4_STRACE, 760 761 /* We explicitly don't support hypervisor tracing. The T4 762 * generates the overflow event for precise events via a trap 763 * which will not be generated (ie. it's completely lost) if 764 * we happen to be in the hypervisor when the event triggers. 765 * Essentially, the overflow event reporting is completely 766 * unusable when you have hypervisor mode tracing enabled. 767 */ 768 .hv_bit = 0, 769 770 .irq_bit = PCR_N4_TOE, 771 .upper_nop = 0, 772 .lower_nop = 0, 773 .flags = 0, 774 .max_hw_events = 4, 775 .num_pcrs = 4, 776 .num_pic_regs = 4, 777}; 778 779static const struct sparc_pmu sparc_m7_pmu = { 780 .event_map = niagara4_event_map, 781 .cache_map = &niagara4_cache_map, 782 .max_events = ARRAY_SIZE(niagara4_perfmon_event_map), 783 .read_pmc = sparc_vt_read_pmc, 784 .write_pmc = sparc_vt_write_pmc, 785 .upper_shift = 5, 786 .lower_shift = 5, 787 .event_mask = 0x7ff, 788 .user_bit = PCR_N4_UTRACE, 789 .priv_bit = PCR_N4_STRACE, 790 791 /* We explicitly don't support hypervisor tracing. */ 792 .hv_bit = 0, 793 794 .irq_bit = PCR_N4_TOE, 795 .upper_nop = 0, 796 .lower_nop = 0, 797 .flags = 0, 798 .max_hw_events = 4, 799 .num_pcrs = 4, 800 .num_pic_regs = 4, 801}; 802static const struct sparc_pmu *sparc_pmu __read_mostly; 803 804static u64 event_encoding(u64 event_id, int idx) 805{ 806 if (idx == PIC_UPPER_INDEX) 807 event_id <<= sparc_pmu->upper_shift; 808 else 809 event_id <<= sparc_pmu->lower_shift; 810 return event_id; 811} 812 813static u64 mask_for_index(int idx) 814{ 815 return event_encoding(sparc_pmu->event_mask, idx); 816} 817 818static u64 nop_for_index(int idx) 819{ 820 return event_encoding(idx == PIC_UPPER_INDEX ? 821 sparc_pmu->upper_nop : 822 sparc_pmu->lower_nop, idx); 823} 824 825static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx) 826{ 827 u64 enc, val, mask = mask_for_index(idx); 828 int pcr_index = 0; 829 830 if (sparc_pmu->num_pcrs > 1) 831 pcr_index = idx; 832 833 enc = perf_event_get_enc(cpuc->events[idx]); 834 835 val = cpuc->pcr[pcr_index]; 836 val &= ~mask; 837 val |= event_encoding(enc, idx); 838 cpuc->pcr[pcr_index] = val; 839 840 pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]); 841} 842 843static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx) 844{ 845 u64 mask = mask_for_index(idx); 846 u64 nop = nop_for_index(idx); 847 int pcr_index = 0; 848 u64 val; 849 850 if (sparc_pmu->num_pcrs > 1) 851 pcr_index = idx; 852 853 val = cpuc->pcr[pcr_index]; 854 val &= ~mask; 855 val |= nop; 856 cpuc->pcr[pcr_index] = val; 857 858 pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]); 859} 860 861static u64 sparc_perf_event_update(struct perf_event *event, 862 struct hw_perf_event *hwc, int idx) 863{ 864 int shift = 64 - 32; 865 u64 prev_raw_count, new_raw_count; 866 s64 delta; 867 868again: 869 prev_raw_count = local64_read(&hwc->prev_count); 870 new_raw_count = sparc_pmu->read_pmc(idx); 871 872 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, 873 new_raw_count) != prev_raw_count) 874 goto again; 875 876 delta = (new_raw_count << shift) - (prev_raw_count << shift); 877 delta >>= shift; 878 879 local64_add(delta, &event->count); 880 local64_sub(delta, &hwc->period_left); 881 882 return new_raw_count; 883} 884 885static int sparc_perf_event_set_period(struct perf_event *event, 886 struct hw_perf_event *hwc, int idx) 887{ 888 s64 left = local64_read(&hwc->period_left); 889 s64 period = hwc->sample_period; 890 int ret = 0; 891 892 if (unlikely(left <= -period)) { 893 left = period; 894 local64_set(&hwc->period_left, left); 895 hwc->last_period = period; 896 ret = 1; 897 } 898 899 if (unlikely(left <= 0)) { 900 left += period; 901 local64_set(&hwc->period_left, left); 902 hwc->last_period = period; 903 ret = 1; 904 } 905 if (left > MAX_PERIOD) 906 left = MAX_PERIOD; 907 908 local64_set(&hwc->prev_count, (u64)-left); 909 910 sparc_pmu->write_pmc(idx, (u64)(-left) & 0xffffffff); 911 912 perf_event_update_userpage(event); 913 914 return ret; 915} 916 917static void read_in_all_counters(struct cpu_hw_events *cpuc) 918{ 919 int i; 920 921 for (i = 0; i < cpuc->n_events; i++) { 922 struct perf_event *cp = cpuc->event[i]; 923 924 if (cpuc->current_idx[i] != PIC_NO_INDEX && 925 cpuc->current_idx[i] != cp->hw.idx) { 926 sparc_perf_event_update(cp, &cp->hw, 927 cpuc->current_idx[i]); 928 cpuc->current_idx[i] = PIC_NO_INDEX; 929 } 930 } 931} 932 933/* On this PMU all PICs are programmed using a single PCR. Calculate 934 * the combined control register value. 935 * 936 * For such chips we require that all of the events have the same 937 * configuration, so just fetch the settings from the first entry. 938 */ 939static void calculate_single_pcr(struct cpu_hw_events *cpuc) 940{ 941 int i; 942 943 if (!cpuc->n_added) 944 goto out; 945 946 /* Assign to counters all unassigned events. */ 947 for (i = 0; i < cpuc->n_events; i++) { 948 struct perf_event *cp = cpuc->event[i]; 949 struct hw_perf_event *hwc = &cp->hw; 950 int idx = hwc->idx; 951 u64 enc; 952 953 if (cpuc->current_idx[i] != PIC_NO_INDEX) 954 continue; 955 956 sparc_perf_event_set_period(cp, hwc, idx); 957 cpuc->current_idx[i] = idx; 958 959 enc = perf_event_get_enc(cpuc->events[i]); 960 cpuc->pcr[0] &= ~mask_for_index(idx); 961 if (hwc->state & PERF_HES_STOPPED) 962 cpuc->pcr[0] |= nop_for_index(idx); 963 else 964 cpuc->pcr[0] |= event_encoding(enc, idx); 965 } 966out: 967 cpuc->pcr[0] |= cpuc->event[0]->hw.config_base; 968} 969 970static void sparc_pmu_start(struct perf_event *event, int flags); 971 972/* On this PMU each PIC has it's own PCR control register. */ 973static void calculate_multiple_pcrs(struct cpu_hw_events *cpuc) 974{ 975 int i; 976 977 if (!cpuc->n_added) 978 goto out; 979 980 for (i = 0; i < cpuc->n_events; i++) { 981 struct perf_event *cp = cpuc->event[i]; 982 struct hw_perf_event *hwc = &cp->hw; 983 int idx = hwc->idx; 984 985 if (cpuc->current_idx[i] != PIC_NO_INDEX) 986 continue; 987 988 cpuc->current_idx[i] = idx; 989 990 sparc_pmu_start(cp, PERF_EF_RELOAD); 991 } 992out: 993 for (i = 0; i < cpuc->n_events; i++) { 994 struct perf_event *cp = cpuc->event[i]; 995 int idx = cp->hw.idx; 996 997 cpuc->pcr[idx] |= cp->hw.config_base; 998 } 999} 1000 1001/* If performance event entries have been added, move existing events 1002 * around (if necessary) and then assign new entries to counters. 1003 */ 1004static void update_pcrs_for_enable(struct cpu_hw_events *cpuc) 1005{ 1006 if (cpuc->n_added) 1007 read_in_all_counters(cpuc); 1008 1009 if (sparc_pmu->num_pcrs == 1) { 1010 calculate_single_pcr(cpuc); 1011 } else { 1012 calculate_multiple_pcrs(cpuc); 1013 } 1014} 1015 1016static void sparc_pmu_enable(struct pmu *pmu) 1017{ 1018 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1019 int i; 1020 1021 if (cpuc->enabled) 1022 return; 1023 1024 cpuc->enabled = 1; 1025 barrier(); 1026 1027 if (cpuc->n_events) 1028 update_pcrs_for_enable(cpuc); 1029 1030 for (i = 0; i < sparc_pmu->num_pcrs; i++) 1031 pcr_ops->write_pcr(i, cpuc->pcr[i]); 1032} 1033 1034static void sparc_pmu_disable(struct pmu *pmu) 1035{ 1036 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1037 int i; 1038 1039 if (!cpuc->enabled) 1040 return; 1041 1042 cpuc->enabled = 0; 1043 cpuc->n_added = 0; 1044 1045 for (i = 0; i < sparc_pmu->num_pcrs; i++) { 1046 u64 val = cpuc->pcr[i]; 1047 1048 val &= ~(sparc_pmu->user_bit | sparc_pmu->priv_bit | 1049 sparc_pmu->hv_bit | sparc_pmu->irq_bit); 1050 cpuc->pcr[i] = val; 1051 pcr_ops->write_pcr(i, cpuc->pcr[i]); 1052 } 1053} 1054 1055static int active_event_index(struct cpu_hw_events *cpuc, 1056 struct perf_event *event) 1057{ 1058 int i; 1059 1060 for (i = 0; i < cpuc->n_events; i++) { 1061 if (cpuc->event[i] == event) 1062 break; 1063 } 1064 BUG_ON(i == cpuc->n_events); 1065 return cpuc->current_idx[i]; 1066} 1067 1068static void sparc_pmu_start(struct perf_event *event, int flags) 1069{ 1070 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1071 int idx = active_event_index(cpuc, event); 1072 1073 if (flags & PERF_EF_RELOAD) { 1074 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1075 sparc_perf_event_set_period(event, &event->hw, idx); 1076 } 1077 1078 event->hw.state = 0; 1079 1080 sparc_pmu_enable_event(cpuc, &event->hw, idx); 1081} 1082 1083static void sparc_pmu_stop(struct perf_event *event, int flags) 1084{ 1085 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1086 int idx = active_event_index(cpuc, event); 1087 1088 if (!(event->hw.state & PERF_HES_STOPPED)) { 1089 sparc_pmu_disable_event(cpuc, &event->hw, idx); 1090 event->hw.state |= PERF_HES_STOPPED; 1091 } 1092 1093 if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) { 1094 sparc_perf_event_update(event, &event->hw, idx); 1095 event->hw.state |= PERF_HES_UPTODATE; 1096 } 1097} 1098 1099static void sparc_pmu_del(struct perf_event *event, int _flags) 1100{ 1101 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1102 unsigned long flags; 1103 int i; 1104 1105 local_irq_save(flags); 1106 1107 for (i = 0; i < cpuc->n_events; i++) { 1108 if (event == cpuc->event[i]) { 1109 /* Absorb the final count and turn off the 1110 * event. 1111 */ 1112 sparc_pmu_stop(event, PERF_EF_UPDATE); 1113 1114 /* Shift remaining entries down into 1115 * the existing slot. 1116 */ 1117 while (++i < cpuc->n_events) { 1118 cpuc->event[i - 1] = cpuc->event[i]; 1119 cpuc->events[i - 1] = cpuc->events[i]; 1120 cpuc->current_idx[i - 1] = 1121 cpuc->current_idx[i]; 1122 } 1123 1124 perf_event_update_userpage(event); 1125 1126 cpuc->n_events--; 1127 break; 1128 } 1129 } 1130 1131 local_irq_restore(flags); 1132} 1133 1134static void sparc_pmu_read(struct perf_event *event) 1135{ 1136 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1137 int idx = active_event_index(cpuc, event); 1138 struct hw_perf_event *hwc = &event->hw; 1139 1140 sparc_perf_event_update(event, hwc, idx); 1141} 1142 1143static atomic_t active_events = ATOMIC_INIT(0); 1144static DEFINE_MUTEX(pmc_grab_mutex); 1145 1146static void perf_stop_nmi_watchdog(void *unused) 1147{ 1148 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1149 int i; 1150 1151 stop_nmi_watchdog(NULL); 1152 for (i = 0; i < sparc_pmu->num_pcrs; i++) 1153 cpuc->pcr[i] = pcr_ops->read_pcr(i); 1154} 1155 1156static void perf_event_grab_pmc(void) 1157{ 1158 if (atomic_inc_not_zero(&active_events)) 1159 return; 1160 1161 mutex_lock(&pmc_grab_mutex); 1162 if (atomic_read(&active_events) == 0) { 1163 if (atomic_read(&nmi_active) > 0) { 1164 on_each_cpu(perf_stop_nmi_watchdog, NULL, 1); 1165 BUG_ON(atomic_read(&nmi_active) != 0); 1166 } 1167 atomic_inc(&active_events); 1168 } 1169 mutex_unlock(&pmc_grab_mutex); 1170} 1171 1172static void perf_event_release_pmc(void) 1173{ 1174 if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) { 1175 if (atomic_read(&nmi_active) == 0) 1176 on_each_cpu(start_nmi_watchdog, NULL, 1); 1177 mutex_unlock(&pmc_grab_mutex); 1178 } 1179} 1180 1181static const struct perf_event_map *sparc_map_cache_event(u64 config) 1182{ 1183 unsigned int cache_type, cache_op, cache_result; 1184 const struct perf_event_map *pmap; 1185 1186 if (!sparc_pmu->cache_map) 1187 return ERR_PTR(-ENOENT); 1188 1189 cache_type = (config >> 0) & 0xff; 1190 if (cache_type >= PERF_COUNT_HW_CACHE_MAX) 1191 return ERR_PTR(-EINVAL); 1192 1193 cache_op = (config >> 8) & 0xff; 1194 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) 1195 return ERR_PTR(-EINVAL); 1196 1197 cache_result = (config >> 16) & 0xff; 1198 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 1199 return ERR_PTR(-EINVAL); 1200 1201 pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]); 1202 1203 if (pmap->encoding == CACHE_OP_UNSUPPORTED) 1204 return ERR_PTR(-ENOENT); 1205 1206 if (pmap->encoding == CACHE_OP_NONSENSE) 1207 return ERR_PTR(-EINVAL); 1208 1209 return pmap; 1210} 1211 1212static void hw_perf_event_destroy(struct perf_event *event) 1213{ 1214 perf_event_release_pmc(); 1215} 1216 1217/* Make sure all events can be scheduled into the hardware at 1218 * the same time. This is simplified by the fact that we only 1219 * need to support 2 simultaneous HW events. 1220 * 1221 * As a side effect, the evts[]->hw.idx values will be assigned 1222 * on success. These are pending indexes. When the events are 1223 * actually programmed into the chip, these values will propagate 1224 * to the per-cpu cpuc->current_idx[] slots, see the code in 1225 * maybe_change_configuration() for details. 1226 */ 1227static int sparc_check_constraints(struct perf_event **evts, 1228 unsigned long *events, int n_ev) 1229{ 1230 u8 msk0 = 0, msk1 = 0; 1231 int idx0 = 0; 1232 1233 /* This case is possible when we are invoked from 1234 * hw_perf_group_sched_in(). 1235 */ 1236 if (!n_ev) 1237 return 0; 1238 1239 if (n_ev > sparc_pmu->max_hw_events) 1240 return -1; 1241 1242 if (!(sparc_pmu->flags & SPARC_PMU_HAS_CONFLICTS)) { 1243 int i; 1244 1245 for (i = 0; i < n_ev; i++) 1246 evts[i]->hw.idx = i; 1247 return 0; 1248 } 1249 1250 msk0 = perf_event_get_msk(events[0]); 1251 if (n_ev == 1) { 1252 if (msk0 & PIC_LOWER) 1253 idx0 = 1; 1254 goto success; 1255 } 1256 BUG_ON(n_ev != 2); 1257 msk1 = perf_event_get_msk(events[1]); 1258 1259 /* If both events can go on any counter, OK. */ 1260 if (msk0 == (PIC_UPPER | PIC_LOWER) && 1261 msk1 == (PIC_UPPER | PIC_LOWER)) 1262 goto success; 1263 1264 /* If one event is limited to a specific counter, 1265 * and the other can go on both, OK. 1266 */ 1267 if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) && 1268 msk1 == (PIC_UPPER | PIC_LOWER)) { 1269 if (msk0 & PIC_LOWER) 1270 idx0 = 1; 1271 goto success; 1272 } 1273 1274 if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) && 1275 msk0 == (PIC_UPPER | PIC_LOWER)) { 1276 if (msk1 & PIC_UPPER) 1277 idx0 = 1; 1278 goto success; 1279 } 1280 1281 /* If the events are fixed to different counters, OK. */ 1282 if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) || 1283 (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) { 1284 if (msk0 & PIC_LOWER) 1285 idx0 = 1; 1286 goto success; 1287 } 1288 1289 /* Otherwise, there is a conflict. */ 1290 return -1; 1291 1292success: 1293 evts[0]->hw.idx = idx0; 1294 if (n_ev == 2) 1295 evts[1]->hw.idx = idx0 ^ 1; 1296 return 0; 1297} 1298 1299static int check_excludes(struct perf_event **evts, int n_prev, int n_new) 1300{ 1301 int eu = 0, ek = 0, eh = 0; 1302 struct perf_event *event; 1303 int i, n, first; 1304 1305 if (!(sparc_pmu->flags & SPARC_PMU_ALL_EXCLUDES_SAME)) 1306 return 0; 1307 1308 n = n_prev + n_new; 1309 if (n <= 1) 1310 return 0; 1311 1312 first = 1; 1313 for (i = 0; i < n; i++) { 1314 event = evts[i]; 1315 if (first) { 1316 eu = event->attr.exclude_user; 1317 ek = event->attr.exclude_kernel; 1318 eh = event->attr.exclude_hv; 1319 first = 0; 1320 } else if (event->attr.exclude_user != eu || 1321 event->attr.exclude_kernel != ek || 1322 event->attr.exclude_hv != eh) { 1323 return -EAGAIN; 1324 } 1325 } 1326 1327 return 0; 1328} 1329 1330static int collect_events(struct perf_event *group, int max_count, 1331 struct perf_event *evts[], unsigned long *events, 1332 int *current_idx) 1333{ 1334 struct perf_event *event; 1335 int n = 0; 1336 1337 if (!is_software_event(group)) { 1338 if (n >= max_count) 1339 return -1; 1340 evts[n] = group; 1341 events[n] = group->hw.event_base; 1342 current_idx[n++] = PIC_NO_INDEX; 1343 } 1344 list_for_each_entry(event, &group->sibling_list, group_entry) { 1345 if (!is_software_event(event) && 1346 event->state != PERF_EVENT_STATE_OFF) { 1347 if (n >= max_count) 1348 return -1; 1349 evts[n] = event; 1350 events[n] = event->hw.event_base; 1351 current_idx[n++] = PIC_NO_INDEX; 1352 } 1353 } 1354 return n; 1355} 1356 1357static int sparc_pmu_add(struct perf_event *event, int ef_flags) 1358{ 1359 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1360 int n0, ret = -EAGAIN; 1361 unsigned long flags; 1362 1363 local_irq_save(flags); 1364 1365 n0 = cpuc->n_events; 1366 if (n0 >= sparc_pmu->max_hw_events) 1367 goto out; 1368 1369 cpuc->event[n0] = event; 1370 cpuc->events[n0] = event->hw.event_base; 1371 cpuc->current_idx[n0] = PIC_NO_INDEX; 1372 1373 event->hw.state = PERF_HES_UPTODATE; 1374 if (!(ef_flags & PERF_EF_START)) 1375 event->hw.state |= PERF_HES_STOPPED; 1376 1377 /* 1378 * If group events scheduling transaction was started, 1379 * skip the schedulability test here, it will be performed 1380 * at commit time(->commit_txn) as a whole 1381 */ 1382 if (cpuc->group_flag & PERF_EVENT_TXN) 1383 goto nocheck; 1384 1385 if (check_excludes(cpuc->event, n0, 1)) 1386 goto out; 1387 if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1)) 1388 goto out; 1389 1390nocheck: 1391 cpuc->n_events++; 1392 cpuc->n_added++; 1393 1394 ret = 0; 1395out: 1396 local_irq_restore(flags); 1397 return ret; 1398} 1399 1400static int sparc_pmu_event_init(struct perf_event *event) 1401{ 1402 struct perf_event_attr *attr = &event->attr; 1403 struct perf_event *evts[MAX_HWEVENTS]; 1404 struct hw_perf_event *hwc = &event->hw; 1405 unsigned long events[MAX_HWEVENTS]; 1406 int current_idx_dmy[MAX_HWEVENTS]; 1407 const struct perf_event_map *pmap; 1408 int n; 1409 1410 if (atomic_read(&nmi_active) < 0) 1411 return -ENODEV; 1412 1413 /* does not support taken branch sampling */ 1414 if (has_branch_stack(event)) 1415 return -EOPNOTSUPP; 1416 1417 switch (attr->type) { 1418 case PERF_TYPE_HARDWARE: 1419 if (attr->config >= sparc_pmu->max_events) 1420 return -EINVAL; 1421 pmap = sparc_pmu->event_map(attr->config); 1422 break; 1423 1424 case PERF_TYPE_HW_CACHE: 1425 pmap = sparc_map_cache_event(attr->config); 1426 if (IS_ERR(pmap)) 1427 return PTR_ERR(pmap); 1428 break; 1429 1430 case PERF_TYPE_RAW: 1431 pmap = NULL; 1432 break; 1433 1434 default: 1435 return -ENOENT; 1436 1437 } 1438 1439 if (pmap) { 1440 hwc->event_base = perf_event_encode(pmap); 1441 } else { 1442 /* 1443 * User gives us "(encoding << 16) | pic_mask" for 1444 * PERF_TYPE_RAW events. 1445 */ 1446 hwc->event_base = attr->config; 1447 } 1448 1449 /* We save the enable bits in the config_base. */ 1450 hwc->config_base = sparc_pmu->irq_bit; 1451 if (!attr->exclude_user) 1452 hwc->config_base |= sparc_pmu->user_bit; 1453 if (!attr->exclude_kernel) 1454 hwc->config_base |= sparc_pmu->priv_bit; 1455 if (!attr->exclude_hv) 1456 hwc->config_base |= sparc_pmu->hv_bit; 1457 1458 n = 0; 1459 if (event->group_leader != event) { 1460 n = collect_events(event->group_leader, 1461 sparc_pmu->max_hw_events - 1, 1462 evts, events, current_idx_dmy); 1463 if (n < 0) 1464 return -EINVAL; 1465 } 1466 events[n] = hwc->event_base; 1467 evts[n] = event; 1468 1469 if (check_excludes(evts, n, 1)) 1470 return -EINVAL; 1471 1472 if (sparc_check_constraints(evts, events, n + 1)) 1473 return -EINVAL; 1474 1475 hwc->idx = PIC_NO_INDEX; 1476 1477 /* Try to do all error checking before this point, as unwinding 1478 * state after grabbing the PMC is difficult. 1479 */ 1480 perf_event_grab_pmc(); 1481 event->destroy = hw_perf_event_destroy; 1482 1483 if (!hwc->sample_period) { 1484 hwc->sample_period = MAX_PERIOD; 1485 hwc->last_period = hwc->sample_period; 1486 local64_set(&hwc->period_left, hwc->sample_period); 1487 } 1488 1489 return 0; 1490} 1491 1492/* 1493 * Start group events scheduling transaction 1494 * Set the flag to make pmu::enable() not perform the 1495 * schedulability test, it will be performed at commit time 1496 */ 1497static void sparc_pmu_start_txn(struct pmu *pmu) 1498{ 1499 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1500 1501 perf_pmu_disable(pmu); 1502 cpuhw->group_flag |= PERF_EVENT_TXN; 1503} 1504 1505/* 1506 * Stop group events scheduling transaction 1507 * Clear the flag and pmu::enable() will perform the 1508 * schedulability test. 1509 */ 1510static void sparc_pmu_cancel_txn(struct pmu *pmu) 1511{ 1512 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1513 1514 cpuhw->group_flag &= ~PERF_EVENT_TXN; 1515 perf_pmu_enable(pmu); 1516} 1517 1518/* 1519 * Commit group events scheduling transaction 1520 * Perform the group schedulability test as a whole 1521 * Return 0 if success 1522 */ 1523static int sparc_pmu_commit_txn(struct pmu *pmu) 1524{ 1525 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1526 int n; 1527 1528 if (!sparc_pmu) 1529 return -EINVAL; 1530 1531 cpuc = this_cpu_ptr(&cpu_hw_events); 1532 n = cpuc->n_events; 1533 if (check_excludes(cpuc->event, 0, n)) 1534 return -EINVAL; 1535 if (sparc_check_constraints(cpuc->event, cpuc->events, n)) 1536 return -EAGAIN; 1537 1538 cpuc->group_flag &= ~PERF_EVENT_TXN; 1539 perf_pmu_enable(pmu); 1540 return 0; 1541} 1542 1543static struct pmu pmu = { 1544 .pmu_enable = sparc_pmu_enable, 1545 .pmu_disable = sparc_pmu_disable, 1546 .event_init = sparc_pmu_event_init, 1547 .add = sparc_pmu_add, 1548 .del = sparc_pmu_del, 1549 .start = sparc_pmu_start, 1550 .stop = sparc_pmu_stop, 1551 .read = sparc_pmu_read, 1552 .start_txn = sparc_pmu_start_txn, 1553 .cancel_txn = sparc_pmu_cancel_txn, 1554 .commit_txn = sparc_pmu_commit_txn, 1555}; 1556 1557void perf_event_print_debug(void) 1558{ 1559 unsigned long flags; 1560 int cpu, i; 1561 1562 if (!sparc_pmu) 1563 return; 1564 1565 local_irq_save(flags); 1566 1567 cpu = smp_processor_id(); 1568 1569 pr_info("\n"); 1570 for (i = 0; i < sparc_pmu->num_pcrs; i++) 1571 pr_info("CPU#%d: PCR%d[%016llx]\n", 1572 cpu, i, pcr_ops->read_pcr(i)); 1573 for (i = 0; i < sparc_pmu->num_pic_regs; i++) 1574 pr_info("CPU#%d: PIC%d[%016llx]\n", 1575 cpu, i, pcr_ops->read_pic(i)); 1576 1577 local_irq_restore(flags); 1578} 1579 1580static int __kprobes perf_event_nmi_handler(struct notifier_block *self, 1581 unsigned long cmd, void *__args) 1582{ 1583 struct die_args *args = __args; 1584 struct perf_sample_data data; 1585 struct cpu_hw_events *cpuc; 1586 struct pt_regs *regs; 1587 int i; 1588 1589 if (!atomic_read(&active_events)) 1590 return NOTIFY_DONE; 1591 1592 switch (cmd) { 1593 case DIE_NMI: 1594 break; 1595 1596 default: 1597 return NOTIFY_DONE; 1598 } 1599 1600 regs = args->regs; 1601 1602 cpuc = this_cpu_ptr(&cpu_hw_events); 1603 1604 /* If the PMU has the TOE IRQ enable bits, we need to do a 1605 * dummy write to the %pcr to clear the overflow bits and thus 1606 * the interrupt. 1607 * 1608 * Do this before we peek at the counters to determine 1609 * overflow so we don't lose any events. 1610 */ 1611 if (sparc_pmu->irq_bit && 1612 sparc_pmu->num_pcrs == 1) 1613 pcr_ops->write_pcr(0, cpuc->pcr[0]); 1614 1615 for (i = 0; i < cpuc->n_events; i++) { 1616 struct perf_event *event = cpuc->event[i]; 1617 int idx = cpuc->current_idx[i]; 1618 struct hw_perf_event *hwc; 1619 u64 val; 1620 1621 if (sparc_pmu->irq_bit && 1622 sparc_pmu->num_pcrs > 1) 1623 pcr_ops->write_pcr(idx, cpuc->pcr[idx]); 1624 1625 hwc = &event->hw; 1626 val = sparc_perf_event_update(event, hwc, idx); 1627 if (val & (1ULL << 31)) 1628 continue; 1629 1630 perf_sample_data_init(&data, 0, hwc->last_period); 1631 if (!sparc_perf_event_set_period(event, hwc, idx)) 1632 continue; 1633 1634 if (perf_event_overflow(event, &data, regs)) 1635 sparc_pmu_stop(event, 0); 1636 } 1637 1638 return NOTIFY_STOP; 1639} 1640 1641static __read_mostly struct notifier_block perf_event_nmi_notifier = { 1642 .notifier_call = perf_event_nmi_handler, 1643}; 1644 1645static bool __init supported_pmu(void) 1646{ 1647 if (!strcmp(sparc_pmu_type, "ultra3") || 1648 !strcmp(sparc_pmu_type, "ultra3+") || 1649 !strcmp(sparc_pmu_type, "ultra3i") || 1650 !strcmp(sparc_pmu_type, "ultra4+")) { 1651 sparc_pmu = &ultra3_pmu; 1652 return true; 1653 } 1654 if (!strcmp(sparc_pmu_type, "niagara")) { 1655 sparc_pmu = &niagara1_pmu; 1656 return true; 1657 } 1658 if (!strcmp(sparc_pmu_type, "niagara2") || 1659 !strcmp(sparc_pmu_type, "niagara3")) { 1660 sparc_pmu = &niagara2_pmu; 1661 return true; 1662 } 1663 if (!strcmp(sparc_pmu_type, "niagara4") || 1664 !strcmp(sparc_pmu_type, "niagara5")) { 1665 sparc_pmu = &niagara4_pmu; 1666 return true; 1667 } 1668 if (!strcmp(sparc_pmu_type, "sparc-m7")) { 1669 sparc_pmu = &sparc_m7_pmu; 1670 return true; 1671 } 1672 return false; 1673} 1674 1675static int __init init_hw_perf_events(void) 1676{ 1677 int err; 1678 1679 pr_info("Performance events: "); 1680 1681 err = pcr_arch_init(); 1682 if (err || !supported_pmu()) { 1683 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type); 1684 return 0; 1685 } 1686 1687 pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type); 1688 1689 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); 1690 register_die_notifier(&perf_event_nmi_notifier); 1691 1692 return 0; 1693} 1694pure_initcall(init_hw_perf_events); 1695 1696void perf_callchain_kernel(struct perf_callchain_entry *entry, 1697 struct pt_regs *regs) 1698{ 1699 unsigned long ksp, fp; 1700#ifdef CONFIG_FUNCTION_GRAPH_TRACER 1701 int graph = 0; 1702#endif 1703 1704 stack_trace_flush(); 1705 1706 perf_callchain_store(entry, regs->tpc); 1707 1708 ksp = regs->u_regs[UREG_I6]; 1709 fp = ksp + STACK_BIAS; 1710 do { 1711 struct sparc_stackf *sf; 1712 struct pt_regs *regs; 1713 unsigned long pc; 1714 1715 if (!kstack_valid(current_thread_info(), fp)) 1716 break; 1717 1718 sf = (struct sparc_stackf *) fp; 1719 regs = (struct pt_regs *) (sf + 1); 1720 1721 if (kstack_is_trap_frame(current_thread_info(), regs)) { 1722 if (user_mode(regs)) 1723 break; 1724 pc = regs->tpc; 1725 fp = regs->u_regs[UREG_I6] + STACK_BIAS; 1726 } else { 1727 pc = sf->callers_pc; 1728 fp = (unsigned long)sf->fp + STACK_BIAS; 1729 } 1730 perf_callchain_store(entry, pc); 1731#ifdef CONFIG_FUNCTION_GRAPH_TRACER 1732 if ((pc + 8UL) == (unsigned long) &return_to_handler) { 1733 int index = current->curr_ret_stack; 1734 if (current->ret_stack && index >= graph) { 1735 pc = current->ret_stack[index - graph].ret; 1736 perf_callchain_store(entry, pc); 1737 graph++; 1738 } 1739 } 1740#endif 1741 } while (entry->nr < PERF_MAX_STACK_DEPTH); 1742} 1743 1744static void perf_callchain_user_64(struct perf_callchain_entry *entry, 1745 struct pt_regs *regs) 1746{ 1747 unsigned long ufp; 1748 1749 ufp = regs->u_regs[UREG_I6] + STACK_BIAS; 1750 do { 1751 struct sparc_stackf __user *usf; 1752 struct sparc_stackf sf; 1753 unsigned long pc; 1754 1755 usf = (struct sparc_stackf __user *)ufp; 1756 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf))) 1757 break; 1758 1759 pc = sf.callers_pc; 1760 ufp = (unsigned long)sf.fp + STACK_BIAS; 1761 perf_callchain_store(entry, pc); 1762 } while (entry->nr < PERF_MAX_STACK_DEPTH); 1763} 1764 1765static void perf_callchain_user_32(struct perf_callchain_entry *entry, 1766 struct pt_regs *regs) 1767{ 1768 unsigned long ufp; 1769 1770 ufp = regs->u_regs[UREG_I6] & 0xffffffffUL; 1771 do { 1772 unsigned long pc; 1773 1774 if (thread32_stack_is_64bit(ufp)) { 1775 struct sparc_stackf __user *usf; 1776 struct sparc_stackf sf; 1777 1778 ufp += STACK_BIAS; 1779 usf = (struct sparc_stackf __user *)ufp; 1780 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf))) 1781 break; 1782 pc = sf.callers_pc & 0xffffffff; 1783 ufp = ((unsigned long) sf.fp) & 0xffffffff; 1784 } else { 1785 struct sparc_stackf32 __user *usf; 1786 struct sparc_stackf32 sf; 1787 usf = (struct sparc_stackf32 __user *)ufp; 1788 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf))) 1789 break; 1790 pc = sf.callers_pc; 1791 ufp = (unsigned long)sf.fp; 1792 } 1793 perf_callchain_store(entry, pc); 1794 } while (entry->nr < PERF_MAX_STACK_DEPTH); 1795} 1796 1797void 1798perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) 1799{ 1800 perf_callchain_store(entry, regs->tpc); 1801 1802 if (!current->mm) 1803 return; 1804 1805 flushw_user(); 1806 if (test_thread_flag(TIF_32BIT)) 1807 perf_callchain_user_32(entry, regs); 1808 else 1809 perf_callchain_user_64(entry, regs); 1810} 1811