252 				struct hw_perf_event *hwc, int idx)  in alpha_perf_event_set_period()  argument
254 	long left = local64_read(&hwc->period_left);  in alpha_perf_event_set_period()
255 	long period = hwc->sample_period;  in alpha_perf_event_set_period()
260 		local64_set(&hwc->period_left, left);  in alpha_perf_event_set_period()
261 		hwc->last_period = period;  in alpha_perf_event_set_period()
267 		local64_set(&hwc->period_left, left);  in alpha_perf_event_set_period()
268 		hwc->last_period = period;  in alpha_perf_event_set_period()
282 	local64_set(&hwc->prev_count, (unsigned long)(-left));  in alpha_perf_event_set_period()
307 					struct hw_perf_event *hwc, int idx, long ovf)  in alpha_perf_event_update()  argument
313 	prev_raw_count = local64_read(&hwc->prev_count);  in alpha_perf_event_update()
316 	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,  in alpha_perf_event_update()
330 	local64_sub(delta, &hwc->period_left);  in alpha_perf_event_update()
412 		struct hw_perf_event *hwc = &pe->hw;  in maybe_change_configuration()  local
413 		int idx = hwc->idx;  in maybe_change_configuration()
416 			alpha_perf_event_set_period(pe, hwc, idx);  in maybe_change_configuration()
420 		if (!(hwc->state & PERF_HES_STOPPED))  in maybe_change_configuration()
435 	struct hw_perf_event *hwc = &event->hw;  in alpha_pmu_add()  local
468 	hwc->state = PERF_HES_UPTODATE;  in alpha_pmu_add()
470 		hwc->state |= PERF_HES_STOPPED;  in alpha_pmu_add()
487 	struct hw_perf_event *hwc = &event->hw;  in alpha_pmu_del()  local
509 			alpha_perf_event_update(event, hwc, idx, 0);  in alpha_pmu_del()
525 	struct hw_perf_event *hwc = &event->hw;  in alpha_pmu_read()  local
527 	alpha_perf_event_update(event, hwc, hwc->idx, 0);  in alpha_pmu_read()
533 	struct hw_perf_event *hwc = &event->hw;  in alpha_pmu_stop()  local
536 	if (!(hwc->state & PERF_HES_STOPPED)) {  in alpha_pmu_stop()
537 		cpuc->idx_mask &= ~(1UL<<hwc->idx);  in alpha_pmu_stop()
538 		hwc->state |= PERF_HES_STOPPED;  in alpha_pmu_stop()
541 	if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {  in alpha_pmu_stop()
542 		alpha_perf_event_update(event, hwc, hwc->idx, 0);  in alpha_pmu_stop()
543 		hwc->state |= PERF_HES_UPTODATE;  in alpha_pmu_stop()
547 		wrperfmon(PERFMON_CMD_DISABLE, (1UL<<hwc->idx));  in alpha_pmu_stop()
553 	struct hw_perf_event *hwc = &event->hw;  in alpha_pmu_start()  local
556 	if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))  in alpha_pmu_start()
560 		WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));  in alpha_pmu_start()
561 		alpha_perf_event_set_period(event, hwc, hwc->idx);  in alpha_pmu_start()
564 	hwc->state = 0;  in alpha_pmu_start()
566 	cpuc->idx_mask |= 1UL<<hwc->idx;  in alpha_pmu_start()
568 		wrperfmon(PERFMON_CMD_ENABLE, (1UL<<hwc->idx));  in alpha_pmu_start()
604 	struct hw_perf_event *hwc = &event->hw;  in __hw_perf_event_init()  local
647 	hwc->event_base = ev;  in __hw_perf_event_init()
661 	evtypes[n] = hwc->event_base;  in __hw_perf_event_init()
668 	hwc->config_base = 0;  in __hw_perf_event_init()
669 	hwc->idx = PMC_NO_INDEX;  in __hw_perf_event_init()
683 	if (!hwc->sample_period) {  in __hw_perf_event_init()
684 		hwc->sample_period = alpha_pmu->pmc_max_period[0];  in __hw_perf_event_init()
685 		hwc->last_period = hwc->sample_period;  in __hw_perf_event_init()
686 		local64_set(&hwc->period_left, hwc->sample_period);  in __hw_perf_event_init()
814 	struct hw_perf_event *hwc;  in alpha_perf_event_irq_handler()  local
859 	hwc = &event->hw;  in alpha_perf_event_irq_handler()
860 	alpha_perf_event_update(event, hwc, idx, alpha_pmu->pmc_max_period[idx]+1);  in alpha_perf_event_irq_handler()
861 	perf_sample_data_init(&data, 0, hwc->last_period);  in alpha_perf_event_irq_handler()
863 	if (alpha_perf_event_set_period(event, hwc, idx)) {  in alpha_perf_event_irq_handler()