312 				    struct hw_perf_event *hwc)  in mipsxx_pmu_alloc_counter()  argument
320 	unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;  in mipsxx_pmu_alloc_counter()
376 				    struct hw_perf_event *hwc,  in mipspmu_event_set_period()  argument
379 	u64 left = local64_read(&hwc->period_left);  in mipspmu_event_set_period()
380 	u64 period = hwc->sample_period;  in mipspmu_event_set_period()
386 		local64_set(&hwc->period_left, left);  in mipspmu_event_set_period()
387 		hwc->last_period = period;  in mipspmu_event_set_period()
392 		local64_set(&hwc->period_left, left);  in mipspmu_event_set_period()
393 		hwc->last_period = period;  in mipspmu_event_set_period()
399 		local64_set(&hwc->period_left, left);  in mipspmu_event_set_period()
402 	local64_set(&hwc->prev_count, mipspmu.overflow - left);  in mipspmu_event_set_period()
412 				 struct hw_perf_event *hwc,  in mipspmu_event_update()  argument
419 	prev_raw_count = local64_read(&hwc->prev_count);  in mipspmu_event_update()
422 	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,  in mipspmu_event_update()
429 	local64_sub(delta, &hwc->period_left);  in mipspmu_event_update()
434 	struct hw_perf_event *hwc = &event->hw;  in mipspmu_start()  local
437 		WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));  in mipspmu_start()
439 	hwc->state = 0;  in mipspmu_start()
442 	mipspmu_event_set_period(event, hwc, hwc->idx);  in mipspmu_start()
445 	mipsxx_pmu_enable_event(hwc, hwc->idx);  in mipspmu_start()
450 	struct hw_perf_event *hwc = &event->hw;  in mipspmu_stop()  local
452 	if (!(hwc->state & PERF_HES_STOPPED)) {  in mipspmu_stop()
454 		mipsxx_pmu_disable_event(hwc->idx);  in mipspmu_stop()
456 		mipspmu_event_update(event, hwc, hwc->idx);  in mipspmu_stop()
457 		hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;  in mipspmu_stop()
464 	struct hw_perf_event *hwc = &event->hw;  in mipspmu_add()  local
471 	idx = mipsxx_pmu_alloc_counter(cpuc, hwc);  in mipspmu_add()
485 	hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;  in mipspmu_add()
500 	struct hw_perf_event *hwc = &event->hw;  in mipspmu_del()  local
501 	int idx = hwc->idx;  in mipspmu_del()
514 	struct hw_perf_event *hwc = &event->hw;  in mipspmu_read()  local
517 	if (hwc->idx < 0)  in mipspmu_read()
520 	mipspmu_event_update(event, hwc, hwc->idx);  in mipspmu_read()
743 	struct hw_perf_event *hwc = &event->hw;  in handle_associated_event()  local
745 	mipspmu_event_update(event, hwc, idx);  in handle_associated_event()
747 	if (!mipspmu_event_set_period(event, hwc, idx))  in handle_associated_event()
1234 	struct hw_perf_event *hwc = &event->hw;  in check_and_calc_range()  local
1242 			hwc->config_base |= M_TC_EN_ALL;  in check_and_calc_range()
1248 			hwc->config_base |= M_PERFCTL_VPEID(event->cpu);  in check_and_calc_range()
1249 			hwc->config_base |= M_TC_EN_VPE;  in check_and_calc_range()
1252 		hwc->config_base |= M_TC_EN_ALL;  in check_and_calc_range()
1264 	struct hw_perf_event *hwc = &event->hw;  in __hw_perf_event_init()  local
1294 	hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE;  in __hw_perf_event_init()
1300 	hwc->event_base = mipspmu_perf_event_encode(pev);  in __hw_perf_event_init()
1305 		hwc->config_base |= M_PERFCTL_USER;  in __hw_perf_event_init()
1307 		hwc->config_base |= M_PERFCTL_KERNEL;  in __hw_perf_event_init()
1309 		hwc->config_base |= M_PERFCTL_EXL;  in __hw_perf_event_init()
1312 		hwc->config_base |= M_PERFCTL_SUPERVISOR;  in __hw_perf_event_init()
1314 	hwc->config_base &= M_PERFCTL_CONFIG_MASK;  in __hw_perf_event_init()
1319 	hwc->idx = -1;  in __hw_perf_event_init()
1320 	hwc->config = 0;  in __hw_perf_event_init()
1322 	if (!hwc->sample_period) {  in __hw_perf_event_init()
1323 		hwc->sample_period  = mipspmu.max_period;  in __hw_perf_event_init()
1324 		hwc->last_period    = hwc->sample_period;  in __hw_perf_event_init()
1325 		local64_set(&hwc->period_left, hwc->sample_period);  in __hw_perf_event_init()