Searched refs:flush (Results 1 - 200 of 1882) sorted by relevance

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/linux-4.1.27/arch/sparc/include/asm/
H A Dcacheflush.h4 /* flush addr - to allow use of self-modifying code */
5 #define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
H A Dtlbflush_64.h6 /* TSB flush operations. */
21 /* TLB flush operations. */
H A Dross.h69 * FTD: If set to one flush instructions executed during an
72 * an unimplemented 'flush' trap will occur when any
73 * flush is executed by the processor.
H A Dcacheflush_32.h49 /* When a context switch happens we must flush all user windows so that
/linux-4.1.27/arch/sh/include/uapi/asm/
H A Dcachectl.h15 #define ICACHE CACHEFLUSH_I /* flush instruction cache */
16 #define DCACHE CACHEFLUSH_D_PURGE /* writeback and flush data cache */
17 #define BCACHE (ICACHE|DCACHE) /* flush both caches */
H A Dcpu-features.h16 #define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */
/linux-4.1.27/arch/blackfin/include/uapi/asm/
H A Dcachectl.h16 #define ICACHE (1<<0) /* flush instruction cache */
17 #define DCACHE (1<<1) /* writeback and flush data cache */
18 #define BCACHE (ICACHE|DCACHE) /* flush both caches */
/linux-4.1.27/arch/mn10300/mm/
H A DMakefile5 cache-smp-wback-$(CONFIG_MN10300_CACHE_WBACK) := cache-smp-flush.o
10 cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_ICACHE) += cache-flush-icache.o
13 cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_TAG) += cache-flush-by-tag.o
14 cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_REG) += cache-flush-by-reg.o
17 cache-dbg-flush-by-tag.o cache-dbg-inv-by-tag.o
19 cache-dbg-flush-by-reg.o
H A Dcache-smp-flush.c1 /* Functions for global dcache flush when writeback caching in SMP
16 * mn10300_dcache_flush - Globally flush data cache
31 * mn10300_dcache_flush_page - Globally flush a page of data cache
50 * mn10300_dcache_flush_range - Globally flush range of data cache
68 * mn10300_dcache_flush_range2 - Globally flush range of data cache
86 * mn10300_dcache_flush_inv - Globally flush and invalidate data cache
101 * mn10300_dcache_flush_inv_page - Globally flush and invalidate a page of data
121 * mn10300_dcache_flush_inv_range - Globally flush and invalidate range of data
140 * mn10300_dcache_flush_inv_range2 - Globally flush and invalidate range of data
H A Dcache-smp.c32 * smp_cache_interrupt - Handle IPI request to flush caches.
34 * Handle a request delivered by IPI to flush the current CPU's
81 * smp_cache_call - Issue an IPI to request the other CPUs flush caches
86 * Send cache flush IPI to other CPUs. This invokes smp_cache_interrupt()
H A Dcache-disabled.c14 * allow userspace to flush the instruction cache
H A Dcache-flush-icache.c59 /* work out how much of the page to flush */ flush_icache_page_range()
92 /* flush the dcache and invalidate the icache coverage on that flush_icache_page_range()
100 * flush_icache_range - Globally flush dcache and invalidate icache for region
104 * This is used by the kernel to globally flush some code it has just written
146 /* more than 2 pages; just flush the entire cache */ flush_icache_range()
H A Dcache-inv-icache.c37 /* work out how much of the page to flush */ flush_icache_page_range()
76 * flush_icache_range - Globally flush dcache and invalidate icache for region
80 * This is used by the kernel to globally flush some code it has just written
121 /* more than 2 pages; just flush the entire cache */ flush_icache_range()
H A Dcache.c45 * allow userspace to flush the instruction cache
H A Dtlb-smp.c39 * For flush TLB
91 * @mm: The VM context to flush from (if va!=FLUSH_ALL).
92 * @va: Virtual address to flush or FLUSH_ALL to flush everything.
H A Dcache-dbg-flush-by-tag.S34 # firstly flush the dcache
43 # read the addresses tagged in the cache's tag RAM and attempt to flush
H A Dcache-dbg-flush-by-reg.S33 # firstly flush the dcache
125 # now try to flush the icache
/linux-4.1.27/arch/m32r/include/asm/
H A Dcachectl.h14 #define ICACHE (1<<0) /* flush instruction cache */
15 #define DCACHE (1<<1) /* writeback and flush data cache */
16 #define BCACHE (ICACHE|DCACHE) /* flush both caches */
H A Dtlb.h13 * .. because we flush the whole mm when it
/linux-4.1.27/arch/arm64/mm/
H A DMakefile2 cache.o copypage.o flush.o \
/linux-4.1.27/arch/arm/include/debug/
H A Duncompress.h6 static inline void flush(void) {} arch_decomp_setup() function
/linux-4.1.27/include/linux/decompress/
H A Dunlzma.h6 long (*flush)(void*, unsigned long),
H A Dbunzip2.h6 long (*flush)(void*, unsigned long),
H A Dinflate.h6 long (*flush)(void*, unsigned long),
H A Dunlz4.h6 long (*flush)(void*, unsigned long),
H A Dunlzo.h6 long (*flush)(void*, unsigned long),
H A Dgeneric.h6 long (*flush)(void*, unsigned long),
14 *flush - function to write out outbuf
27 *If flush = NULL, outbuf must be large enough to buffer all the expected
28 *output. If flush != NULL, the output buffer will be allocated by the
29 *decompressor (outbuf = NULL), and the flush function will be called to
30 *flush the output buffer at the appropriate time (decompressor and stream
H A Dunxz.h15 long (*flush)(void *src, unsigned long size),
/linux-4.1.27/block/
H A Dblk-flush.c14 * indicates a simple flush request. If there is data, REQ_FLUSH indicates
29 * The actual execution of flush is double buffered. Whenever a request
32 * flush is issued and the pending_idx is toggled. When the flush
38 * flush.
40 * C1. At any given time, only one flush shall be in progress. This makes
88 * If flush has been pending longer than the following timeout,
115 return 1 << ffz(rq->flush.seq); blk_flush_cur_seq()
121 * After flush data completion, @rq->bio is %NULL but we need to blk_flush_restore_request()
129 rq->end_io = rq->flush.saved_end_io; blk_flush_restore_request()
150 * blk_flush_complete_seq - complete flush sequence
152 * @fq: flush queue
156 * @rq just completed @seq part of its flush sequence, record the
173 BUG_ON(rq->flush.seq & seq); blk_flush_complete_seq()
174 rq->flush.seq |= seq; blk_flush_complete_seq()
184 /* queue for flush */ blk_flush_complete_seq()
187 list_move_tail(&rq->flush.list, pending); blk_flush_complete_seq()
191 list_move_tail(&rq->flush.list, &fq->flush_data_in_flight); blk_flush_complete_seq()
198 * flush sequencing and may already have gone through the blk_flush_complete_seq()
199 * flush data request completion path. Restore @rq for blk_flush_complete_seq()
203 list_del_init(&rq->flush.list); blk_flush_complete_seq()
236 /* account completion of the flush request */ flush_end_io()
243 list_for_each_entry_safe(rq, n, running, flush.list) { list_for_each_entry_safe()
254 * 2. When flush request is running in non-queueable queue, the
255 * queue is hold. Restart the queue after flush request is finished
271 * blk_kick_flush - consider issuing flush request
273 * @fq: flush queue
275 * Flush related states of @q have changed, consider issuing flush request.
282 * %true if flush was issued, %false otherwise.
288 list_first_entry(pending, struct request, flush.list); blk_kick_flush()
302 * Issue flush and toggle pending_idx. This makes pending_idx blk_kick_flush()
303 * different from running_idx, which means flush is in flight. blk_kick_flush()
387 * An empty flush handed down from a stacking driver may blk_insert_flush()
403 * If there's data but flush is not necessary, the request can be blk_insert_flush()
404 * processed directly without going through flush machinery. Queue blk_insert_flush()
417 * @rq should go through flush machinery. Mark it part of flush blk_insert_flush()
420 memset(&rq->flush, 0, sizeof(rq->flush)); blk_insert_flush()
421 INIT_LIST_HEAD(&rq->flush.list); blk_insert_flush()
423 rq->flush.saved_end_io = rq->end_io; /* Usually NULL */ blk_insert_flush()
438 * blkdev_issue_flush - queue a flush
439 * @bdev: blockdev to issue flush for
444 * Issue a flush for the block device in question. Caller can supply
445 * room for storing the error offset in case of a flush error, if they
465 * (e.g. loop device without a backing file) and so issuing a flush blkdev_issue_flush()
467 * the flush. blkdev_issue_flush()
523 /* bio based request queue hasn't flush queue */ blk_free_flush_queue()
/linux-4.1.27/arch/mips/include/uapi/asm/
H A Dcachectl.h14 #define ICACHE (1<<0) /* flush instruction cache */
15 #define DCACHE (1<<1) /* writeback and flush data cache */
16 #define BCACHE (ICACHE|DCACHE) /* flush both caches */
H A Dioctls.h38 #define TIOCPKT_FLUSHREAD 0x01 /* flush packet */
39 #define TIOCPKT_FLUSHWRITE 0x02 /* flush packet */
68 #define TIOCSETN 0x740a /* TIOCSETP wo flush */
/linux-4.1.27/arch/x86/include/asm/xen/
H A Dtrace_types.h5 XEN_MC_FL_NONE, /* explicit flush */
/linux-4.1.27/arch/unicore32/mm/
H A DMakefile6 obj-y += flush.o ioremap.o
H A Dcache-ucv2.S34 movc p0.c5, r0, #14 @ Dcache flush all
73 movc p0.c5, ip, #14 @ Dcache flush all
140 movc p0.c5, ip, #14 @ Dcache flush all
208 movc p0.c5, ip, #14 @ Dcache flush all
/linux-4.1.27/arch/mips/include/asm/mach-rc32434/
H A Drc32434.h13 /* cpu pipeline flush */ rc32434_sync()
/linux-4.1.27/arch/cris/arch-v10/kernel/
H A Dcrisksyms.c14 /* Cache flush functions */
/linux-4.1.27/arch/frv/mm/
H A DMakefile8 pgalloc.o highmem.o fault.o extable.o cache-page.o tlb-flush.o tlb-miss.o \
H A Dtlb-flush.S1 /* tlb-flush.S: TLB flushing routines
41 # flush everything
85 # flush everything to do with one context
99 # specify the context we want to flush
126 # flush a range of addresses from the TLB
139 # specify the context we want to flush
153 # flush a range of addresses from the TLB
167 # specify the context we want to flush
180 bne icc0,#0,2b ; most likely a 1-page flush
/linux-4.1.27/arch/arc/include/asm/
H A Dtlb.h19 * This pair is called at time of munmap/exit to flush cache and TLB entries
21 * 1) cache-flush part -implemented via tlb_start_vma( ) for VIPT aliasing D$
22 * 2) tlb-flush part - implemted via tlb_end_vma( ) flushes the TLB range
H A Dcacheflush.h14 * -Added a critical CacheLine flush to copy_to_user_page( ) which
26 * However ARC Cache flush requires paddr as well as vaddr, latter not available
/linux-4.1.27/arch/mips/include/asm/
H A Dtlb.h6 * we need to flush cache for area to be unmapped.
17 * .. because we flush the whole mm when it fills up.
H A Dcacheflush.h23 * - flush_icache_range(start, end) flush a range of instructions
26 * MIPS specific flush operations:
28 * - flush_cache_sigtramp() flush signal trampoline
29 * - flush_icache_all() flush the entire instruction cache
/linux-4.1.27/net/ipv4/
H A Dtcp_offload.c190 int flush = 1; tcp_gro_receive() local
236 flush = NAPI_GRO_CB(p)->flush | NAPI_GRO_CB(p)->flush_id; tcp_gro_receive()
237 flush |= (__force int)(flags & TCP_FLAG_CWR); tcp_gro_receive()
238 flush |= (__force int)((flags ^ tcp_flag_word(th2)) & tcp_gro_receive()
240 flush |= (__force int)(th->ack_seq ^ th2->ack_seq); tcp_gro_receive()
242 flush |= *(u32 *)((u8 *)th + i) ^ tcp_gro_receive()
247 flush |= (len - 1) >= mss; tcp_gro_receive()
248 flush |= (ntohl(th2->seq) + skb_gro_len(p)) ^ ntohl(th->seq); tcp_gro_receive()
250 if (flush || skb_gro_receive(head, skb)) { tcp_gro_receive()
260 flush = len < mss; tcp_gro_receive()
261 flush |= (__force int)(flags & (TCP_FLAG_URG | TCP_FLAG_PSH | tcp_gro_receive()
265 if (p && (!NAPI_GRO_CB(skb)->same_flow || flush)) tcp_gro_receive()
269 NAPI_GRO_CB(skb)->flush |= (flush != 0); tcp_gro_receive()
293 /* Don't bother verifying checksum if we're going to flush anyway. */ tcp4_gro_receive()
294 if (!NAPI_GRO_CB(skb)->flush && tcp4_gro_receive()
297 NAPI_GRO_CB(skb)->flush = 1; tcp4_gro_receive()
H A Dudp_offload.c300 int flush = 1; udp_gro_receive() local
321 flush = 0; udp_gro_receive()
348 NAPI_GRO_CB(skb)->flush |= flush; udp_gro_receive()
358 goto flush; udp4_gro_receive()
360 /* Don't bother verifying checksum if we're going to flush anyway. */ udp4_gro_receive()
361 if (NAPI_GRO_CB(skb)->flush) udp4_gro_receive()
366 goto flush; udp4_gro_receive()
374 flush: udp4_gro_receive()
375 NAPI_GRO_CB(skb)->flush = 1; udp4_gro_receive()
H A Dgre_offload.c127 int flush = 1; gre_gro_receive() local
171 /* Don't bother verifying checksum if we're going to flush anyway. */ gre_gro_receive()
172 if ((greh->flags & GRE_CSUM) && !NAPI_GRO_CB(skb)->flush) { gre_gro_receive()
180 flush = 0; gre_gro_receive()
222 NAPI_GRO_CB(skb)->flush |= flush; gre_gro_receive()
/linux-4.1.27/lib/
H A Ddecompress_inflate.c39 long (*flush)(void*, unsigned long), __gunzip()
48 if (flush) { __gunzip()
77 strm->workspace = malloc(flush ? zlib_inflate_workspacesize() : __gunzip()
125 if (!flush) { __gunzip()
145 if (flush && strm->next_out > out_buf) { __gunzip()
147 if (l != flush(out_buf, l)) { __gunzip()
179 if (flush) __gunzip()
188 long (*flush)(void*, unsigned long), gunzip()
193 return __gunzip(buf, len, fill, flush, out_buf, 0, pos, error); gunzip()
198 long (*flush)(void*, unsigned long), __decompress()
203 return __gunzip(buf, len, fill, flush, out_buf, out_len, pos, error); __decompress()
37 __gunzip(unsigned char *buf, long len, long (*fill)(void*, unsigned long), long (*flush)(void*, unsigned long), unsigned char *out_buf, long out_len, long *pos, void(*error)(char *x)) __gunzip() argument
186 gunzip(unsigned char *buf, long len, long (*fill)(void*, unsigned long), long (*flush)(void*, unsigned long), unsigned char *out_buf, long *pos, void (*error)(char *x)) gunzip() argument
196 __decompress(unsigned char *buf, long len, long (*fill)(void*, unsigned long), long (*flush)(void*, unsigned long), unsigned char *out_buf, long out_len, long *pos, void (*error)(char *x)) __decompress() argument
H A Ddecompress_unlz4.c36 long (*flush)(void *, unsigned long), unlz4()
55 } else if (!flush) { unlz4()
56 error("NULL output pointer and no flush function provided"); unlz4()
167 if (flush && flush(outp, dest_len) != dest_len) unlz4()
201 long (*flush)(void*, unsigned long), __decompress()
207 return unlz4(buf, in_len - 4, fill, flush, output, posp, error); __decompress()
199 __decompress(unsigned char *buf, long in_len, long (*fill)(void*, unsigned long), long (*flush)(void*, unsigned long), unsigned char *output, long out_len, long *posp, void (*error)(char *x) ) __decompress() argument
H A Ddecompress_unlzo.c114 long (*flush)(void *, unsigned long), unlzo()
127 } else if (!flush) { unlzo()
128 error("NULL output pointer and no flush function provided"); unlzo()
258 if (flush && flush(out_buf, dst_len) != dst_len) unlzo()
294 long (*flush)(void*, unsigned long), __decompress()
299 return unlzo(buf, len, fill, flush, out_buf, pos, error); __decompress()
292 __decompress(unsigned char *buf, long len, long (*fill)(void*, unsigned long), long (*flush)(void*, unsigned long), unsigned char *out_buf, long olen, long *pos, void (*error)(char *x)) __decompress() argument
H A Ddecompress_unlzma.c283 long (*flush)(void*, unsigned long); member in struct:writer
301 if (!wr->flush) { peek_old_byte()
319 if (wr->flush && wr->buffer_pos == wr->header->dict_size) { write_byte()
322 if (wr->flush((char *)wr->buffer, wr->header->dict_size) write_byte()
539 long (*flush)(void*, unsigned long), unlzma()
573 wr.flush = flush; unlzma()
655 if (!wr.flush || wr.flush(wr.buffer, wr.buffer_pos) == wr.buffer_pos) unlzma()
672 long (*flush)(void*, unsigned long), __decompress()
677 return unlzma(buf, in_len - 4, fill, flush, output, posp, error); __decompress()
537 unlzma(unsigned char *buf, long in_len, long (*fill)(void*, unsigned long), long (*flush)(void*, unsigned long), unsigned char *output, long *posp, void(*error)(char *x) ) unlzma() argument
670 __decompress(unsigned char *buf, long in_len, long (*fill)(void*, unsigned long), long (*flush)(void*, unsigned long), unsigned char *output, long out_len, long *posp, void (*error)(char *x)) __decompress() argument
H A Ddecompress_unxz.c249 * fill() and flush() won't be used.
253 long (*flush)(void *src, unsigned long size), unxz()
269 if (fill == NULL && flush == NULL) unxz()
277 if (flush == NULL) { unxz()
299 if (fill == NULL && flush == NULL) { unxz()
325 if (flush != NULL && (b.out_pos == b.out_size unxz()
332 if (flush(b.out, b.out_pos) != (long)b.out_pos) unxz()
342 if (flush != NULL) unxz()
382 if (flush != NULL) unxz()
400 long (*flush)(void*, unsigned long), __decompress()
405 return unxz(buf, len, fill, flush, out_buf, pos, error); __decompress()
398 __decompress(unsigned char *buf, long len, long (*fill)(void*, unsigned long), long (*flush)(void*, unsigned long), unsigned char *out_buf, long olen, long *pos, void (*error)(char *x)) __decompress() argument
/linux-4.1.27/arch/metag/mm/
H A Dcache.c81 /* flush the cache line to fix any incoherency */ metag_lnkget_probe()
99 * gateway page won't flush and userland could break. metag_lnkget_probe()
207 /* Use a sequence of writes to flush the cache region requested */ metag_phys_data_cache_flush()
214 /* Move to the base of the physical cache flush region */ metag_phys_data_cache_flush()
287 /* No need to flush the data cache it's not actually enabled */ metag_data_cache_flush_all()
299 /* No need to flush the data cache it's not actually enabled */ metag_data_cache_flush()
307 /* Use linear cache flush mechanism on META IP */ metag_data_cache_flush()
352 /* Use a sequence of writes to flush the cache region requested */ metag_phys_code_cache_flush()
357 /* Move to the base of the physical cache flush region */ metag_phys_code_cache_flush()
458 /* No need to flush the code cache it's not actually enabled */ metag_code_cache_flush_all()
468 void *flush; metag_code_cache_flush() local
473 /* No need to flush the code cache it's not actually enabled */ metag_code_cache_flush()
477 /* CACHEWD isn't available on Meta1, so always do full cache flush */ metag_code_cache_flush()
481 /* If large size do full physical cache flush */ metag_code_cache_flush()
487 /* Use linear cache flush mechanism on META IP */ metag_code_cache_flush()
488 flush = (void *)((int)start & ~(ICACHE_LINE_BYTES-1)); metag_code_cache_flush()
505 PRIM_IFLUSH(flush, 3); metag_code_cache_flush()
509 PRIM_IFLUSH(flush, 2); metag_code_cache_flush()
511 PRIM_IFLUSH(flush, 1); metag_code_cache_flush()
513 PRIM_IFLUSH(flush, 0); metag_code_cache_flush()
514 flush += LOOP_INC; metag_code_cache_flush()
/linux-4.1.27/arch/x86/mm/
H A Dtlb.c26 * More scalable flush, from Andi Kleen
28 * Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi
61 * The flush IPI assumes that a thread switch happens in this order:
66 * Now the tlb flush NMI handler flush_tlb_func won't call leave_mm
71 * Now the other cpus will send tlb flush ipis.
75 * the other cpus, but flush_tlb_func ignore flush ipis for the wrong
76 * mm, and in the worst case we perform a superfluous tlb flush.
78 * cpu active_mm is correct, cpu0 already handles flush ipis.
81 * Atomically set the bit [other cpus will start sending flush ipis],
83 * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
97 * TLB flush funcation:
178 * flush is about 100 ns, so this caps the maximum overhead at
189 /* do a global flush by default */ flush_tlb_mm_range()
221 /* flush range by one by one 'invlpg' */ flush_tlb_mm_range()
284 /* flush range by one by one 'invlpg' */ do_kernel_range_flush()
292 /* Balance as user space task's flush, a bit conservative */ flush_tlb_kernel_range()
/linux-4.1.27/arch/score/include/asm/
H A Dtlb.h6 * we need to flush cache for area to be unmapped.
/linux-4.1.27/arch/blackfin/include/asm/
H A Dtlb.h15 * .. because we flush the whole mm when it
H A Dcacheflush.h53 * needs to be after the data flush and before the icache flush_icache_range()
54 * flush so that the SSYNC does the right thing in preventing flush_icache_range()
/linux-4.1.27/arch/m68k/include/asm/
H A Dtlb.h13 * .. because we flush the whole mm when it
H A Dtlbflush.h27 * flush all user-space atc entries.
63 * flush all atc entries (both kernel and user-space entries).
115 /* Flush all userspace mappings one by one... (why no flush command,
233 * flush all user-space atc entries.
248 * flush all atc entries (both kernel and user-space entries).
H A Dm53xxacr.h86 * Unified cache means we will never need to flush for coherency of
87 * instruction fetch. We will need to flush to maintain memory/DMA
/linux-4.1.27/arch/m68k/include/uapi/asm/
H A Dcachectl.h10 #define FLUSH_CACHE_DATA 1 /* Writeback and flush data cache */
/linux-4.1.27/arch/arm/mach-iop13xx/include/mach/
H A Duncompress.h15 static inline void flush(void) flush() function
/linux-4.1.27/arch/s390/include/asm/
H A Dtlbflush.h22 /* Global TLB flush for the mm */ __tlb_flush_idte()
33 /* Local TLB flush for the mm */ __tlb_flush_idte_local()
69 /* Local TLB flush */ __tlb_flush_full()
72 /* Global TLB flush */ __tlb_flush_full()
74 /* Reset TLB flush mask */ __tlb_flush_full()
101 /* Reset TLB flush mask */ __tlb_flush_asce()
146 * If the machine has IDTE we prefer to do a per mm flush __tlb_flush_mm()
147 * on all cpus instead of doing a local flush if the mm __tlb_flush_mm()
179 * ptep_get_and_clear do not flush the TLBs directly if the mm has
181 * flush_tlb_range functions need to do the flush.
/linux-4.1.27/arch/tile/include/uapi/asm/
H A Dcachectl.h21 * The ICACHE flush is performed on all cores currently running the
34 * to flush the entire L1+L2 data cache from the core. In this case,
35 * the address and length arguments are not used. The DCACHE flush is
39 #define DCACHE (1<<1) /* flush and invalidate data cache */
40 #define BCACHE (ICACHE|DCACHE) /* flush both caches */
/linux-4.1.27/include/uapi/linux/
H A Dnfs_fs.h34 #define FLUSH_LOWPRI 8 /* low priority background flush */
35 #define FLUSH_HIGHPRI 16 /* high priority memory reclaim flush */
/linux-4.1.27/arch/avr32/kernel/
H A Dswitch_to.S31 frs /* flush the return stack */
32 sub pc, -2 /* flush the pipeline */
/linux-4.1.27/arch/ia64/sn/kernel/sn2/
H A Dcache.c14 * sn_flush_all_caches - flush a range of address from all caches (incl. L4)
16 * @bytes: number of bytes to flush
/linux-4.1.27/arch/arm/boot/compressed/
H A Dhead-xscale.S17 @ Be sure to flush kernel binary out of the cache,
27 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
H A Dhead-sa1100.S31 @ Be sure to flush kernel binary out of the cache,
41 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
H A Dhead.S632 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
633 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
642 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
643 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
743 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
750 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
764 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
798 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
803 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
818 sub pc, lr, r0, lsr #32 @ properly flush pipeline
846 * __armv7_mmu_cache_{on,off,flush}) would be selected which
869 * - 'cache flush' method instruction
874 * methods. Writeback caches _must_ have the flush method
1051 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1052 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1094 * Clean and flush the cache to maintain consistency.
1130 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1210 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1237 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1238 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1243 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1244 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
/linux-4.1.27/arch/frv/include/asm/
H A Dtlb.h20 * .. because we flush the whole mm when it fills up
/linux-4.1.27/arch/metag/include/asm/
H A Dbarrier.h22 * ATP doesn't have system event to fence writes, so it is necessary to flush
26 * register (in this case write combiner flush) which will also flush the write
42 /* flush writes through the write combiner */
H A Dtlbflush.h20 * FIXME: Meta 2 can flush single TLB entries.
27 /* flush TLB entries for just the current hardware thread */ __flush_tlb()
35 /* flush TLB entries for all hardware threads */ __flush_tlb()
H A Dcacheflush.h18 * Routines to flush physical cache lines that may be used to cache data or code
39 /* flush the entire user address space referenced in this mm structure */ flush_cache_mm()
48 /* flush a range of addresses from this mm */ flush_cache_range()
134 * We don't need to flush the dcache, it's write through and flush_cache_sigtramp()
191 * effect. Therefore fully flush the line first. l2c_fence()
200 /* metag_data_cache_flush won't flush L2 cache lines if size >= 4096 */ flush_dcache_region()
/linux-4.1.27/arch/arm/mach-dove/include/mach/
H A Duncompress.h29 static void flush(void) flush() function
/linux-4.1.27/arch/arm/mach-iop32x/include/mach/
H A Duncompress.h21 static inline void flush(void) flush() function
/linux-4.1.27/arch/arm/mach-iop33x/include/mach/
H A Duncompress.h21 static inline void flush(void) flush() function
/linux-4.1.27/arch/tile/mm/
H A Dmigrate.h29 * you can't legally touch the stack during the cache flush.
39 * - Do a global TLB flush for (va,length) and the specified ASIDs.
47 * you can't legally touch the stack during the cache flush.
H A Dmigrate_32.S76 * Create a stack frame; we can't touch it once we flush the
77 * cache until we install the new page table and flush the TLB.
118 /* First, flush our L2 cache. */
158 /* Finally, flush the TLB. */
H A Dmigrate_64.S73 * Create a stack frame; we can't touch it once we flush the
74 * cache until we install the new page table and flush the TLB.
103 /* First, flush our L2 cache. */
142 /* Finally, flush the TLB. */
/linux-4.1.27/net/ipv6/
H A Dtcpv6_offload.c21 /* Don't bother verifying checksum if we're going to flush anyway. */ tcp6_gro_receive()
22 if (!NAPI_GRO_CB(skb)->flush && tcp6_gro_receive()
25 NAPI_GRO_CB(skb)->flush = 1; tcp6_gro_receive()
H A Dip6_offload.c176 u16 flush = 1; ipv6_gro_receive() local
192 flush += ntohs(iph->payload_len) != skb_gro_len(skb); ipv6_gro_receive()
213 flush--; ipv6_gro_receive()
238 /* flush if Traffic Class fields are different */ ipv6_gro_receive()
239 NAPI_GRO_CB(p)->flush |= !!(first_word & htonl(0x0FF00000)); ipv6_gro_receive()
240 NAPI_GRO_CB(p)->flush |= flush; ipv6_gro_receive()
246 NAPI_GRO_CB(skb)->flush |= flush; ipv6_gro_receive()
256 NAPI_GRO_CB(skb)->flush |= flush; ipv6_gro_receive()
H A Dudp_offload.c135 goto flush; udp6_gro_receive()
137 /* Don't bother verifying checksum if we're going to flush anyway. */ udp6_gro_receive()
138 if (NAPI_GRO_CB(skb)->flush) udp6_gro_receive()
143 goto flush; udp6_gro_receive()
152 flush: udp6_gro_receive()
153 NAPI_GRO_CB(skb)->flush = 1; udp6_gro_receive()
/linux-4.1.27/lib/zlib_deflate/
H A Ddeflate.c61 block_done, /* block flush performed */
66 typedef block_state (*compress_func) (deflate_state *s, int flush);
70 static block_state deflate_stored (deflate_state *s, int flush);
71 static block_state deflate_fast (deflate_state *s, int flush);
72 static block_state deflate_slow (deflate_state *s, int flush);
329 int flush zlib_deflate()
332 int old_flush; /* value of flush param for previous deflate call */ zlib_deflate()
336 flush > Z_FINISH || flush < 0) { zlib_deflate()
342 (s->status == FINISH_STATE && flush != Z_FINISH)) { zlib_deflate()
349 s->last_flush = flush; zlib_deflate()
391 } else if (strm->avail_in == 0 && flush <= old_flush && zlib_deflate()
392 flush != Z_FINISH) { zlib_deflate()
404 (flush != Z_NO_FLUSH && s->status != FINISH_STATE)) { zlib_deflate()
407 bstate = (*(configuration_table[s->level].func))(s, flush); zlib_deflate()
417 /* If flush != Z_NO_FLUSH && avail_out == 0, the next call zlib_deflate()
418 * of deflate should use the same flush parameter to make sure zlib_deflate()
419 * that the flush is complete. So we don't have to output an zlib_deflate()
426 if (flush == Z_PARTIAL_FLUSH) { zlib_deflate()
428 } else if (flush == Z_PACKET_FLUSH) { zlib_deflate()
434 /* For a full flush, this empty block will be recognized zlib_deflate()
437 if (flush == Z_FULL_FLUSH) { zlib_deflate()
450 if (flush != Z_FINISH) return Z_OK; zlib_deflate()
458 * to flush the rest. zlib_deflate()
855 int flush deflate_stored()
877 if (s->lookahead == 0 && flush == Z_NO_FLUSH) return need_more; deflate_stored()
879 if (s->lookahead == 0) break; /* flush the current block */ deflate_stored()
901 FLUSH_BLOCK(s, flush == Z_FINISH); deflate_stored()
902 return flush == Z_FINISH ? finish_done : block_done; deflate_stored()
914 int flush deflate_fast()
928 if (s->lookahead < MIN_LOOKAHEAD && flush == Z_NO_FLUSH) { deflate_fast()
931 if (s->lookahead == 0) break; /* flush the current block */ deflate_fast()
997 FLUSH_BLOCK(s, flush == Z_FINISH); deflate_fast()
998 return flush == Z_FINISH ? finish_done : block_done; deflate_fast()
1008 int flush deflate_slow()
1023 if (s->lookahead < MIN_LOOKAHEAD && flush == Z_NO_FLUSH) { deflate_slow()
1026 if (s->lookahead == 0) break; /* flush the current block */ deflate_slow()
1113 Assert (flush != Z_NO_FLUSH, "no flush?"); deflate_slow()
1119 FLUSH_BLOCK(s, flush == Z_FINISH); deflate_slow()
1120 return flush == Z_FINISH ? finish_done : block_done; deflate_slow()
/linux-4.1.27/arch/mips/mm/
H A Dc-octeon.c63 * @vma: VMA to flush or NULL to flush all icaches.
97 * Called to flush the icache on all cores
106 * Called to flush all memory associated with a memory
109 * @mm: Memory context to flush
134 * @addr: Address to flush
150 * @vma: VMA to flush
165 * @vma: VMA to flush page for
166 * @page: Page to flush
278 * Setup the Octeon cache flush routines
H A Dsc-ip22.c43 "or\t%0, $1\t\t\t# first line to flush\n\t" indy_sc_wipe()
44 "or\t%1, $1\t\t\t# last line to flush\n\t" indy_sc_wipe()
70 /* Which lines to flush? */ indy_sc_wback_invalidate()
/linux-4.1.27/arch/mn10300/kernel/
H A Dmn10300-serial-low.S72 movhu (e3),d2 # flush
95 movhu (a2),d2 # flush
119 movhu (e3),d2 # flush
160 movhu (a2),d2 # flush
169 movhu (e3),d2 # flush
184 movhu (e3),d2 # flush
/linux-4.1.27/arch/powerpc/mm/
H A Dtlb_hash32.c4 * physical translations, these routines flush entries from the
38 * Called when unmapping pages to flush entries from the TLB/hash table.
52 * Called by ptep_set_access_flags, must flush on CPUs for which the
64 * TLB flush is completely done.
70 * 603 needs to flush the whole TLB here since tlb_flush()
86 * tlb as far as the linux tables are concerned, flush it too.
H A Dtlb_hash64.c39 * neesd to be flushed. This function will either perform the flush
96 * flush now and return. For now, we don global invalidates hpte_need_flush()
136 * is full. It will perform the flush of all the entries currently stored
162 /* If there's a TLB batch pending, then we must flush it because the tlb_flush()
179 * @end : ending address (not included in the flush)
203 * since we don't actually modify the PTEs, we just flush the __flush_hash_table_range()
240 * since we don't actually modify the PTEs, we just flush the flush_tlb_pmd_range()
/linux-4.1.27/arch/arm/mm/
H A Dcopypage-v4wt.c10 * This is for CPUs with a writethrough cache and 'flush ID cache' is
40 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache\n\ v4wt_copy_user_page()
78 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache" v4wt_clear_user_highpage()
H A Dproc-arm940.S54 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
55 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
102 * There is no efficient way to flush a range of cache entries
112 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
116 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
166 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
188 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
235 mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
H A Dproc-arm720.S82 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
90 * Purpose : Set a PTE and flush it out of any WB cache
109 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
124 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
152 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
H A Dflush.c2 * linux/arch/arm/mm/flush.c
218 * we only need to do one flush - which would be at the relevant __flush_dcache_page()
265 /* only flush non-aliasing VIPT caches for exec mappings */ __sync_icache_dcache()
301 * Note that we disable the lazy flush for SMP configurations where
337 * dirty at creation. Otherwise, we need to flush the dirty kernel
389 * For aliasing VIPT, we can flush an alias of the __flush_anon_page()
/linux-4.1.27/arch/sparc/lib/
H A DGENpatch.S23 flush %g2;
H A DNG2patch.S23 flush %g2;
H A DNGpatch.S23 flush %g2;
H A DU3patch.S23 flush %g2;
H A DNG4patch.S23 flush %g2;
H A Dclear_page.S22 * Then we do a normal TLB flush on exit. We need only
67 flush %g1
H A DGENpage.S67 flush %g2;
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dbar.h18 void (*flush)(struct nvkm_bar *); member in struct:nvkm_bar
/linux-4.1.27/arch/mips/ath79/
H A Dirq.c60 /* flush write */ ar71xx_misc_irq_unmask()
73 /* flush write */ ar71xx_misc_irq_mask()
86 /* flush write */ ar724x_misc_irq_ack()
171 /* TODO: flush DDR? */ qca955x_ip2_irq_dispatch()
176 /* TODO: flush DDR? */ qca955x_ip2_irq_dispatch()
201 /* TODO: flush DDR? */ qca955x_ip3_irq_dispatch()
206 /* TODO: flush DDR? */ qca955x_ip3_irq_dispatch()
211 /* TODO: flush DDR? */ qca955x_ip3_irq_dispatch()
270 * Issue a flush in the handlers to ensure that the driver sees
/linux-4.1.27/arch/mn10300/include/asm/
H A Datomic.h58 " mov (_ADR,%3),%0 \n" /* flush */ \
77 " mov (_ADR,%3),%0 \n" /* flush */ \
147 " mov (_ADR,%2),%0 \n" /* flush */ atomic_clear_mask()
181 " mov (_ADR,%2),%0 \n" /* flush */ atomic_set_mask()
H A Dtlb.h27 * .. because we flush the whole mm when it fills up
H A Dcmpxchg.h28 " mov (_ADR,%3),%0 \n" /* flush */ __xchg()
51 "2: mov (_ADR,%3),%0 \n" /* flush */ __cmpxchg()
/linux-4.1.27/arch/powerpc/kernel/
H A Dswsusp.c20 * flush out all the special registers so we don't need save_processor_state()
H A Dmce_power.c57 * Generic routine to flush TLB on power7. This routine is used as
69 * Generic routine to flush TLB on power8. This routine is used as
80 /* flush SLBs and reload */ flush_and_reload_slb()
92 * only flush the SLBs and continue. flush_and_reload_slb()
120 * flush and reload SLBs for SLB errors and flush TLBs for TLB errors. mce_handle_derror()
156 /* flush and reload SLBs for SLB errors. */ mce_handle_common_ierror()
/linux-4.1.27/arch/blackfin/mach-common/
H A Dcache.S22 * them. Only the actual flush instruction differs. We write this in asm as
104 * instruction, we use flush/invalidate. Perhaps as a speed optimization we
116 /* Our headers convert the page structure to an address, so just need to flush
119 * the middle of the dcache flush function.
/linux-4.1.27/arch/arm/mach-orion5x/include/mach/
H A Duncompress.h30 static void flush(void) flush() function
/linux-4.1.27/arch/arm/mach-spear/include/mach/
H A Duncompress.h33 static inline void flush(void) flush() function
/linux-4.1.27/arch/arm/mach-ebsa110/include/mach/
H A Duncompress.h30 static inline void flush(void) flush() function
/linux-4.1.27/arch/arm/mach-footbridge/include/mach/
H A Duncompress.h30 static inline void flush(void) flush() function
H A Dhardware.h19 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
23 * 0xf9000000 0x50000000 1MB Cache flush
/linux-4.1.27/arch/arm/mach-ks8695/include/mach/
H A Duncompress.h28 static inline void flush(void) flush() function
/linux-4.1.27/arch/arm/mach-mmp/include/mach/
H A Duncompress.h34 static inline void flush(void) flush() function
/linux-4.1.27/arch/arm/mach-mv78xx0/include/mach/
H A Duncompress.h28 static void flush(void) flush() function
/linux-4.1.27/drivers/gpu/drm/i915/
H A Dintel_frontbuffer.c36 * frontbuffer rendering has stopped again to flush out all the changes and when
45 * into the invalidate and the flush functions: At invalidate the caching must
46 * be stopped and at flush time it can be restarted. And maybe they need to know
48 * and flush on its own) which can be achieved with placing callbacks into the
52 * (e.g. DRRS). In that case all three (invalidate, flush and flip) indicate
54 * work delayed work should be started from the flush and flip functions and
162 * intel_frontbuffer_flush - flush frontbuffer
190 * intel_fb_obj_flush - flush frontbuffer object
191 * @obj: GEM object to flush
232 * flush will be cancelled.
254 * on the next vblank. It will execute the flush if it hasn't been cancelled yet.
/linux-4.1.27/arch/powerpc/platforms/powermac/
H A Dcache.S66 /* Disp-flush L1. We have a weird problem here that I never
67 * totally figured out. On 750FX, using the ROM for the flush
68 * results in a non-working flush. We use that workaround for
117 1: /* disp-flush L2. The interesting thing here is that the L2 can be
119 * but that is probbaly fine. We disp-flush over 4Mb to be safe
222 /* Due to a bug with the HW flush on some CPU revs, we occasionally
223 * experience data corruption. I'm adding a displacement flush along
238 /* Now, flush the first 4MB of memory */
250 lis r3,0xfff0 /* read from ROM for displacement flush */
293 mtspr SPRN_L2CR,r0 /* set the hardware flush bit */
334 mtspr SPRN_L3CR,r0 /* set the hardware flush bit */
/linux-4.1.27/drivers/scsi/arm/
H A Dmsgqueue.h77 * Purpose : flush all messages from message queue
78 * Params : msgq - queue to flush
H A Dmsgqueue.c148 * Purpose : flush all messages from message queue
149 * Params : msgq - queue to flush
/linux-4.1.27/include/linux/
H A Dvm_event_item.h84 NR_TLB_REMOTE_FLUSH, /* cpu tried to flush others' tlbs */
85 NR_TLB_REMOTE_FLUSH_RECEIVED,/* cpu received ipi for flush */
H A Dzlib.h146 /* Allowed flush values; see deflate() and inflate() below for details */
217 extern int zlib_deflate (z_streamp strm, int flush);
222 forced to flush.
233 accordingly. This action is forced if the parameter flush is non zero.
234 Forcing flush frequently degrades the compression ratio, so this parameter
236 Some output may be provided even if flush is not set.
247 If the parameter flush is set to Z_SYNC_FLUSH, all pending output is
254 If flush is set to Z_FULL_FLUSH, all output is flushed as with
261 with the same value of the flush parameter and more output space (updated
262 avail_out), until the flush is complete (deflate returns with non-zero
265 If the parameter flush is set to Z_FINISH, pending input is processed,
288 consumed and all output has been produced (only when flush is set to
298 This function discards any unprocessed input and does not flush any
337 extern int zlib_inflate (z_streamp strm, int flush);
342 forced to flush.
355 about the flush parameter).
366 The flush parameter of inflate() can be Z_NO_FLUSH, Z_SYNC_FLUSH,
367 Z_FINISH, or Z_BLOCK. Z_SYNC_FLUSH requests that inflate() flush as much
389 (a single call of inflate), the parameter flush should be set to
400 first call. So the only effect of the flush parameter in this implementation
439 This function discards any unprocessed input and does not flush any
/linux-4.1.27/arch/mn10300/proc-mn103e010/include/proc/
H A Dcache.h35 * The size of range at which it becomes more economical to just flush the
36 * whole cache rather than trying to flush the specified range.
/linux-4.1.27/arch/mn10300/proc-mn2ws0050/include/proc/
H A Dcache.h41 * The size of range at which it becomes more economical to just flush the
42 * whole cache rather than trying to flush the specified range.
/linux-4.1.27/arch/sparc/kernel/
H A Dsetup_64.c208 __asm__ __volatile__("flush %0" : : "r" (addr + 0)); per_cpu_patch()
212 __asm__ __volatile__("flush %0" : : "r" (addr + 4)); per_cpu_patch()
216 __asm__ __volatile__("flush %0" : : "r" (addr + 8)); per_cpu_patch()
220 __asm__ __volatile__("flush %0" : : "r" (addr + 12)); per_cpu_patch()
234 __asm__ __volatile__("flush %0" : : "r" (addr + 0)); sun4v_patch_1insn_range()
248 __asm__ __volatile__("flush %0" : : "r" (addr + 0)); sun4v_patch_2insn_range()
252 __asm__ __volatile__("flush %0" : : "r" (addr + 4)); sun4v_patch_2insn_range()
266 __asm__ __volatile__("flush %0" : : "r" (addr + 0)); sun_m7_patch_2insn_range()
270 __asm__ __volatile__("flush %0" : : "r" (addr + 4)); sun_m7_patch_2insn_range()
307 __asm__ __volatile__("flush %0" popc_patch()
321 __asm__ __volatile__("flush %0" popc_patch()
340 __asm__ __volatile__("flush %0" pause_patch()
375 "flush", "stbar", "swap", "muldiv", "v9",
/linux-4.1.27/drivers/misc/sgi-gru/
H A Dgrulib.h72 * Structure used to pass TLB flush parameters to the driver
102 * Structure used to pass TLB flush parameters to the driver
111 * Structure used to pass TLB flush parameters to the driver
/linux-4.1.27/drivers/gpu/drm/
H A Ddrm_cache.c81 printk(KERN_ERR "Timed out waiting for cache flush.\n"); drm_clflush_pages()
120 printk(KERN_ERR "Timed out waiting for cache flush.\n"); drm_clflush_sg()
143 printk(KERN_ERR "Timed out waiting for cache flush.\n"); drm_clflush_virt_range()
/linux-4.1.27/arch/tile/kernel/
H A Dtlb.c28 * Note that we flush the L1I (for VM_EXEC pages) as well as the TLB
29 * so that when we are unmapping an executable page, we also flush it.
95 * Callers need to flush the L1I themselves if necessary, e.g. for
H A Drelocate_kernel_32.S81 * On TILEPro, we need to flush all tiles' caches, since we may
86 * because the hypervisor is going to do this flush again at that
87 * point, and we don't want that second flush to overwrite any memory.
197 * Issue a flush of the destination every 16 words to avoid
236 { flush r11 ; addi r11, r11, 4 }
H A Drelocate_kernel_64.S82 * On TILE-GX, we need to flush all tiles' caches, since we may
87 * because the hypervisor is going to do this flush again at that
88 * point, and we don't want that second flush to overwrite any memory.
203 * Issue a flush of the destination every 8 words to avoid
226 { flush r11 ; addi r11, r11, 8 }
H A Dsmp.c175 struct ipi_flush *flush = (struct ipi_flush *) info; ipi_flush_icache_range() local
176 __flush_icache_range(flush->start, flush->end); ipi_flush_icache_range()
181 struct ipi_flush flush = { start, end }; flush_icache_range() local
189 on_each_cpu(ipi_flush_icache_range, &flush, 1); flush_icache_range()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Drammcp77.c71 u64 dniso, hostnb, flush; mcp77_ram_init() local
79 flush = ((priv->base.size - (priv->poller_base + 0x40)) >> 5) - 1; mcp77_ram_init()
88 nv_wr32(pfb, 0x100c24, flush); mcp77_ram_init()
/linux-4.1.27/arch/nios2/boot/compressed/
H A Dhead.S51 /* flush the data cache after moving */
87 /* flush all data cache after decompressing */
93 /* flush all instruction cache */
/linux-4.1.27/net/atm/
H A Dlec_arpc.h40 unsigned long flush_tran_id; /* Transaction id in flush protocol */
81 * status and it is assumed that the flush
87 * that the flush protocol has completed. In
/linux-4.1.27/arch/sparc/mm/
H A Dultra.S42 flush %g3
74 flush %o4
106 flush %o4
130 flush %o3
141 flush %g6
144 flush %o1
163 flush %o0 + %g2
170 #error only page shift of 13 is supported by dcache flush
200 * better flush that too when necessary.
228 flush %o2
253 flush %o4
283 flush %o4
299 retl /* I-cache flush never needed on Cheetah, see callers. */
389 flush %o0
441 * %g7 address arg 2 (tlb range flush only)
680 1: flush %g7
H A Dhypersparc.S38 /* We expand the window flush to get maximum performance. */
123 /* Below our threshold, flush one page at a time. */
161 /* HyperSparc requires a valid mapping where we are about to flush
162 * in order to check for a physical tag match during the flush.
216 flush %o1
218 flush %o1 + 4
261 /* It was noted that at boot time a TLB flush all in a delay slot
H A Dtsunami.S43 flush %o1
45 flush %o1 + 4
/linux-4.1.27/arch/tile/include/asm/
H A Dcacheflush.h60 * and rely on the fact that we flush the icache on every context
62 * conservative and just do a global icache flush.
144 * true, we will do a more expensive flush involving additional loads
152 * it needs a way to flush as much of the CPU's caches as possible:
H A Dkgdb.h47 * Require cache flush for set/clear a software breakpoint or write memory.
/linux-4.1.27/include/trace/events/
H A Dtlb.h11 EM( TLB_FLUSH_ON_TASK_SWITCH, "flush on task switch" ) \
/linux-4.1.27/arch/sh/include/cpu-sh3/cpu/
H A Dmmu_context.h19 #define MMUCR_TI (1 << 2) /* TLB flush bit */
/linux-4.1.27/arch/nios2/include/asm/
H A Dtlb.h20 * we need to flush cache for the area to be unmapped.
H A Ddma-mapping.h27 * We just need to flush the caches here , but Nios2 flush __dma_sync_for_device()
30 case DMA_BIDIRECTIONAL: /* flush and invalidate */ __dma_sync_for_device()
/linux-4.1.27/arch/nios2/kernel/
H A Dsys_nios2.c20 /* sys_cacheflush -- flush the processor cache. */ sys_cacheflush()
/linux-4.1.27/arch/cris/arch-v10/mm/
H A Dtlb.c30 * of a flush causing.
70 D(printk("tlb: flush mm context %d (%p)\n", page_id, mm)); flush_tlb_mm()
76 * here we could also check the _PAGE_GLOBAL bit and NOT flush flush_tlb_mm()
106 D(printk("tlb: flush page %p in context %d (%p)\n", addr, page_id, mm)); flush_tlb_page()
/linux-4.1.27/arch/ia64/lib/
H A DMakefile11 flush.o ip_fast_csum.o do_csum.o \
/linux-4.1.27/arch/m32r/boot/compressed/
H A Dhead.S136 /* Cache flush */
141 /* Cache flush */
146 /* Cache flush */
151 #error "put your cache flush function, please"
/linux-4.1.27/arch/arm/mach-sa1100/include/mach/
H A Duncompress.h44 static inline void flush(void) flush() function
/linux-4.1.27/arch/arm/mach-w90x900/include/mach/
H A Duncompress.h40 static inline void flush(void) flush() function
/linux-4.1.27/arch/arm/mach-gemini/include/mach/
H A Duncompress.h33 static inline void flush(void) flush() function
/linux-4.1.27/arch/arm/mach-ixp4xx/include/mach/
H A Duncompress.h34 static void flush(void) flush() function
/linux-4.1.27/arch/sh/mm/
H A DMakefile10 cacheops-$(CONFIG_CPU_SH4) := cache-sh4.o flush-sh4.o
11 cacheops-$(CONFIG_CPU_SH5) := cache-sh5.o flush-sh4.o
H A Dcache-sh4.c26 * flushing. Anything exceeding this will simply flush the dcache in its
57 * Selectively flush d-cache then invalidate the i-cache. sh4_flush_icache_range()
272 * NOTE: We need to flush the _physical_ page entry.
274 * We need to flush for P1 too, which may contain aliases.
306 * @phys: P1 address to flush (has to match tags if addr has 'A' bit
308 * @exec_offset: set to 0x20000000 if flush has to be executed from P2
H A Dtlbflush_32.c51 if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */ local_flush_tlb_range()
86 if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */ local_flush_tlb_kernel_range()
H A Dtlbex_32.c68 * flush it in order to avoid potential TLB entry duplication. handle_tlbmiss()
/linux-4.1.27/arch/microblaze/kernel/
H A Dmisc.S37 mts rtlbhi, r0 /* flush: ensure V is clear */
59 mts rtlbhi, r0 /* flush: ensure V is clear */
/linux-4.1.27/arch/alpha/include/asm/
H A Dcacheflush.h23 /* We need to flush the kernel's icache after loading modules. The
38 /* We need to flush the userspace icache after setting breakpoints in
H A Dtlbflush.h115 /* Page-granular tlb flush. */
127 /* Flush a specified range of user mapping. On the Alpha we flush
/linux-4.1.27/fs/exofs/
H A Dfile.c40 /* exofs_file_fsync - flush the inode to disk
76 .flush = exofs_flush,
/linux-4.1.27/drivers/staging/speakup/
H A Dspeakup_dectlk.c55 static DECLARE_WAIT_QUEUE_HEAD(flush);
141 .flush = synth_flush,
187 wake_up_interruptible(&flush); read_buff_add()
230 prepare_to_wait(&flush, &wait, TASK_INTERRUPTIBLE); do_catch_up()
235 finish_wait(&flush, &wait); do_catch_up()
243 synth->flush(synth); do_catch_up()
/linux-4.1.27/arch/score/mm/
H A Dcache.c37 Just flush entire Dcache!!
39 the function will not flush the Icache.
68 * We could delay the flush for the !page_mapping case too. But that flush_dcache_page()
162 /*if we flush a range precisely , the processing may be very long.
164 we can flush the range in the page. Be careful, the range may be cross two
253 /* flush dcache to ram, and invalidate dcache lines. */ flush_dcache_range()
/linux-4.1.27/arch/arc/mm/
H A Dcache_arc700.c32 * -Off-by-one error when computing num_of_lines to flush
36 * -GCC can't generate ZOL for core cache flush loops.
40 * -In I-cache flush routine we used to chk for aliasing for every line INV.
45 * -Cache Line flush routines used to flush an extra line beyond end addr
58 * -Also added optimisation there, that for range > PAGE SIZE we flush the
146 * 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn)
148 * 3. Enable the Caches, setup default flush mode for D-Cache
276 * flush-n-inv is achieved by INV cmd but with IM=1 __before_dc_op()
289 if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ __after_dc_op()
310 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ __dc_entire_op()
537 /* Shortcut for bigger flush ranges. flush_icache_range()
598 /* wrapper to compile time eliminate alignment checks in flush loop */ __inv_icache_page()
715 * Explicit Cache flush request from user space via syscall
/linux-4.1.27/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_overlay.c71 SVGAEscapeVideoFlush flush; member in struct:vmw_escape_video_flush
85 fill_escape(&cmd->escape, sizeof(cmd->flush)); fill_flush()
86 cmd->flush.cmdType = SVGA_ESCAPE_VMWARE_VIDEO_FLUSH; fill_flush()
87 cmd->flush.streamId = stream_id; fill_flush()
101 struct vmw_escape_video_flush *flush; vmw_overlay_send_put() local
125 fifo_size = sizeof(*cmds) + sizeof(*flush) + sizeof(*items) * num_items; vmw_overlay_send_put()
133 flush = (struct vmw_escape_video_flush *)&items[num_items]; vmw_overlay_send_put()
172 fill_flush(flush, arg->stream_id); vmw_overlay_send_put()
192 struct vmw_escape_video_flush flush; vmw_overlay_send_stop() member in struct:__anon4620
214 fill_flush(&cmds->flush, stream_id); vmw_overlay_send_stop()
/linux-4.1.27/arch/parisc/kernel/
H A Dcache.c84 an invalid pfn and we don't need to flush the kernel dcache page. update_mmu_cache()
206 "Will flush I/D separately (could be optimized).\n"); parisc_cache_init()
309 * to flush one address here for them all to become coherent */ flush_dcache_page()
318 * mapping, so here we kill the mapping then flush the flush_dcache_page()
319 * page along a special flush only alias mapping. flush_dcache_page()
364 printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n", parisc_setup_cache_timing()
377 printk(KERN_INFO "Setting cache flush threshold to %lu kB\n", parisc_setup_cache_timing()
380 /* calculate TLB flush threshold */ parisc_setup_cache_timing()
396 printk(KERN_DEBUG "Whole TLB flush %lu cycles, flushing %lu bytes %lu cycles\n", parisc_setup_cache_timing()
405 printk(KERN_INFO "Setting TLB flush threshold to %lu kB\n", parisc_setup_cache_timing()
/linux-4.1.27/drivers/md/
H A Ddm-log-userspace-base.c49 * Mark and clear requests are held until a flush is issued
68 * Workqueue for flush of clear region requests.
75 * Combine userspace flush and mark requests for efficiency.
184 * If integrated_flush is defined, the kernel combines flush
333 /* flush workqueue */ userspace_dtr()
371 * Run planned flush earlier. userspace_postsuspend()
518 * Integrated flush failed.
551 * The flush happens in two stages. First, it sends all
559 * load on flush. Then the flush would have less in
601 * Send integrated flush request with mark_list as payload. userspace_flush()
610 * we schedule a flush in the future. userspace_flush()
616 * Cancel pending flush because we userspace_flush()
882 .flush = userspace_flush,
/linux-4.1.27/include/xen/interface/io/
H A Dblkif.h48 * Recognised if "feature-flush-cache" is present in backend xenbus
49 * info. A flush will ask the underlying storage hardware to flush its
50 * non-volatile caches as appropriate. The "feature-flush-cache" node
51 * contains a boolean indicating whether flush requests are likely to
52 * succeed or fail. Either way, a flush request may fail at any time
57 * "feature-flush-cache" node!
/linux-4.1.27/arch/s390/mm/
H A Dpgtable.c63 int flush; crst_table_upgrade() local
66 flush = 0; crst_table_upgrade()
92 flush = 1; crst_table_upgrade()
99 if (flush) crst_table_upgrade()
332 * Returns 1 if a TLB flush is required
337 int flush = 0; __gmap_unlink_by_vmaddr() local
342 flush = (*entry != _SEGMENT_ENTRY_INVALID); __gmap_unlink_by_vmaddr()
346 return flush; __gmap_unlink_by_vmaddr()
354 * Returns 1 if a TLB flush is required
376 int flush; gmap_unmap_segment() local
383 flush = 0; gmap_unmap_segment()
386 flush |= __gmap_unmap_by_gaddr(gmap, to + off); gmap_unmap_segment()
388 if (flush) gmap_unmap_segment()
407 int flush; gmap_map_segment() local
415 flush = 0; gmap_map_segment()
419 flush |= __gmap_unmap_by_gaddr(gmap, to + off); gmap_map_segment()
427 if (flush) gmap_map_segment()
487 int flush; gmap_unlink() local
490 flush = __gmap_unlink_by_vmaddr(gmap, vmaddr); gmap_unlink()
491 if (flush) gmap_unlink()
1337 /* No need to flush TLB pmdp_clear_flush_young()
/linux-4.1.27/drivers/i2c/busses/
H A Di2c-diolan-u2c.c161 static int diolan_write_cmd(struct i2c_diolan_u2c *dev, bool flush) diolan_write_cmd() argument
163 if (flush || dev->olen >= DIOLAN_FLUSH_LEN) diolan_write_cmd()
169 static int diolan_usb_cmd(struct i2c_diolan_u2c *dev, u8 command, bool flush) diolan_usb_cmd() argument
173 return diolan_write_cmd(dev, flush); diolan_usb_cmd()
178 bool flush) diolan_usb_cmd_data()
183 return diolan_write_cmd(dev, flush); diolan_usb_cmd_data()
188 u8 d2, bool flush) diolan_usb_cmd_data2()
194 return diolan_write_cmd(dev, flush); diolan_usb_cmd_data2()
219 dev_err(&dev->interface->dev, "Failed to flush input buffer\n"); diolan_flush_input()
177 diolan_usb_cmd_data(struct i2c_diolan_u2c *dev, u8 command, u8 data, bool flush) diolan_usb_cmd_data() argument
187 diolan_usb_cmd_data2(struct i2c_diolan_u2c *dev, u8 command, u8 d1, u8 d2, bool flush) diolan_usb_cmd_data2() argument
/linux-4.1.27/arch/x86/kvm/
H A Dmmu.h105 * mmu-lock. And the another case does not need to flush tlb until returning
108 * missed, so it can flush tlb out of mmu-lock.
111 * by another case which write-protects pages but without flush tlb
113 * it flush tlb if we try to write-protect a spte whose SPTE_MMU_WRITEABLE bit
118 * readonly, if that happens, we need to flush tlb. Fortunately,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
H A Dnv50.c89 nv_warn(priv, "flush timeout\n"); nv50_bar_flush()
101 nv_warn(priv, "flush timeout\n"); g84_bar_flush()
204 priv->base.flush = nv50_bar_flush; nv50_bar_ctor()
206 priv->base.flush = g84_bar_flush; nv50_bar_ctor()
242 nv_error(priv, "vm flush timeout\n"); nv50_bar_init()
/linux-4.1.27/arch/mips/pci/
H A Dpci-ar724x.c106 /* flush write */ ar724x_pci_local_write()
217 /* flush write */ ar724x_pci_write()
263 /* flush write */ ar724x_pci_irq_unmask()
285 /* flush write */ ar724x_pci_irq_mask()
292 /* flush write */ ar724x_pci_irq_mask()
/linux-4.1.27/include/asm-generic/
H A Dtlb.h33 * Architectures that use IPIs to flush TLBs will then automagically DTRT,
34 * since we unlink the page, flush TLBs, free the page. Since the disabling of
35 * IRQs delays the completion of the TLB flush we can never observe an already
103 * requires a complete flush of the tlb */
149 * case where we're doing a full MM flush. When we're doing a munmap,
/linux-4.1.27/drivers/net/ethernet/freescale/fs_enet/
H A Dmii-bitbang.c67 /* Read back to flush the write. */ mdio_dir()
86 /* Read back to flush the write. */ mdio()
99 /* Read back to flush the write. */ mdc()
/linux-4.1.27/arch/tile/lib/
H A Dusercopy_32.S99 * number of bytes to flush in r1.
108 1: { flush r0; addi r1, r1, -CHIP_FLUSH_STRIDE() }
119 * number of bytes to flush-invalidate in r1.
H A Dusercopy_64.S99 * number of bytes to flush in r1.
108 1: { flush r0; addi r1, r1, -CHIP_FLUSH_STRIDE() }
119 * number of bytes to flush-invalidate in r1.
H A Dcacheflush.c62 * a cache flush; otherwise, we could end up with data in the cache finv_buffer_remote()
74 * and request the home cache to flush and invalidate as well. finv_buffer_remote()
80 * all the flush-and-invalidate requests. This does not mean finv_buffer_remote()
154 * The finv's are guaranteed not to actually flush the data in finv_buffer_remote()
/linux-4.1.27/arch/microblaze/include/asm/
H A Dcacheflush.h33 /* struct cache, d=dcache, i=icache, fl = flush, iv = invalidate,
39 void (*ifl)(void); /* flush */
46 void (*dfl)(void); /* flush */
/linux-4.1.27/arch/arm64/kernel/
H A Dsuspend.c30 * Only flush the context that must be retrieved with the MMU __cpu_suspend_save()
31 * off. VA primitives ensure the flush is applied to all __cpu_suspend_save()
92 * page tables to prevent speculative TLB allocations, flush cpu_suspend()
/linux-4.1.27/arch/hexagon/include/asm/
H A Dcacheflush.h2 * Cache flush operations for the Hexagon architecture
32 * - flush_icache_range(start, end) flush a range of instructions
70 * mean that they aren't necessary. A brute-force, flush-everything
/linux-4.1.27/arch/m68k/kernel/
H A Dsys_m68k.c233 * cpush %dc : flush DC, remains valid (with our %cacr setup) cache_flush_060()
235 * cpush %bc : flush DC + invalidate IC cache_flush_060()
375 /* sys_cacheflush -- flush (part of) the processor cache. */
386 /* Only the superuser may explicitly flush the whole cache. */ sys_cacheflush()
439 * try to flush a few megs of memory. sys_cacheflush()
523 /* sys_cacheflush -- flush (part of) the processor cache. */
/linux-4.1.27/mm/
H A Dpercpu-vm.c114 * pcpu_pre_unmap_flush - flush cache prior to unmapping
121 * expensive, issue flush on the whole region at once rather than
149 * proper pre/post flush functions.
171 * pcpu_post_unmap_tlb_flush - flush TLB after unmapping
242 * pcpu_post_map_flush - flush cache after mapping
324 /* no need to flush tlb, vmalloc will handle it lazily */ pcpu_depopulate_chunk()
H A Dvmacache.c27 * flush will occur upon the next lookup. vmacache_flush_all()
35 * Only flush the vmacache pointers as the for_each_process_thread()
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Dplx9052.h63 #define PLX9052_CNTRL_PCI_R_W_FLUSH (1 << 15) /* read w/write flush mode */
64 #define PLX9052_CNTRL_PCI_R_NO_FLUSH (1 << 16) /* read no flush mode */
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/core/
H A Dramht.c54 bar->flush(bar); nvkm_ramht_insert()
73 bar->flush(bar); nvkm_ramht_remove()
/linux-4.1.27/arch/mips/txx9/jmr3927/
H A Dirq.c57 /* flush write buffer */ mask_irq_ioc()
67 /* flush write buffer */ unmask_irq_ioc()
/linux-4.1.27/arch/nios2/mm/
H A Dmmu_context.c64 * flush the tlb */ get_new_context()
73 * not need to flush the tlb here since it's always done above */ get_new_context()
/linux-4.1.27/arch/avr32/include/asm/
H A Dcacheflush.h86 * We do not need to flush anything in this case.
117 * flush with all configurations.
/linux-4.1.27/arch/avr32/mm/
H A Dcache.c19 * If you attempt to flush anything more than this, you need superuser
31 /* when first and/or last cachelines are shared, flush them invalidate_dcache_region()
/linux-4.1.27/arch/hexagon/mm/
H A Dvm_tlb.c34 * processors must be induced to flush the copies in their local TLBs,
88 * Like flush range, but without the check on the vma->vm_mm.
/linux-4.1.27/arch/m32r/kernel/
H A Dsmp.c175 /* TLB flush request Routines */
237 * Arguments: *mm - a pointer to the mm struct for flush TLB
281 * Arguments: *mm - a pointer to the mm struct for flush TLB
306 * va - virtual address for flush TLB
350 * Description: This routine requests other CPU to execute flush TLB.
359 * *mm - a pointer to the mm struct for flush TLB
361 * va - virtual address for flush TLB
435 * 2.Report flush TLB process was finished.
/linux-4.1.27/arch/arm/include/asm/
H A Dmmu_context.h53 * cpu_switch_mm() needs to flush the VIVT caches. To avoid check_and_switch_context()
73 * have some stateful cache flush implementations. Check finish_arch_post_lock_switch()
/linux-4.1.27/arch/arm/mach-lpc32xx/
H A Dserial.c95 * Force a flush of the RX FIFOs to work around a lpc32xx_serial_init()
111 /* Force a flush of the RX FIFOs to work around a HW bug */ lpc32xx_serial_init()
/linux-4.1.27/fs/f2fs/
H A Dtrace.c83 void f2fs_trace_ios(struct page *page, struct f2fs_io_info *fio, int flush) f2fs_trace_ios() argument
89 if (flush) { f2fs_trace_ios()
/linux-4.1.27/drivers/nfc/microread/
H A Di2c.c169 goto flush; microread_i2c_read()
175 goto flush; microread_i2c_read()
192 goto flush; microread_i2c_read()
202 flush: microread_i2c_read()
/linux-4.1.27/arch/x86/include/asm/
H A Dpgtable_32.h59 /* Clear a kernel PTE and flush it from the TLB */
/linux-4.1.27/arch/x86/kernel/
H A Damd_nb.c256 but I'm not sure if the hardware won't lose flush requests amd_flush_garts()
268 /* Make sure the hardware actually executed the flush*/ amd_flush_garts()
279 pr_notice("nothing to flush?\n"); amd_flush_garts()
293 pr_notice("Cannot initialize GART flush words, GART support disabled\n"); init_amd_nbs()
/linux-4.1.27/arch/x86/power/
H A Dhibernate_asm_32.S38 movl %cr3, %eax; # flush TLB
/linux-4.1.27/arch/xtensa/mm/
H A Dcache.c54 * With cache aliasing, we have to always flush the cache when pages are
182 * For now, flush the whole cache. FIXME??
196 * alias versions of the cache flush functions.
306 * (Note: a simply flush would be sufficient) copy_from_user_page()
/linux-4.1.27/arch/tile/include/hv/
H A Ddrv_srom_intf.h32 /** Write this offset to flush any pending writes. */
/linux-4.1.27/arch/um/drivers/
H A Dslip_common.h52 * Send an initial END character to flush out any slip_esc()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dgf100.c166 bar->flush(bar); gf100_vm_flush()
174 /* looks like maybe a "free flush slots" counter, the gf100_vm_flush()
185 /* wait for flush to be queued? */ gf100_vm_flush()
224 priv->base.flush = gf100_vm_flush; gf100_mmu_ctor()
/linux-4.1.27/fs/xfs/
H A Dxfs_dquot_item.h29 xfs_lsn_t qli_flush_lsn; /* lsn at last flush */

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