1/* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/dma-mapping.h> 18#include "ath9k.h" 19#include "ar9003_mac.h" 20 21#define SKB_CB_ATHBUF(__skb) (*((struct ath_rxbuf **)__skb->cb)) 22 23static inline bool ath9k_check_auto_sleep(struct ath_softc *sc) 24{ 25 return sc->ps_enabled && 26 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP); 27} 28 29/* 30 * Setup and link descriptors. 31 * 32 * 11N: we can no longer afford to self link the last descriptor. 33 * MAC acknowledges BA status as long as it copies frames to host 34 * buffer (or rx fifo). This can incorrectly acknowledge packets 35 * to a sender if last desc is self-linked. 36 */ 37static void ath_rx_buf_link(struct ath_softc *sc, struct ath_rxbuf *bf, 38 bool flush) 39{ 40 struct ath_hw *ah = sc->sc_ah; 41 struct ath_common *common = ath9k_hw_common(ah); 42 struct ath_desc *ds; 43 struct sk_buff *skb; 44 45 ds = bf->bf_desc; 46 ds->ds_link = 0; /* link to null */ 47 ds->ds_data = bf->bf_buf_addr; 48 49 /* virtual addr of the beginning of the buffer. */ 50 skb = bf->bf_mpdu; 51 BUG_ON(skb == NULL); 52 ds->ds_vdata = skb->data; 53 54 /* 55 * setup rx descriptors. The rx_bufsize here tells the hardware 56 * how much data it can DMA to us and that we are prepared 57 * to process 58 */ 59 ath9k_hw_setuprxdesc(ah, ds, 60 common->rx_bufsize, 61 0); 62 63 if (sc->rx.rxlink) 64 *sc->rx.rxlink = bf->bf_daddr; 65 else if (!flush) 66 ath9k_hw_putrxbuf(ah, bf->bf_daddr); 67 68 sc->rx.rxlink = &ds->ds_link; 69} 70 71static void ath_rx_buf_relink(struct ath_softc *sc, struct ath_rxbuf *bf, 72 bool flush) 73{ 74 if (sc->rx.buf_hold) 75 ath_rx_buf_link(sc, sc->rx.buf_hold, flush); 76 77 sc->rx.buf_hold = bf; 78} 79 80static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) 81{ 82 /* XXX block beacon interrupts */ 83 ath9k_hw_setantenna(sc->sc_ah, antenna); 84 sc->rx.defant = antenna; 85 sc->rx.rxotherant = 0; 86} 87 88static void ath_opmode_init(struct ath_softc *sc) 89{ 90 struct ath_hw *ah = sc->sc_ah; 91 struct ath_common *common = ath9k_hw_common(ah); 92 93 u32 rfilt, mfilt[2]; 94 95 /* configure rx filter */ 96 rfilt = ath_calcrxfilter(sc); 97 ath9k_hw_setrxfilter(ah, rfilt); 98 99 /* configure bssid mask */ 100 ath_hw_setbssidmask(common); 101 102 /* configure operational mode */ 103 ath9k_hw_setopmode(ah); 104 105 /* calculate and install multicast filter */ 106 mfilt[0] = mfilt[1] = ~0; 107 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); 108} 109 110static bool ath_rx_edma_buf_link(struct ath_softc *sc, 111 enum ath9k_rx_qtype qtype) 112{ 113 struct ath_hw *ah = sc->sc_ah; 114 struct ath_rx_edma *rx_edma; 115 struct sk_buff *skb; 116 struct ath_rxbuf *bf; 117 118 rx_edma = &sc->rx.rx_edma[qtype]; 119 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize) 120 return false; 121 122 bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list); 123 list_del_init(&bf->list); 124 125 skb = bf->bf_mpdu; 126 127 memset(skb->data, 0, ah->caps.rx_status_len); 128 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 129 ah->caps.rx_status_len, DMA_TO_DEVICE); 130 131 SKB_CB_ATHBUF(skb) = bf; 132 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype); 133 __skb_queue_tail(&rx_edma->rx_fifo, skb); 134 135 return true; 136} 137 138static void ath_rx_addbuffer_edma(struct ath_softc *sc, 139 enum ath9k_rx_qtype qtype) 140{ 141 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 142 struct ath_rxbuf *bf, *tbf; 143 144 if (list_empty(&sc->rx.rxbuf)) { 145 ath_dbg(common, QUEUE, "No free rx buf available\n"); 146 return; 147 } 148 149 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) 150 if (!ath_rx_edma_buf_link(sc, qtype)) 151 break; 152 153} 154 155static void ath_rx_remove_buffer(struct ath_softc *sc, 156 enum ath9k_rx_qtype qtype) 157{ 158 struct ath_rxbuf *bf; 159 struct ath_rx_edma *rx_edma; 160 struct sk_buff *skb; 161 162 rx_edma = &sc->rx.rx_edma[qtype]; 163 164 while ((skb = __skb_dequeue(&rx_edma->rx_fifo)) != NULL) { 165 bf = SKB_CB_ATHBUF(skb); 166 BUG_ON(!bf); 167 list_add_tail(&bf->list, &sc->rx.rxbuf); 168 } 169} 170 171static void ath_rx_edma_cleanup(struct ath_softc *sc) 172{ 173 struct ath_hw *ah = sc->sc_ah; 174 struct ath_common *common = ath9k_hw_common(ah); 175 struct ath_rxbuf *bf; 176 177 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); 178 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); 179 180 list_for_each_entry(bf, &sc->rx.rxbuf, list) { 181 if (bf->bf_mpdu) { 182 dma_unmap_single(sc->dev, bf->bf_buf_addr, 183 common->rx_bufsize, 184 DMA_BIDIRECTIONAL); 185 dev_kfree_skb_any(bf->bf_mpdu); 186 bf->bf_buf_addr = 0; 187 bf->bf_mpdu = NULL; 188 } 189 } 190} 191 192static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size) 193{ 194 __skb_queue_head_init(&rx_edma->rx_fifo); 195 rx_edma->rx_fifo_hwsize = size; 196} 197 198static int ath_rx_edma_init(struct ath_softc *sc, int nbufs) 199{ 200 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 201 struct ath_hw *ah = sc->sc_ah; 202 struct sk_buff *skb; 203 struct ath_rxbuf *bf; 204 int error = 0, i; 205 u32 size; 206 207 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 208 ah->caps.rx_status_len); 209 210 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP], 211 ah->caps.rx_lp_qdepth); 212 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP], 213 ah->caps.rx_hp_qdepth); 214 215 size = sizeof(struct ath_rxbuf) * nbufs; 216 bf = devm_kzalloc(sc->dev, size, GFP_KERNEL); 217 if (!bf) 218 return -ENOMEM; 219 220 INIT_LIST_HEAD(&sc->rx.rxbuf); 221 222 for (i = 0; i < nbufs; i++, bf++) { 223 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL); 224 if (!skb) { 225 error = -ENOMEM; 226 goto rx_init_fail; 227 } 228 229 memset(skb->data, 0, common->rx_bufsize); 230 bf->bf_mpdu = skb; 231 232 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 233 common->rx_bufsize, 234 DMA_BIDIRECTIONAL); 235 if (unlikely(dma_mapping_error(sc->dev, 236 bf->bf_buf_addr))) { 237 dev_kfree_skb_any(skb); 238 bf->bf_mpdu = NULL; 239 bf->bf_buf_addr = 0; 240 ath_err(common, 241 "dma_mapping_error() on RX init\n"); 242 error = -ENOMEM; 243 goto rx_init_fail; 244 } 245 246 list_add_tail(&bf->list, &sc->rx.rxbuf); 247 } 248 249 return 0; 250 251rx_init_fail: 252 ath_rx_edma_cleanup(sc); 253 return error; 254} 255 256static void ath_edma_start_recv(struct ath_softc *sc) 257{ 258 ath9k_hw_rxena(sc->sc_ah); 259 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP); 260 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP); 261 ath_opmode_init(sc); 262 ath9k_hw_startpcureceive(sc->sc_ah, sc->cur_chan->offchannel); 263} 264 265static void ath_edma_stop_recv(struct ath_softc *sc) 266{ 267 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); 268 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); 269} 270 271int ath_rx_init(struct ath_softc *sc, int nbufs) 272{ 273 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 274 struct sk_buff *skb; 275 struct ath_rxbuf *bf; 276 int error = 0; 277 278 spin_lock_init(&sc->sc_pcu_lock); 279 280 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 + 281 sc->sc_ah->caps.rx_status_len; 282 283 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 284 return ath_rx_edma_init(sc, nbufs); 285 286 ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n", 287 common->cachelsz, common->rx_bufsize); 288 289 /* Initialize rx descriptors */ 290 291 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, 292 "rx", nbufs, 1, 0); 293 if (error != 0) { 294 ath_err(common, 295 "failed to allocate rx descriptors: %d\n", 296 error); 297 goto err; 298 } 299 300 list_for_each_entry(bf, &sc->rx.rxbuf, list) { 301 skb = ath_rxbuf_alloc(common, common->rx_bufsize, 302 GFP_KERNEL); 303 if (skb == NULL) { 304 error = -ENOMEM; 305 goto err; 306 } 307 308 bf->bf_mpdu = skb; 309 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 310 common->rx_bufsize, 311 DMA_FROM_DEVICE); 312 if (unlikely(dma_mapping_error(sc->dev, 313 bf->bf_buf_addr))) { 314 dev_kfree_skb_any(skb); 315 bf->bf_mpdu = NULL; 316 bf->bf_buf_addr = 0; 317 ath_err(common, 318 "dma_mapping_error() on RX init\n"); 319 error = -ENOMEM; 320 goto err; 321 } 322 } 323 sc->rx.rxlink = NULL; 324err: 325 if (error) 326 ath_rx_cleanup(sc); 327 328 return error; 329} 330 331void ath_rx_cleanup(struct ath_softc *sc) 332{ 333 struct ath_hw *ah = sc->sc_ah; 334 struct ath_common *common = ath9k_hw_common(ah); 335 struct sk_buff *skb; 336 struct ath_rxbuf *bf; 337 338 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 339 ath_rx_edma_cleanup(sc); 340 return; 341 } 342 343 list_for_each_entry(bf, &sc->rx.rxbuf, list) { 344 skb = bf->bf_mpdu; 345 if (skb) { 346 dma_unmap_single(sc->dev, bf->bf_buf_addr, 347 common->rx_bufsize, 348 DMA_FROM_DEVICE); 349 dev_kfree_skb(skb); 350 bf->bf_buf_addr = 0; 351 bf->bf_mpdu = NULL; 352 } 353 } 354} 355 356/* 357 * Calculate the receive filter according to the 358 * operating mode and state: 359 * 360 * o always accept unicast, broadcast, and multicast traffic 361 * o maintain current state of phy error reception (the hal 362 * may enable phy error frames for noise immunity work) 363 * o probe request frames are accepted only when operating in 364 * hostap, adhoc, or monitor modes 365 * o enable promiscuous mode according to the interface state 366 * o accept beacons: 367 * - when operating in adhoc mode so the 802.11 layer creates 368 * node table entries for peers, 369 * - when operating in station mode for collecting rssi data when 370 * the station is otherwise quiet, or 371 * - when operating as a repeater so we see repeater-sta beacons 372 * - when scanning 373 */ 374 375u32 ath_calcrxfilter(struct ath_softc *sc) 376{ 377 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 378 u32 rfilt; 379 380 if (config_enabled(CONFIG_ATH9K_TX99)) 381 return 0; 382 383 rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST 384 | ATH9K_RX_FILTER_MCAST; 385 386 /* if operating on a DFS channel, enable radar pulse detection */ 387 if (sc->hw->conf.radar_enabled) 388 rfilt |= ATH9K_RX_FILTER_PHYRADAR | ATH9K_RX_FILTER_PHYERR; 389 390 spin_lock_bh(&sc->chan_lock); 391 392 if (sc->cur_chan->rxfilter & FIF_PROBE_REQ) 393 rfilt |= ATH9K_RX_FILTER_PROBEREQ; 394 395 /* 396 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station 397 * mode interface or when in monitor mode. AP mode does not need this 398 * since it receives all in-BSS frames anyway. 399 */ 400 if (sc->sc_ah->is_monitoring) 401 rfilt |= ATH9K_RX_FILTER_PROM; 402 403 if ((sc->cur_chan->rxfilter & FIF_CONTROL) || 404 sc->sc_ah->dynack.enabled) 405 rfilt |= ATH9K_RX_FILTER_CONTROL; 406 407 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && 408 (sc->cur_chan->nvifs <= 1) && 409 !(sc->cur_chan->rxfilter & FIF_BCN_PRBRESP_PROMISC)) 410 rfilt |= ATH9K_RX_FILTER_MYBEACON; 411 else 412 rfilt |= ATH9K_RX_FILTER_BEACON; 413 414 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || 415 (sc->cur_chan->rxfilter & FIF_PSPOLL)) 416 rfilt |= ATH9K_RX_FILTER_PSPOLL; 417 418 if (sc->cur_chandef.width != NL80211_CHAN_WIDTH_20_NOHT) 419 rfilt |= ATH9K_RX_FILTER_COMP_BAR; 420 421 if (sc->cur_chan->nvifs > 1 || (sc->cur_chan->rxfilter & FIF_OTHER_BSS)) { 422 /* This is needed for older chips */ 423 if (sc->sc_ah->hw_version.macVersion <= AR_SREV_VERSION_9160) 424 rfilt |= ATH9K_RX_FILTER_PROM; 425 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; 426 } 427 428 if (AR_SREV_9550(sc->sc_ah) || AR_SREV_9531(sc->sc_ah) || 429 AR_SREV_9561(sc->sc_ah)) 430 rfilt |= ATH9K_RX_FILTER_4ADDRESS; 431 432 if (ath9k_is_chanctx_enabled() && 433 test_bit(ATH_OP_SCANNING, &common->op_flags)) 434 rfilt |= ATH9K_RX_FILTER_BEACON; 435 436 spin_unlock_bh(&sc->chan_lock); 437 438 return rfilt; 439 440} 441 442void ath_startrecv(struct ath_softc *sc) 443{ 444 struct ath_hw *ah = sc->sc_ah; 445 struct ath_rxbuf *bf, *tbf; 446 447 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 448 ath_edma_start_recv(sc); 449 return; 450 } 451 452 if (list_empty(&sc->rx.rxbuf)) 453 goto start_recv; 454 455 sc->rx.buf_hold = NULL; 456 sc->rx.rxlink = NULL; 457 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { 458 ath_rx_buf_link(sc, bf, false); 459 } 460 461 /* We could have deleted elements so the list may be empty now */ 462 if (list_empty(&sc->rx.rxbuf)) 463 goto start_recv; 464 465 bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list); 466 ath9k_hw_putrxbuf(ah, bf->bf_daddr); 467 ath9k_hw_rxena(ah); 468 469start_recv: 470 ath_opmode_init(sc); 471 ath9k_hw_startpcureceive(ah, sc->cur_chan->offchannel); 472} 473 474static void ath_flushrecv(struct ath_softc *sc) 475{ 476 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 477 ath_rx_tasklet(sc, 1, true); 478 ath_rx_tasklet(sc, 1, false); 479} 480 481bool ath_stoprecv(struct ath_softc *sc) 482{ 483 struct ath_hw *ah = sc->sc_ah; 484 bool stopped, reset = false; 485 486 ath9k_hw_abortpcurecv(ah); 487 ath9k_hw_setrxfilter(ah, 0); 488 stopped = ath9k_hw_stopdmarecv(ah, &reset); 489 490 ath_flushrecv(sc); 491 492 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 493 ath_edma_stop_recv(sc); 494 else 495 sc->rx.rxlink = NULL; 496 497 if (!(ah->ah_flags & AH_UNPLUGGED) && 498 unlikely(!stopped)) { 499 ath_err(ath9k_hw_common(sc->sc_ah), 500 "Could not stop RX, we could be " 501 "confusing the DMA engine when we start RX up\n"); 502 ATH_DBG_WARN_ON_ONCE(!stopped); 503 } 504 return stopped && !reset; 505} 506 507static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb) 508{ 509 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */ 510 struct ieee80211_mgmt *mgmt; 511 u8 *pos, *end, id, elen; 512 struct ieee80211_tim_ie *tim; 513 514 mgmt = (struct ieee80211_mgmt *)skb->data; 515 pos = mgmt->u.beacon.variable; 516 end = skb->data + skb->len; 517 518 while (pos + 2 < end) { 519 id = *pos++; 520 elen = *pos++; 521 if (pos + elen > end) 522 break; 523 524 if (id == WLAN_EID_TIM) { 525 if (elen < sizeof(*tim)) 526 break; 527 tim = (struct ieee80211_tim_ie *) pos; 528 if (tim->dtim_count != 0) 529 break; 530 return tim->bitmap_ctrl & 0x01; 531 } 532 533 pos += elen; 534 } 535 536 return false; 537} 538 539static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) 540{ 541 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 542 bool skip_beacon = false; 543 544 if (skb->len < 24 + 8 + 2 + 2) 545 return; 546 547 sc->ps_flags &= ~PS_WAIT_FOR_BEACON; 548 549 if (sc->ps_flags & PS_BEACON_SYNC) { 550 sc->ps_flags &= ~PS_BEACON_SYNC; 551 ath_dbg(common, PS, 552 "Reconfigure beacon timers based on synchronized timestamp\n"); 553 554#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 555 if (ath9k_is_chanctx_enabled()) { 556 if (sc->cur_chan == &sc->offchannel.chan) 557 skip_beacon = true; 558 } 559#endif 560 561 if (!skip_beacon && 562 !(WARN_ON_ONCE(sc->cur_chan->beacon.beacon_interval == 0))) 563 ath9k_set_beacon(sc); 564 565 ath9k_p2p_beacon_sync(sc); 566 } 567 568 if (ath_beacon_dtim_pending_cab(skb)) { 569 /* 570 * Remain awake waiting for buffered broadcast/multicast 571 * frames. If the last broadcast/multicast frame is not 572 * received properly, the next beacon frame will work as 573 * a backup trigger for returning into NETWORK SLEEP state, 574 * so we are waiting for it as well. 575 */ 576 ath_dbg(common, PS, 577 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n"); 578 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON; 579 return; 580 } 581 582 if (sc->ps_flags & PS_WAIT_FOR_CAB) { 583 /* 584 * This can happen if a broadcast frame is dropped or the AP 585 * fails to send a frame indicating that all CAB frames have 586 * been delivered. 587 */ 588 sc->ps_flags &= ~PS_WAIT_FOR_CAB; 589 ath_dbg(common, PS, "PS wait for CAB frames timed out\n"); 590 } 591} 592 593static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon) 594{ 595 struct ieee80211_hdr *hdr; 596 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 597 598 hdr = (struct ieee80211_hdr *)skb->data; 599 600 /* Process Beacon and CAB receive in PS state */ 601 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc)) 602 && mybeacon) { 603 ath_rx_ps_beacon(sc, skb); 604 } else if ((sc->ps_flags & PS_WAIT_FOR_CAB) && 605 (ieee80211_is_data(hdr->frame_control) || 606 ieee80211_is_action(hdr->frame_control)) && 607 is_multicast_ether_addr(hdr->addr1) && 608 !ieee80211_has_moredata(hdr->frame_control)) { 609 /* 610 * No more broadcast/multicast frames to be received at this 611 * point. 612 */ 613 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON); 614 ath_dbg(common, PS, 615 "All PS CAB frames received, back to sleep\n"); 616 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) && 617 !is_multicast_ether_addr(hdr->addr1) && 618 !ieee80211_has_morefrags(hdr->frame_control)) { 619 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA; 620 ath_dbg(common, PS, 621 "Going back to sleep after having received PS-Poll data (0x%lx)\n", 622 sc->ps_flags & (PS_WAIT_FOR_BEACON | 623 PS_WAIT_FOR_CAB | 624 PS_WAIT_FOR_PSPOLL_DATA | 625 PS_WAIT_FOR_TX_ACK)); 626 } 627} 628 629static bool ath_edma_get_buffers(struct ath_softc *sc, 630 enum ath9k_rx_qtype qtype, 631 struct ath_rx_status *rs, 632 struct ath_rxbuf **dest) 633{ 634 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype]; 635 struct ath_hw *ah = sc->sc_ah; 636 struct ath_common *common = ath9k_hw_common(ah); 637 struct sk_buff *skb; 638 struct ath_rxbuf *bf; 639 int ret; 640 641 skb = skb_peek(&rx_edma->rx_fifo); 642 if (!skb) 643 return false; 644 645 bf = SKB_CB_ATHBUF(skb); 646 BUG_ON(!bf); 647 648 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, 649 common->rx_bufsize, DMA_FROM_DEVICE); 650 651 ret = ath9k_hw_process_rxdesc_edma(ah, rs, skb->data); 652 if (ret == -EINPROGRESS) { 653 /*let device gain the buffer again*/ 654 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 655 common->rx_bufsize, DMA_FROM_DEVICE); 656 return false; 657 } 658 659 __skb_unlink(skb, &rx_edma->rx_fifo); 660 if (ret == -EINVAL) { 661 /* corrupt descriptor, skip this one and the following one */ 662 list_add_tail(&bf->list, &sc->rx.rxbuf); 663 ath_rx_edma_buf_link(sc, qtype); 664 665 skb = skb_peek(&rx_edma->rx_fifo); 666 if (skb) { 667 bf = SKB_CB_ATHBUF(skb); 668 BUG_ON(!bf); 669 670 __skb_unlink(skb, &rx_edma->rx_fifo); 671 list_add_tail(&bf->list, &sc->rx.rxbuf); 672 ath_rx_edma_buf_link(sc, qtype); 673 } 674 675 bf = NULL; 676 } 677 678 *dest = bf; 679 return true; 680} 681 682static struct ath_rxbuf *ath_edma_get_next_rx_buf(struct ath_softc *sc, 683 struct ath_rx_status *rs, 684 enum ath9k_rx_qtype qtype) 685{ 686 struct ath_rxbuf *bf = NULL; 687 688 while (ath_edma_get_buffers(sc, qtype, rs, &bf)) { 689 if (!bf) 690 continue; 691 692 return bf; 693 } 694 return NULL; 695} 696 697static struct ath_rxbuf *ath_get_next_rx_buf(struct ath_softc *sc, 698 struct ath_rx_status *rs) 699{ 700 struct ath_hw *ah = sc->sc_ah; 701 struct ath_common *common = ath9k_hw_common(ah); 702 struct ath_desc *ds; 703 struct ath_rxbuf *bf; 704 int ret; 705 706 if (list_empty(&sc->rx.rxbuf)) { 707 sc->rx.rxlink = NULL; 708 return NULL; 709 } 710 711 bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list); 712 if (bf == sc->rx.buf_hold) 713 return NULL; 714 715 ds = bf->bf_desc; 716 717 /* 718 * Must provide the virtual address of the current 719 * descriptor, the physical address, and the virtual 720 * address of the next descriptor in the h/w chain. 721 * This allows the HAL to look ahead to see if the 722 * hardware is done with a descriptor by checking the 723 * done bit in the following descriptor and the address 724 * of the current descriptor the DMA engine is working 725 * on. All this is necessary because of our use of 726 * a self-linked list to avoid rx overruns. 727 */ 728 ret = ath9k_hw_rxprocdesc(ah, ds, rs); 729 if (ret == -EINPROGRESS) { 730 struct ath_rx_status trs; 731 struct ath_rxbuf *tbf; 732 struct ath_desc *tds; 733 734 memset(&trs, 0, sizeof(trs)); 735 if (list_is_last(&bf->list, &sc->rx.rxbuf)) { 736 sc->rx.rxlink = NULL; 737 return NULL; 738 } 739 740 tbf = list_entry(bf->list.next, struct ath_rxbuf, list); 741 742 /* 743 * On some hardware the descriptor status words could 744 * get corrupted, including the done bit. Because of 745 * this, check if the next descriptor's done bit is 746 * set or not. 747 * 748 * If the next descriptor's done bit is set, the current 749 * descriptor has been corrupted. Force s/w to discard 750 * this descriptor and continue... 751 */ 752 753 tds = tbf->bf_desc; 754 ret = ath9k_hw_rxprocdesc(ah, tds, &trs); 755 if (ret == -EINPROGRESS) 756 return NULL; 757 758 /* 759 * Re-check previous descriptor, in case it has been filled 760 * in the mean time. 761 */ 762 ret = ath9k_hw_rxprocdesc(ah, ds, rs); 763 if (ret == -EINPROGRESS) { 764 /* 765 * mark descriptor as zero-length and set the 'more' 766 * flag to ensure that both buffers get discarded 767 */ 768 rs->rs_datalen = 0; 769 rs->rs_more = true; 770 } 771 } 772 773 list_del(&bf->list); 774 if (!bf->bf_mpdu) 775 return bf; 776 777 /* 778 * Synchronize the DMA transfer with CPU before 779 * 1. accessing the frame 780 * 2. requeueing the same buffer to h/w 781 */ 782 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, 783 common->rx_bufsize, 784 DMA_FROM_DEVICE); 785 786 return bf; 787} 788 789static void ath9k_process_tsf(struct ath_rx_status *rs, 790 struct ieee80211_rx_status *rxs, 791 u64 tsf) 792{ 793 u32 tsf_lower = tsf & 0xffffffff; 794 795 rxs->mactime = (tsf & ~0xffffffffULL) | rs->rs_tstamp; 796 if (rs->rs_tstamp > tsf_lower && 797 unlikely(rs->rs_tstamp - tsf_lower > 0x10000000)) 798 rxs->mactime -= 0x100000000ULL; 799 800 if (rs->rs_tstamp < tsf_lower && 801 unlikely(tsf_lower - rs->rs_tstamp > 0x10000000)) 802 rxs->mactime += 0x100000000ULL; 803} 804 805/* 806 * For Decrypt or Demic errors, we only mark packet status here and always push 807 * up the frame up to let mac80211 handle the actual error case, be it no 808 * decryption key or real decryption error. This let us keep statistics there. 809 */ 810static int ath9k_rx_skb_preprocess(struct ath_softc *sc, 811 struct sk_buff *skb, 812 struct ath_rx_status *rx_stats, 813 struct ieee80211_rx_status *rx_status, 814 bool *decrypt_error, u64 tsf) 815{ 816 struct ieee80211_hw *hw = sc->hw; 817 struct ath_hw *ah = sc->sc_ah; 818 struct ath_common *common = ath9k_hw_common(ah); 819 struct ieee80211_hdr *hdr; 820 bool discard_current = sc->rx.discard_next; 821 822 /* 823 * Discard corrupt descriptors which are marked in 824 * ath_get_next_rx_buf(). 825 */ 826 if (discard_current) 827 goto corrupt; 828 829 sc->rx.discard_next = false; 830 831 /* 832 * Discard zero-length packets. 833 */ 834 if (!rx_stats->rs_datalen) { 835 RX_STAT_INC(rx_len_err); 836 goto corrupt; 837 } 838 839 /* 840 * rs_status follows rs_datalen so if rs_datalen is too large 841 * we can take a hint that hardware corrupted it, so ignore 842 * those frames. 843 */ 844 if (rx_stats->rs_datalen > (common->rx_bufsize - ah->caps.rx_status_len)) { 845 RX_STAT_INC(rx_len_err); 846 goto corrupt; 847 } 848 849 /* Only use status info from the last fragment */ 850 if (rx_stats->rs_more) 851 return 0; 852 853 /* 854 * Return immediately if the RX descriptor has been marked 855 * as corrupt based on the various error bits. 856 * 857 * This is different from the other corrupt descriptor 858 * condition handled above. 859 */ 860 if (rx_stats->rs_status & ATH9K_RXERR_CORRUPT_DESC) 861 goto corrupt; 862 863 hdr = (struct ieee80211_hdr *) (skb->data + ah->caps.rx_status_len); 864 865 ath9k_process_tsf(rx_stats, rx_status, tsf); 866 ath_debug_stat_rx(sc, rx_stats); 867 868 /* 869 * Process PHY errors and return so that the packet 870 * can be dropped. 871 */ 872 if (rx_stats->rs_status & ATH9K_RXERR_PHY) { 873 ath9k_dfs_process_phyerr(sc, hdr, rx_stats, rx_status->mactime); 874 if (ath_cmn_process_fft(&sc->spec_priv, hdr, rx_stats, rx_status->mactime)) 875 RX_STAT_INC(rx_spectral); 876 877 return -EINVAL; 878 } 879 880 /* 881 * everything but the rate is checked here, the rate check is done 882 * separately to avoid doing two lookups for a rate for each frame. 883 */ 884 spin_lock_bh(&sc->chan_lock); 885 if (!ath9k_cmn_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error, 886 sc->cur_chan->rxfilter)) { 887 spin_unlock_bh(&sc->chan_lock); 888 return -EINVAL; 889 } 890 spin_unlock_bh(&sc->chan_lock); 891 892 if (ath_is_mybeacon(common, hdr)) { 893 RX_STAT_INC(rx_beacons); 894 rx_stats->is_mybeacon = true; 895 } 896 897 /* 898 * This shouldn't happen, but have a safety check anyway. 899 */ 900 if (WARN_ON(!ah->curchan)) 901 return -EINVAL; 902 903 if (ath9k_cmn_process_rate(common, hw, rx_stats, rx_status)) { 904 /* 905 * No valid hardware bitrate found -- we should not get here 906 * because hardware has already validated this frame as OK. 907 */ 908 ath_dbg(common, ANY, "unsupported hw bitrate detected 0x%02x using 1 Mbit\n", 909 rx_stats->rs_rate); 910 RX_STAT_INC(rx_rate_err); 911 return -EINVAL; 912 } 913 914 if (ath9k_is_chanctx_enabled()) { 915 if (rx_stats->is_mybeacon) 916 ath_chanctx_beacon_recv_ev(sc, 917 ATH_CHANCTX_EVENT_BEACON_RECEIVED); 918 } 919 920 ath9k_cmn_process_rssi(common, hw, rx_stats, rx_status); 921 922 rx_status->band = ah->curchan->chan->band; 923 rx_status->freq = ah->curchan->chan->center_freq; 924 rx_status->antenna = rx_stats->rs_antenna; 925 rx_status->flag |= RX_FLAG_MACTIME_END; 926 927#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 928 if (ieee80211_is_data_present(hdr->frame_control) && 929 !ieee80211_is_qos_nullfunc(hdr->frame_control)) 930 sc->rx.num_pkts++; 931#endif 932 933 return 0; 934 935corrupt: 936 sc->rx.discard_next = rx_stats->rs_more; 937 return -EINVAL; 938} 939 940/* 941 * Run the LNA combining algorithm only in these cases: 942 * 943 * Standalone WLAN cards with both LNA/Antenna diversity 944 * enabled in the EEPROM. 945 * 946 * WLAN+BT cards which are in the supported card list 947 * in ath_pci_id_table and the user has loaded the 948 * driver with "bt_ant_diversity" set to true. 949 */ 950static void ath9k_antenna_check(struct ath_softc *sc, 951 struct ath_rx_status *rs) 952{ 953 struct ath_hw *ah = sc->sc_ah; 954 struct ath9k_hw_capabilities *pCap = &ah->caps; 955 struct ath_common *common = ath9k_hw_common(ah); 956 957 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)) 958 return; 959 960 /* 961 * Change the default rx antenna if rx diversity 962 * chooses the other antenna 3 times in a row. 963 */ 964 if (sc->rx.defant != rs->rs_antenna) { 965 if (++sc->rx.rxotherant >= 3) 966 ath_setdefantenna(sc, rs->rs_antenna); 967 } else { 968 sc->rx.rxotherant = 0; 969 } 970 971 if (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV) { 972 if (common->bt_ant_diversity) 973 ath_ant_comb_scan(sc, rs); 974 } else { 975 ath_ant_comb_scan(sc, rs); 976 } 977} 978 979static void ath9k_apply_ampdu_details(struct ath_softc *sc, 980 struct ath_rx_status *rs, struct ieee80211_rx_status *rxs) 981{ 982 if (rs->rs_isaggr) { 983 rxs->flag |= RX_FLAG_AMPDU_DETAILS | RX_FLAG_AMPDU_LAST_KNOWN; 984 985 rxs->ampdu_reference = sc->rx.ampdu_ref; 986 987 if (!rs->rs_moreaggr) { 988 rxs->flag |= RX_FLAG_AMPDU_IS_LAST; 989 sc->rx.ampdu_ref++; 990 } 991 992 if (rs->rs_flags & ATH9K_RX_DELIM_CRC_PRE) 993 rxs->flag |= RX_FLAG_AMPDU_DELIM_CRC_ERROR; 994 } 995} 996 997int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp) 998{ 999 struct ath_rxbuf *bf; 1000 struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb; 1001 struct ieee80211_rx_status *rxs; 1002 struct ath_hw *ah = sc->sc_ah; 1003 struct ath_common *common = ath9k_hw_common(ah); 1004 struct ieee80211_hw *hw = sc->hw; 1005 int retval; 1006 struct ath_rx_status rs; 1007 enum ath9k_rx_qtype qtype; 1008 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1009 int dma_type; 1010 u64 tsf = 0; 1011 unsigned long flags; 1012 dma_addr_t new_buf_addr; 1013 unsigned int budget = 512; 1014 struct ieee80211_hdr *hdr; 1015 1016 if (edma) 1017 dma_type = DMA_BIDIRECTIONAL; 1018 else 1019 dma_type = DMA_FROM_DEVICE; 1020 1021 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP; 1022 1023 tsf = ath9k_hw_gettsf64(ah); 1024 1025 do { 1026 bool decrypt_error = false; 1027 1028 memset(&rs, 0, sizeof(rs)); 1029 if (edma) 1030 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype); 1031 else 1032 bf = ath_get_next_rx_buf(sc, &rs); 1033 1034 if (!bf) 1035 break; 1036 1037 skb = bf->bf_mpdu; 1038 if (!skb) 1039 continue; 1040 1041 /* 1042 * Take frame header from the first fragment and RX status from 1043 * the last one. 1044 */ 1045 if (sc->rx.frag) 1046 hdr_skb = sc->rx.frag; 1047 else 1048 hdr_skb = skb; 1049 1050 rxs = IEEE80211_SKB_RXCB(hdr_skb); 1051 memset(rxs, 0, sizeof(struct ieee80211_rx_status)); 1052 1053 retval = ath9k_rx_skb_preprocess(sc, hdr_skb, &rs, rxs, 1054 &decrypt_error, tsf); 1055 if (retval) 1056 goto requeue_drop_frag; 1057 1058 /* Ensure we always have an skb to requeue once we are done 1059 * processing the current buffer's skb */ 1060 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC); 1061 1062 /* If there is no memory we ignore the current RX'd frame, 1063 * tell hardware it can give us a new frame using the old 1064 * skb and put it at the tail of the sc->rx.rxbuf list for 1065 * processing. */ 1066 if (!requeue_skb) { 1067 RX_STAT_INC(rx_oom_err); 1068 goto requeue_drop_frag; 1069 } 1070 1071 /* We will now give hardware our shiny new allocated skb */ 1072 new_buf_addr = dma_map_single(sc->dev, requeue_skb->data, 1073 common->rx_bufsize, dma_type); 1074 if (unlikely(dma_mapping_error(sc->dev, new_buf_addr))) { 1075 dev_kfree_skb_any(requeue_skb); 1076 goto requeue_drop_frag; 1077 } 1078 1079 /* Unmap the frame */ 1080 dma_unmap_single(sc->dev, bf->bf_buf_addr, 1081 common->rx_bufsize, dma_type); 1082 1083 bf->bf_mpdu = requeue_skb; 1084 bf->bf_buf_addr = new_buf_addr; 1085 1086 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len); 1087 if (ah->caps.rx_status_len) 1088 skb_pull(skb, ah->caps.rx_status_len); 1089 1090 if (!rs.rs_more) 1091 ath9k_cmn_rx_skb_postprocess(common, hdr_skb, &rs, 1092 rxs, decrypt_error); 1093 1094 if (rs.rs_more) { 1095 RX_STAT_INC(rx_frags); 1096 /* 1097 * rs_more indicates chained descriptors which can be 1098 * used to link buffers together for a sort of 1099 * scatter-gather operation. 1100 */ 1101 if (sc->rx.frag) { 1102 /* too many fragments - cannot handle frame */ 1103 dev_kfree_skb_any(sc->rx.frag); 1104 dev_kfree_skb_any(skb); 1105 RX_STAT_INC(rx_too_many_frags_err); 1106 skb = NULL; 1107 } 1108 sc->rx.frag = skb; 1109 goto requeue; 1110 } 1111 1112 if (sc->rx.frag) { 1113 int space = skb->len - skb_tailroom(hdr_skb); 1114 1115 if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) { 1116 dev_kfree_skb(skb); 1117 RX_STAT_INC(rx_oom_err); 1118 goto requeue_drop_frag; 1119 } 1120 1121 sc->rx.frag = NULL; 1122 1123 skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len), 1124 skb->len); 1125 dev_kfree_skb_any(skb); 1126 skb = hdr_skb; 1127 } 1128 1129 if (rxs->flag & RX_FLAG_MMIC_STRIPPED) 1130 skb_trim(skb, skb->len - 8); 1131 1132 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1133 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON | 1134 PS_WAIT_FOR_CAB | 1135 PS_WAIT_FOR_PSPOLL_DATA)) || 1136 ath9k_check_auto_sleep(sc)) 1137 ath_rx_ps(sc, skb, rs.is_mybeacon); 1138 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1139 1140 ath9k_antenna_check(sc, &rs); 1141 ath9k_apply_ampdu_details(sc, &rs, rxs); 1142 ath_debug_rate_stats(sc, &rs, skb); 1143 1144 hdr = (struct ieee80211_hdr *)skb->data; 1145 if (ieee80211_is_ack(hdr->frame_control)) 1146 ath_dynack_sample_ack_ts(sc->sc_ah, skb, rs.rs_tstamp); 1147 1148 ieee80211_rx(hw, skb); 1149 1150requeue_drop_frag: 1151 if (sc->rx.frag) { 1152 dev_kfree_skb_any(sc->rx.frag); 1153 sc->rx.frag = NULL; 1154 } 1155requeue: 1156 list_add_tail(&bf->list, &sc->rx.rxbuf); 1157 1158 if (!edma) { 1159 ath_rx_buf_relink(sc, bf, flush); 1160 if (!flush) 1161 ath9k_hw_rxena(ah); 1162 } else if (!flush) { 1163 ath_rx_edma_buf_link(sc, qtype); 1164 } 1165 1166 if (!budget--) 1167 break; 1168 } while (1); 1169 1170 if (!(ah->imask & ATH9K_INT_RXEOL)) { 1171 ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 1172 ath9k_hw_set_interrupts(ah); 1173 } 1174 1175 return 0; 1176} 1177