Searched refs:Memory (Results 1 - 200 of 1305) sorted by relevance

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/linux-4.1.27/arch/blackfin/mach-bf518/include/mach/
H A Dmem_map.h15 /* Async Memory Banks */
25 /* Boot ROM Memory */
30 /* Level 1 Memory */
32 /* Memory Map for ADSP-BF518/6/4/2 processors */
H A Danomaly.h35 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
41 /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
67 /* Incorrect L1 Instruction Bank B Memory Map Location */
75 /* False Hardware Error when RETI Points to Invalid Memory */
93 /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
/linux-4.1.27/arch/sparc/include/asm/
H A Dchmctrl.h5 #define CHMCTRL_TCTRL1 0x00 /* Memory Timing Control I */
6 #define CHMCTRL_TCTRL2 0x08 /* Memory Timing Control II */
7 #define CHMCTRL_TCTRL3 0x38 /* Memory Timing Control III */
8 #define CHMCTRL_TCTRL4 0x40 /* Memory Timing Control IV */
9 #define CHMCTRL_DECODE1 0x10 /* Memory Address Decode I */
10 #define CHMCTRL_DECODE2 0x18 /* Memory Address Decode II */
11 #define CHMCTRL_DECODE3 0x20 /* Memory Address Decode III */
12 #define CHMCTRL_DECODE4 0x28 /* Memory Address Decode IV */
13 #define CHMCTRL_MACTRL 0x30 /* Memory Address Control */
15 /* Memory Timing Control I */
47 /* Memory Timing Control II */
73 /* Memory Timing Control III */
105 /* Memory Timing Control IV */
H A Dpci_32.h42 * On LEON PCI Memory space is mapped 1:1 with physical address space.
H A Diommu_32.h37 volatile unsigned long mfsr; /* Memory-fault status register */
38 volatile unsigned long mfar; /* Memory-fault physical address */
84 #define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */
H A Dtsunami.h22 * MV: Memory View bit
/linux-4.1.27/arch/sh/drivers/pci/
H A Dpci-sh7751.h23 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
24 #define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
50 #define SH7751_PCICONF1_MWIE 0x00000010 /* Memory Write+Invalidate */
53 #define SH7751_PCICONF1_MES 0x00000002 /* Memory Space Control */
74 #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */
79 #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */
109 /* Memory Control Registers */
110 #define SH7751_BCR1 0xFF800000 /* Memory BCR1 Register */
111 #define SH7751_BCR2 0xFF800004 /* Memory BCR2 Register */
112 #define SH7751_BCR3 0xFF800050 /* Memory BCR3 Register */
113 #define SH7751_BCR4 0xFE0A00F0 /* Memory BCR4 Register */
117 #define SH7751_MCR 0xFF800014 /* Memory Control Register */
119 /* General Memory Config Addresses */
H A Dpci-sh4.h120 #define SH4_PCIMBR 0x1C4 /* Memory Base Address */
121 #define SH4_PCIMBR_MASK 0xFF000000 /* Memory Space Mask */
122 #define SH4_PCIMBR_LOCK 0x00000001 /* Lock Memory Space */
134 #define SH4_PCIBCR1 0x1E0 /* Memory BCR1 Register */
136 #define SH4_PCIBCR2 0x1E4 /* Memory BCR2 Register */
142 #define SH4_PCIMCR 0x1F4 /* Memory Control Register */
143 #define SH4_PCIBCR3 0x1f8 /* Memory BCR3 Register */
H A Dpci-sh5.h59 #define PCISH5_ICR_MBR 0x1c4 /* Memory space bank register values */
75 #define PCISH5_ICR_CSR_MBAR0 0x014 /* First Memory base address register */
76 #define PCISH5_ICR_CSR_MBAR1 0x018 /* Second Memory base address register */
/linux-4.1.27/include/linux/platform_data/
H A Ddma-imx.h33 IMX_DMATYPE_MSHC, /* Memory Stick Host Controller */
34 IMX_DMATYPE_MSHC_SP, /* Shared Memory Stick Host Controller */
36 IMX_DMATYPE_MEMORY, /* Memory */
37 IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */
39 IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */
H A Ddma-mmp_tdma.h2 * SRAM Memory Management
H A Dmtd-nand-pxa3xx.h46 /* the data flash bus is shared between the Static Memory
/linux-4.1.27/arch/blackfin/mach-bf548/include/mach/
H A Dmem_map.h15 /* Async Memory Banks */
25 /* Boot ROM Memory */
35 /* Level 1 Memory */
37 /* Memory Map for ADSP-BF548 processors */
74 /* Level 2 Memory */
H A DdefBF54x_base.h151 /* Asynchronous Memory Control Registers */
153 #define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */
154 #define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */
155 #define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */
156 #define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */
157 #define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */
159 #define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */
161 /* DDR Memory Control Registers */
163 #define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */
164 #define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */
165 #define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */
166 #define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */
399 #define MDMA_D0_NEXT_DESC_PTR 0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
400 #define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */
401 #define MDMA_D0_CONFIG 0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */
402 #define MDMA_D0_X_COUNT 0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */
403 #define MDMA_D0_X_MODIFY 0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */
404 #define MDMA_D0_Y_COUNT 0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */
405 #define MDMA_D0_Y_MODIFY 0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */
406 #define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
407 #define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */
408 #define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
409 #define MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */
410 #define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */
411 #define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */
412 #define MDMA_S0_NEXT_DESC_PTR 0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
413 #define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */
414 #define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */
415 #define MDMA_S0_X_COUNT 0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */
416 #define MDMA_S0_X_MODIFY 0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */
417 #define MDMA_S0_Y_COUNT 0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */
418 #define MDMA_S0_Y_MODIFY 0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */
419 #define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
420 #define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */
421 #define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
422 #define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */
423 #define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */
424 #define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */
428 #define MDMA_D1_NEXT_DESC_PTR 0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
429 #define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */
430 #define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */
431 #define MDMA_D1_X_COUNT 0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */
432 #define MDMA_D1_X_MODIFY 0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */
433 #define MDMA_D1_Y_COUNT 0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */
434 #define MDMA_D1_Y_MODIFY 0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */
435 #define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
436 #define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */
437 #define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
438 #define MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */
439 #define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */
440 #define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */
441 #define MDMA_S1_NEXT_DESC_PTR 0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
442 #define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */
443 #define MDMA_S1_CONFIG 0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */
444 #define MDMA_S1_X_COUNT 0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */
445 #define MDMA_S1_X_MODIFY 0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */
446 #define MDMA_S1_Y_COUNT 0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */
447 #define MDMA_S1_Y_MODIFY 0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */
448 #define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
449 #define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */
450 #define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
451 #define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */
452 #define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */
453 #define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */
889 #define MDMA_D2_NEXT_DESC_PTR 0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
890 #define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */
891 #define MDMA_D2_CONFIG 0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */
892 #define MDMA_D2_X_COUNT 0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */
893 #define MDMA_D2_X_MODIFY 0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */
894 #define MDMA_D2_Y_COUNT 0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */
895 #define MDMA_D2_Y_MODIFY 0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */
896 #define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
897 #define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */
898 #define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
899 #define MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */
900 #define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */
901 #define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */
902 #define MDMA_S2_NEXT_DESC_PTR 0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
903 #define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */
904 #define MDMA_S2_CONFIG 0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */
905 #define MDMA_S2_X_COUNT 0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */
906 #define MDMA_S2_X_MODIFY 0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */
907 #define MDMA_S2_Y_COUNT 0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */
908 #define MDMA_S2_Y_MODIFY 0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */
909 #define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
910 #define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */
911 #define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
912 #define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */
913 #define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */
914 #define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */
918 #define MDMA_D3_NEXT_DESC_PTR 0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
919 #define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */
920 #define MDMA_D3_CONFIG 0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */
921 #define MDMA_D3_X_COUNT 0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */
922 #define MDMA_D3_X_MODIFY 0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */
923 #define MDMA_D3_Y_COUNT 0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */
924 #define MDMA_D3_Y_MODIFY 0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */
925 #define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
926 #define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */
927 #define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
928 #define MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */
929 #define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */
930 #define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */
931 #define MDMA_S3_NEXT_DESC_PTR 0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
932 #define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */
933 #define MDMA_S3_CONFIG 0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */
934 #define MDMA_S3_X_COUNT 0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */
935 #define MDMA_S3_X_MODIFY 0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */
936 #define MDMA_S3_Y_COUNT 0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */
937 #define MDMA_S3_Y_MODIFY 0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */
938 #define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
939 #define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */
940 #define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
941 #define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */
942 #define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */
943 #define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */
1534 #define MDMA0 0x200000 /* Memory DMA Stream 0 */
1535 #define MDMA1 0x400000 /* Memory DMA Stream 1 */
1565 #define MDMA2 0x20000 /* Memory DMA Stream 0 */
1566 #define MDMA3 0x40000 /* Memory DMA Stream 1 */
1640 #define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1641 #define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1642 #define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1643 #define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1682 #define AMSB0CTL 0x3 /* Async Memory Bank 0 select */
1683 #define AMSB1CTL 0xc /* Async Memory Bank 1 select */
1684 #define AMSB2CTL 0x30 /* Async Memory Bank 2 select */
1685 #define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */
1689 #define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */
1690 #define B1MODE 0xc /* Async Memory Bank 1 Access Mode */
1691 #define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */
1692 #define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */
1966 #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
1967 #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
1968 #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
1969 #define DMA0OVR 0x800 /* DMA0 Memory Access Override */
1970 #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
1973 #define L2DABL 0x70000 /* L2 Memory Disable. */
H A Danomaly.h38 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
50 /* External Memory Read Access Hangs Core With PLL Bypass */
52 /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
54 /* Addressing Conflict between Boot ROM and Asynchronous Memory */
66 /* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
70 /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
114 /* False Hardware Error when RETI Points to Invalid Memory */
146 /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
156 /* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
190 /* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
216 /* Boot from OTP Memory Not Functional */
224 /* Reset Vector Must Not Be in SDRAM Memory Space */
228 /* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
/linux-4.1.27/arch/blackfin/mach-bf609/include/mach/
H A Dmem_map.h15 /* Async Memory Banks */
25 /* Boot ROM Memory */
30 /* Level 1 Memory */
32 /* Memory Map for ADSP-BF60x processors */
82 /* Level 2 Memory */
H A Danomaly.h31 /* DDR2 Memory Reads May Fail Intermittently */
33 /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
39 /* False Hardware Error when RETI Points to Invalid Memory */
43 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
89 /* Spurious Unhandled NMI or L1 Memory Parity Error Interrupt May Occur Upon Entering the NMI ISR */
H A Dirq.h24 #define IRQ_C0_NMI_L1_PARITY_ERR BFIN_IRQ(10) /* Core 0 Unhandled NMI or L1 Memory Parity Error */
25 #define IRQ_C1_NMI_L1_PARITY_ERR BFIN_IRQ(11) /* Core 1 Unhandled NMI or L1 Memory Parity Error */
136 #define IRQ_PVP_MPDO BFIN_IRQ(116) /* DMA42 Data (PVP0 Memory Pipe Data Out) */
137 #define IRQ_PVP_MPDI BFIN_IRQ(117) /* DMA43 Data (PVP0 Memory Pipe Data In) */
138 #define IRQ_PVP_MPSTAT BFIN_IRQ(118) /* DMA44 Data (PVP0 Memory Pipe Status Out) */
139 #define IRQ_PVP_MPCI BFIN_IRQ(119) /* DMA45 Data (PVP0 Memory Pipe Control In) */
/linux-4.1.27/arch/arm/mach-ks8695/include/mach/
H A Dregs-pci.h23 #define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */
30 #define KS8695_PMBA (0x208) /* Bridge Memory Base Address */
31 #define KS8695_PMBAC (0x20C) /* Bridge Memory Base Address Control */
32 #define KS8695_PMBAM (0x210) /* Bridge Memory Base Address Mask */
33 #define KS8695_PMBAT (0x214) /* Bridge Memory Base Address Translation */
H A Dhardware.h7 * KS8695 - Memory Map definitions
H A Dmemory.h6 * KS8695 Memory definitions
H A Dregs-mem.h6 * KS8695 - Memory Controller registers and bit definitions
22 * Memory Controller Registers
/linux-4.1.27/arch/arm/mach-pxa/include/mach/
H A Daddr-map.h27 * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x)
35 * Dynamic Memory Controller (only on PXA3xx)
47 * Internal Memory Controller (PXA27x and later)
H A Dsmemc.h20 #define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */
21 #define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */
22 #define MSC2 (SMEMC_VIRT + 0x10) /* Static Memory Control Register 2 */
23 #define MECR (SMEMC_VIRT + 0x14) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
25 #define SXCNFG (SMEMC_VIRT + 0x1C) /* Synchronous Static Memory Control Register */
27 #define MCMEM0 (SMEMC_VIRT + 0x28) /* Card interface Common Memory Space Socket 0 Timing */
28 #define MCMEM1 (SMEMC_VIRT + 0x2C) /* Card interface Common Memory Space Socket 1 Timing */
47 #define MCMEM(s) (SMEMC_VIRT + 0x28 + ((s)<<2)) /* Card interface Common Memory Space Socket s Timing */
H A Dpxa2xx-regs.h143 #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
144 #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
159 #define CKEN_MEMC (22) /* Memory Controller Clock Enable */
160 #define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
161 #define CKEN_IM (20) /* Internal Memory Clock Enable */
H A Dpxa3xx-regs.h143 #define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */
144 #define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */
147 #define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */
167 #define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */
168 #define CKEN_SMC 9 /* < Static Memory Controller clock enable */
H A Dmainstone.h49 #define MST_MSCWR1_MS_ON (1 << 12) /* Memory Stick power control */
81 #define MST_MSCRD_nMEMSTK_CD (1 << 8) /* Memory Stick detection signal */
98 #define MST_INT_MSINS (1 << 6) /* Memory Stick* detection */
H A Dirqs.h25 #define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */
75 #define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */
/linux-4.1.27/arch/blackfin/mach-bf533/include/mach/
H A Dmem_map.h15 /* Async Memory Banks */
25 /* Boot ROM Memory */
30 /* Level 1 Memory */
38 /* Memory Map for ADSP-BF533 processors */
76 /* Memory Map for ADSP-BF532 processors */
115 /* Memory Map for ADSP-BF531 processors */
H A Dirq.h35 #define IRQ_MEM_DMA0 BFIN_IRQ(21) /* DMA8/9 Interrupt (Memory DMA Stream 0) */
36 #define IRQ_MEM_DMA1 BFIN_IRQ(22) /* DMA10/11 Interrupt (Memory DMA Stream 1) */
H A Danomaly.h68 /* Failing MMR Accesses when Preceding Memory Read Stalls */
94 /* Scratchpad Memory Bank Reads May Return Incorrect Data */
146 /* Writes to Synchronous SDRAM Memory May Be Lost */
156 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
162 /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
172 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
194 /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
206 /* False Hardware Error when RETI Points to Invalid Memory */
214 /* Possible Lockup Condition when Modifying PLL from External Memory */
222 /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
266 /* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */
284 /* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */
334 /* Overlapping Sequencer and Memory Stalls */
/linux-4.1.27/arch/blackfin/mach-bf537/include/mach/
H A Dmem_map.h15 /* Async Memory Banks */
25 /* Boot ROM Memory */
30 /* Level 1 Memory */
32 /* Memory Map for ADSP-BF537 processors */
74 /* Memory Map for ADSP-BF536 processors */
111 /* Memory Map for ADSP-BF534 processors */
H A Danomaly.h80 /* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
86 /* Writes to Synchronous SDRAM Memory May Be Lost */
96 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
104 /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
114 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
136 /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
142 /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
154 /* False Hardware Error when RETI Points to Invalid Memory */
160 /* Possible Lockup Condition when Modifying PLL from External Memory */
170 /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
H A Dirq.h43 #define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */
44 #define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */
/linux-4.1.27/include/uapi/linux/
H A Dsysinfo.h13 __kernel_ulong_t bufferram; /* Memory used by buffers */
20 __u32 mem_unit; /* Memory unit size in bytes */
H A Dacct.h55 comp_t ac_mem; /* Average Memory Usage */
91 comp_t ac_mem; /* Average Memory Usage */
H A Dvirtio_balloon.h35 #define VIRTIO_BALLOON_F_STATS_VQ 1 /* Memory Stats virtqueue */
57 * Memory statistics structure.
/linux-4.1.27/arch/xtensa/platforms/iss/include/platform/
H A Dhardware.h19 * Memory configuration.
/linux-4.1.27/arch/mn10300/include/asm/
H A Dmmu.h1 /* MN10300 Memory management context
/linux-4.1.27/arch/powerpc/boot/
H A Dstdio.h6 #define ENOMEM 12 /* Out of Memory */
H A Dredboot.h23 unsigned int bi_memstart; /* Memory start address */
24 unsigned int bi_memsize; /* Memory (end) size in bytes */
H A Dsimpleboot.c62 fatal("Memory range is not based at address 0\n"); platform_init()
/linux-4.1.27/arch/blackfin/mach-bf527/include/mach/
H A Dmem_map.h15 /* Async Memory Banks */
25 /* Boot ROM Memory */
30 /* Level 1 Memory */
32 /* Memory Map for ADSP-BF527 ADSP-BF525 ADSP-BF522 processors */
H A Danomaly.h52 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
90 /* Data Read From L3 Memory by USB DMA May be Corrupted */
94 /* Boot from OTP Memory Not Functional */
102 /* Reset Vector Must Not Be in SDRAM Memory Space */
130 /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
196 /* False Hardware Error when RETI Points to Invalid Memory */
212 /* Possible Lockup Condition when Modifying PLL from External Memory */
226 /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
/linux-4.1.27/arch/blackfin/mach-bf538/include/mach/
H A Dmem_map.h15 /* Async Memory Banks */
25 /* Boot ROM Memory */
30 /* Level 1 Memory */
38 /* Memory Map for ADSP-BF538/9 processors */
H A Danomaly.h66 /* Writes to Synchronous SDRAM Memory May Be Lost */
74 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
86 /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
92 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
116 /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
130 /* False Hardware Error when RETI Points to Invalid Memory */
136 /* Possible Lockup Condition when Modifying PLL from External Memory */
144 /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
/linux-4.1.27/arch/sh/boards/mach-r2d/
H A Dsetup.c285 * ColSizeX = 11 - External Memory Column Size: 256 words. rts7751r2d_setup()
286 * APX = 1 - External Memory Active to Pre-Charge Delay: 7 clocks. rts7751r2d_setup()
287 * RstX = 1 - External Memory Reset: Normal. rts7751r2d_setup()
288 * Rfsh = 1 - Local Memory Refresh to Command Delay: 12 clocks. rts7751r2d_setup()
289 * BwC = 1 - Local Memory Block Write Cycle Time: 2 clocks. rts7751r2d_setup()
290 * BwP = 1 - Local Memory Block Write to Pre-Charge Delay: 1 clock. rts7751r2d_setup()
291 * AP = 1 - Internal Memory Active to Pre-Charge Delay: 7 clocks. rts7751r2d_setup()
292 * Rst = 1 - Internal Memory Reset: Normal. rts7751r2d_setup()
293 * RA = 1 - Internal Memory Remain in Active State: Do not remain. rts7751r2d_setup()
/linux-4.1.27/arch/m32r/include/asm/
H A Ds1d13806.h11 // Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=33.333MHz)
24 {0x0010,0x00}, // Memory Clock Configuration Register
33 {0x001E,0x02}, // CPU To Memory Wait State Select Register
37 {0x0020,0x80}, // Memory Configuration Register
62 {0x0010,0x01}, // Memory Clock Configuration Register
66 {0x001E,0x00}, // CPU To Memory Wait State Select Register
67 {0x0020,0x80}, // Memory Configuration Register
95 {0x0046,0x00}, // LCD Memory Address Offset Register 0
96 {0x0047,0x02}, // LCD Memory Address Offset Register 1
161 {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
162 {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
175 {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
190 {0x0046,0x80}, // LCD Memory Address Offset Register 0
191 {0x0047,0x02}, // LCD Memory Address Offset Register 1
193 {0x0046,0xf0}, // LCD Memory Address Offset Register 0
194 {0x0047,0x00}, // LCD Memory Address Offset Register 1
197 {0x0066,0x80}, // CRT/TV Memory Address Offset Register 0 // takeo
198 {0x0067,0x02}, // CRT/TV Memory Address Offset Register 1
H A Daddrspace.h14 * Memory segments (32bit kernel mode addresses)
/linux-4.1.27/arch/sh/include/cpu-sh4/cpu/
H A Daddrspace.h40 #define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
41 #define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
H A Dsh7785.h11 * MODE5: LBSC - Area0 Memory Type / Bus Width [CS0BCR.8]
12 * MODE6: LBSC - Area0 Memory Type / Bus Width [CS0BCR.9]
13 * MODE7: LBSC - Area0 Memory Type / Bus Width [CS0BCR.3]
/linux-4.1.27/arch/powerpc/include/asm/
H A Dmmu-44x.h41 #define PPC44x_TLB_M 0x00000200 /* Memory is coherent */
42 #define PPC44x_TLB_G 0x00000100 /* Memory is guarded */
43 #define PPC44x_TLB_E 0x00000080 /* Memory is little endian */
79 #define PPC47x_TLB2_IL1I 0x00020000 /* Memory is guarded */
80 #define PPC47x_TLB2_IL1D 0x00010000 /* Memory is guarded */
87 #define PPC47x_TLB2_M 0x00000200 /* Memory is coherent */
88 #define PPC47x_TLB2_G 0x00000100 /* Memory is guarded */
89 #define PPC47x_TLB2_E 0x00000080 /* Memory is little endian */
H A Dmmu-40x.h51 #define TLB_M 0x00000002 /* Memory is coherent */
52 #define TLB_G 0x00000001 /* Memory is guarded from prefetch */
H A Dpte-hash64.h21 /* We can derive Memory coherence from _PAGE_NO_CACHE */
H A Dimmap_cpm2.h2 * CPM2 Internal Memory Map
5 * The Internal Memory Map for devices with CPM2 on them. This
67 /* Memory controller registers.
582 memctl_cpm2_t im_memctl; /* Memory Controller */
H A Dmmu-hash32.h74 unsigned long m:1; /* Memory coherence */
/linux-4.1.27/arch/unicore32/include/asm/
H A Dbarrier.h2 * Memory barrier implementations for PKUnity SoC and UniCore ISA
H A Dcache.h19 * Memory returned by kmalloc() may be used for DMA, so we must make
H A Dmemblock.h17 * Memory map description
/linux-4.1.27/arch/tile/include/hv/
H A Ddrv_mshim_intf.h26 /** Memory info under each memory controller. */
30 uint8_t mem_type; /**< Memory type, DDR2 or DDR3. */
31 uint8_t mem_ecc; /**< Memory supports ECC. */
/linux-4.1.27/arch/blackfin/mach-bf561/include/mach/
H A Dmem_map.h15 /* Async Memory Banks */
25 /* Boot ROM Memory */
30 /* Level 1 Memory */
38 /* Memory Map for ADSP-BF561 processors */
100 /* Level 2 Memory */
104 /* Scratch Pad Memory */
H A Danomaly.h28 /* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
50 /* Overlapping Sequencer and Memory Stalls */
60 /* Internal Memory DMA Does Not Operate at Full Speed */
70 /* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
80 /* Failing MMR Accesses when Preceding Memory Read Stalls */
106 /* Scratchpad Memory Bank Reads May Return Incorrect Data */
160 /* Data Cache Write Back to External Synchronous Memory May Be Lost */
182 /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
190 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
212 /* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
234 /* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
240 /* False Hardware Error when RETI Points to Invalid Memory */
248 /* Possible Lockup Condition when Modifying PLL from External Memory */
256 /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
320 /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
/linux-4.1.27/arch/mips/include/asm/dec/
H A Dkn02xa.h25 * Memory control ASIC registers.
39 * Memory Error Register bits, common definitions.
57 * Memory Size Register bits, common definitions.
H A Dkn02ba.h49 * Memory Error Register bits.
54 * Memory Size Register bits.
H A Dkn02ca.h50 * Memory Error Register bits.
55 * Memory Size Register bits.
H A Dkn03.h54 * Memory Control Register bits.
/linux-4.1.27/arch/arm/mach-omap2/
H A Dpowerdomain-common.c28 /* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */
35 /* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */
42 /* OMAP3 and OMAP4 Memory Status bits */
H A Dgpio.c54 pr_err("gpio%d: Memory allocation failed\n", id); omap2_gpio_dev_init()
64 pr_err("gpio%d: Memory allocation failed\n", id); omap2_gpio_dev_init()
/linux-4.1.27/drivers/scsi/mvsas/
H A Dmv_defs.h357 CMD_APP_MEM_CTL = 0x144, /* Application Memory Control */
358 CMD_XOR_MEM_CTL = 0x148, /* XOR Block Memory Control */
359 CMD_DMA_MEM_CTL = 0x14c, /* DMA Block Memory Control */
360 CMD_PORT_MEM_CTL0 = 0x150, /* Port Memory Control 0 */
361 CMD_PORT_MEM_CTL1 = 0x154, /* Port Memory Control 1 */
362 CMD_SATA_PORT_MEM_CTL0 = 0x158, /* SATA Port Memory Control 0 */
363 CMD_SATA_PORT_MEM_CTL1 = 0x15c, /* SATA Port Memory Control 1 */
364 CMD_XOR_MEM_BIST_CTL = 0x160, /* XOR Memory BIST Control */
366 CMD_DMA_MEM_BIST_CTL = 0x168, /* DMA Memory BIST Control */
367 CMD_DMA_MEM_BIST_STAT = 0x16c, /* DMA Memory BIST Status */
368 CMD_PORT_MEM_BIST_CTL = 0x170, /* Port Memory BIST Control */
369 CMD_PORT_MEM_BIST_STAT0 = 0x174, /* Port Memory BIST Status 0 */
370 CMD_PORT_MEM_BIST_STAT1 = 0x178, /* Port Memory BIST Status 1 */
371 CMD_STP_MEM_BIST_CTL = 0x17c, /* STP Memory BIST Control */
372 CMD_STP_MEM_BIST_STAT0 = 0x180, /* STP Memory BIST Status 0 */
373 CMD_STP_MEM_BIST_STAT1 = 0x184, /* STP Memory BIST Status 1 */
/linux-4.1.27/arch/xtensa/platforms/xt2000/include/platform/
H A Dhardware.h21 * Memory configuration.
/linux-4.1.27/drivers/usb/host/
H A Dohci-tmio.c44 #define CCR_ILME 0x40 /* b Internal Local Memory Enable */
47 #define CCR_LMW1L 0x54 /* w Local Memory Window 1 LMADRS Low */
48 #define CCR_LMW1H 0x56 /* w Local Memory Window 1 LMADRS High */
49 #define CCR_LMW1BL 0x58 /* w Local Memory Window 1 Base Address Low */
50 #define CCR_LMW1BH 0x5A /* w Local Memory Window 1 Base Address High */
51 #define CCR_LMW2L 0x5C /* w Local Memory Window 2 LMADRS Low */
52 #define CCR_LMW2H 0x5E /* w Local Memory Window 2 LMADRS High */
53 #define CCR_LMW2BL 0x60 /* w Local Memory Window 2 Base Address Low */
54 #define CCR_LMW2BH 0x62 /* w Local Memory Window 2 Base Address High */
H A Dehci-ppc-of.c74 * Fix: Enable Break Memory Transfer (BMT) in INSNREG3
165 ehci_dbg(ehci, "Break Memory Transfer (BMT) is %senabled!\n", ehci_hcd_ppc_of_probe()
/linux-4.1.27/arch/arm/include/asm/
H A Dcache.h11 * Memory returned by kmalloc() may be used for DMA, so we must make
H A Dkvm_asm.h44 #define c10_NMRR 22 /* Normal Memory Remap Register */
51 #define c10_AMAIR0 29 /* Auxilary Memory Attribute Indirection Reg0 */
52 #define c10_AMAIR1 30 /* Auxilary Memory Attribute Indirection Reg1 */
/linux-4.1.27/drivers/staging/olpc_dcon/
H A Dolpc_dcon.h39 /* Memory controller power down function */
41 /* Memory controller software reset */
/linux-4.1.27/arch/mips/include/asm/mach-generic/
H A Dspaces.h44 * Memory above this physical address will be considered highmem.
75 * Memory above this physical address will be considered highmem.
/linux-4.1.27/arch/c6x/platforms/
H A Demif.c2 * External Memory Interface
41 * Parse device tree for existence of an EMIF (External Memory Interface)
/linux-4.1.27/arch/arm/mach-sa1100/include/mach/
H A Dnanoengine.h33 * nanoEngine Memory Map:
37 * 1860.0000 - 186F.FFFF - 1 MB Internal PCI Memory Read/Write
H A DSA-1100.h37 * Personal Computer Memory Card International Association (PCMCIA) sockets
44 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
49 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
54 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
61 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
67 #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
72 #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
973 #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */
974 #define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */
1083 #define TUCR_MR 0x00000400 /* Memory Request mode */
1084 #define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */
1085 #define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */
1210 #define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */
1212 #define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */
1380 * Dynamic Random-Access Memory (DRAM) control registers
1383 * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
1385 * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
1388 * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
1391 * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
1466 * MSC0 Memory system: Static memory Control register 0
1468 * MSC1 Memory system: Static memory Control register 1
1497 #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
1498 #define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */
1532 * Personal Computer Memory Card International Association (PCMCIA) control
1536 * MECR Memory system: Expansion memory bus (PCMCIA)
1545 /* Memory system: */
1564 #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
1565 #define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \
1592 * Direct Memory Access (DMA) control registers
1613 * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access
1615 * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access
1617 * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access
1619 * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access
/linux-4.1.27/sound/soc/codecs/
H A Drt5670-dsp.h24 #define RT5670_DSP_CMD_MW (0x3b << 8) /* Memory Write */
25 #define RT5670_DSP_CMD_MR (0x37 << 8) /* Memory Read */
/linux-4.1.27/include/acpi/
H A Dactbl3.h67 #define ACPI_SIG_MPST "MPST" /* Memory Power State Table */
69 #define ACPI_SIG_PMTT "PMTT" /* Platform Memory Topology Table */
74 #define ACPI_SIG_PCCS "PCC" /* PCC Shared Memory Region */
78 #define ACPI_SIG_MATR "MATR" /* Memory Address Translation Table */
342 * MPST - Memory Power State Table (ACPI 5.0)
360 /* Memory Platform Communication Channel Info */
366 /* Memory Power Node Structure */
385 /* Memory Power State Structure (follows POWER_NODE above) */
398 /* Memory Power State Characteristics Structure (follows all POWER_NODEs) */
421 /* Shared Memory Region (not part of an ACPI table) */
505 /* Shared Memory Region */
515 * PMTT - Platform Memory Topology Table (ACPI 5.0)
560 /* 1: Memory Controller subtable */
602 /* RASF Platform Communication Channel Shared Memory Region */
/linux-4.1.27/arch/arm64/include/asm/
H A Dkvm_asm.h39 #define MAIR_EL1 13 /* Memory Attribute Indirection Register */
45 #define AMAIR_EL1 19 /* Aux Memory Attribute Indirection Register */
89 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
95 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
96 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
H A Dcache.h25 * Memory returned by kmalloc() may be used for DMA, so we must make
H A Dmemory.h96 * Memory types available.
105 * Memory types for Stage-2 translation
/linux-4.1.27/include/video/
H A Ds1d13xxxfb.h33 #define S1DREG_CLK_CNF 0x0010 /* Memory Clock Configuration Register */
37 #define S1DREG_CPU2MEM_WST_SEL 0x001E /* CPU To Memory Wait State Select Register */
38 #define S1DREG_MEM_CNF 0x0020 /* Memory Configuration Register */
58 #define S1DREG_LCD_MEM_OFF0 0x0046 /* LCD Memory Address Offset Register 0 */
59 #define S1DREG_LCD_MEM_OFF1 0x0047 /* LCD Memory Address Offset Register 1 */
77 #define S1DREG_CRT_MEM_OFF0 0x0066 /* CRT/TV Memory Address Offset Register 0 */
78 #define S1DREG_CRT_MEM_OFF1 0x0067 /* CRT/TV Memory Address Offset Register 1 */
118 #define S1DREG_BBLT_MEM_OFF0 0x010C /* BitBLT Memory Address Offset Register 0 */
119 #define S1DREG_BBLT_MEM_OFF1 0x010D /* BitBLT Memory Address Offset Register 1 */
133 #define S1DREG_CPU2MEM_WDOGT 0x01F4 /* CPU-to-Memory Access Watchdog Timer Register */
H A Dmbxfb.h21 /* Memory info */
/linux-4.1.27/drivers/pcmcia/
H A Dpxa2xx_base.c42 * Personal Computer Memory Card International Association (PCMCIA) sockets
49 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
54 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
59 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
66 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
72 #define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */
77 #define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */
H A Dsa11xx_base.h36 /* SA-1100 PCMCIA Memory and I/O timing
47 /* MECR: Expansion Memory Configuration Register
/linux-4.1.27/drivers/block/
H A Dumem.h4 * Micro Memory MM5415
5 * family PCI Memory Module with Battery Backup.
7 * Copyright Micro Memory INC 2001. All rights reserved.
H A Dumem.c2 * mm.c - Micro Memory(tm) PCI memory board block device driver - v2.3
8 * This driver for the Micro Memory PCI Memory Module with Battery Backup
9 * is Copyright Micro Memory Inc 2001-2002. All rights reserved.
15 * This driver provides a standard block device interface for Micro Memory(tm)
30 * 07Jan2002: P. Nguyen - Used PCI Memory Write & Invalidate for DMA
73 #define DRIVER_DESC "Micro Memory(tm) PCI memory board block driver"
592 "Memory access error detected (err count %d)\n", mm_interrupt()
819 "Micro Memory(tm) controller found (PCI Mem Module (Battery Backup))\n"); mm_pci_probe()
976 if (pci_write_cmd != 0x0F) /* If not Memory Write & Invalidate */ mm_pci_probe()
977 pci_write_cmd = 0x07; /* then Memory Write command */ mm_pci_probe()
979 if (pci_write_cmd & 0x08) { /* use Memory Write and Invalidate */ mm_pci_probe()
982 cfg_command |= 0x10; /* Memory Write & Invalidate Enable */ mm_pci_probe()
/linux-4.1.27/arch/arm/mach-realview/include/mach/
H A Dboard-pb1176.h60 #define REALVIEW_PB1176_PCI_MEM_BASE0 0x63000000 /* Memory region 1 */
61 #define REALVIEW_PB1176_PCI_MEM_BASE1 0x64000000 /* Memory region 2 */
62 #define REALVIEW_PB1176_PCI_MEM_BASE2 0x68000000 /* Memory region 3 */
/linux-4.1.27/arch/arm/mach-at91/include/mach/
H A Dat91rm9200_mc.h7 * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
19 /* Memory Controller */
68 /* Static Memory Controller (SMC) registers */
/linux-4.1.27/drivers/edac/
H A Dppc4xx_edac.h66 * Memory Controller Bus Error Status Register
88 * Memory Controller PLB Write Master Interrupt Register
104 * Memory Controller Options 1 Register
122 * Memory Bank 0 - n Configuration Register
H A Di5100_edac.c2 * Intel 5100 Memory Controllers kernel module
9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
37 #define I5100_MC 0x40 /* Memory Control Register */
40 #define I5100_MS 0x44 /* Memory Status Register */
43 #define I5100_TOLM 0x6c /* Top of Low Memory */
44 #define I5100_MIR0 0x80 /* Memory Interleave Range 0 */
45 #define I5100_MIR1 0x84 /* Memory Interleave Range 1 */
46 #define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */
47 #define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */
82 #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */
85 #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */
86 #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */
87 #define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */
88 #define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */
89 #define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */
90 #define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */
91 #define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */
922 * Intel 5100 Memory Controller Hub Chipset (318378) datasheet i5100_do_inject()
925 * Intel 7300 Chipset Memory Controller Hub (318082) datasheet i5100_do_inject()
1030 /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */ i5100_init_one()
1044 /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */ i5100_init_one()
1209 /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */
H A Damd76x_edac.c2 * AMD 76x Memory Controller kernel module
63 #define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b)
97 * @mci: Memory controller
123 * @mci: Memory controller
175 * @mci: Memory controller
H A Di7300_edac.c2 * Intel 7300 class Memory Controllers kernel module (Clarksboro)
12 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
49 * Memory topology is organized as:
105 u16 mir[MAX_MIR]; /* Memory Interleave Reg*/
107 u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */
127 * Function 1: Memory Branch Map, Control, Errors Register
172 * MTRx - Memory Technology Registers
196 [1] = "Memory or FBD configuration CRC read error",
197 [0] = "Memory Write error on non-redundant retry or "
208 [21] = "Memory Write error on redundant retry",
215 [11] = "Memory or FBD configuration CRC read error",
217 [9] = "Memory Write error on first attempt",
758 edac_dbg(2, "Memory Technology Registers:\n"); i7300_init_csrows()
821 * decode_mir() - Decodes Memory Interleave Register (MIR) info
871 edac_dbg(0, "Memory controller operating on single mode\n"); i7300_get_mc_regs()
873 edac_dbg(0, "Memory controller operating on %smirrored mode\n", i7300_get_mc_regs()
881 /* Get Memory Interleave Range registers */ i7300_get_mc_regs()
H A Di5400_edac.c2 * Intel 5400 class Memory Controllers kernel module (Seaburg)
18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
21 * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with
58 * Function 1: Memory Branch Map, Control, Errors Register
103 * Function 0: Memory Map Branch 0
106 * Function 0: Memory Map Branch 1
144 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
145 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
156 EMASK_M13 = 1<<12, /* Memory Write error on first attempt */
158 EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */
168 EMASK_M25 = 1<<24, /* Memory Write error on redundant retry */
179 [0] = "Memory Write error on non-redundant retry",
180 [1] = "Memory or FB-DIMM configuration CRC read error",
191 [12] = "Memory Write error on first attempt",
193 [14] = "Memory or FB-DIMM configuration CRC read error",
203 [24] = "Memory Write error on redundant retry",
283 * MTRx - Memory Technology Registers
340 u16 b0_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */
344 u16 b1_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */
451 NEXT FATAL error register and the Memory Error Log Register A i5400_get_error_info()
1123 edac_dbg(2, "Memory Technology Registers:\n"); i5400_get_mc_regs()
H A Dcpc925_edac.c2 * cpc925_edac.c, EDAC driver for IBM CPC925 Bridge and Memory Controller.
63 * "CPC925 Bridge and Memory Controller User Manual, SA14-2761-02".
67 * CPU and Memory Controller Registers
122 * Memory Bus Configuration Register (MBCR)
131 * Memory Bank Mode Register (MBMR)
141 * Memory Bank Boundary Address Register (MBBAR)
149 * Memory Scrub Control Register (MSCR)
159 * Memory Scrub Range Start Register (MSRSR)
164 * Memory Scrub Range End Register (MSRER)
169 * Memory Scrub Pattern Register (MSPR)
174 * Memory Check Control Register (MCCR)
182 * Memory Check Range End Register (MCRER)
187 * Memory Error Address Register (MEAR)
205 * Memory Error Syndrome Register (MESR)
212 * Memory Mode Control Register (MMCR)
H A Di3200_edac.c2 * Intel 3200/3210 Memory Controller kernel module
33 #define I3200_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */
38 #define I3200_TOM 0xa0 /* Top of Memory (16b)
57 * 9 LOCK to non-DRAM Memory Flag (LCKF)
H A Dx38_edac.c2 * Intel X38 Memory Controller kernel module
33 #define X38_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */
38 #define X38_TOM 0xa0 /* Top of Memory (16b)
57 * 9 LOCK to non-DRAM Memory Flag (LCKF)
/linux-4.1.27/drivers/acpi/
H A Dreboot.c31 /* The reset register can only exist in I/O, Memory or PCI config space acpi_reboot()
H A Dacpi_memhotplug.c24 * ACPI based HotPlug driver that supports Memory Hotplug
54 /* Memory Device States */
74 u64 start_addr; /* Memory Range start physical addr */
75 u64 length; /* Memory Range length */
349 dev_dbg(&device->dev, "Memory device configured by ACPI\n"); acpi_memory_device_add()
/linux-4.1.27/drivers/gpu/drm/via/
H A Dvia_dmablit.h87 #define VIA_PCI_DMA_MAR0 0xE40 /* Memory Address Register of Channel 0 */
92 #define VIA_PCI_DMA_MAR1 0xE50 /* Memory Address Register of Channel 1 */
97 #define VIA_PCI_DMA_MAR2 0xE60 /* Memory Address Register of Channel 2 */
102 #define VIA_PCI_DMA_MAR3 0xE70 /* Memory Address Register of Channel 3 */
/linux-4.1.27/include/linux/ssb/
H A Dssb_driver_pci.h72 #define SSB_PCICORE_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */
74 #define SSB_PCICORE_SBTOPCI_RC_READ 0x00000000 /* Memory read */
75 #define SSB_PCICORE_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
76 #define SSB_PCICORE_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
/linux-4.1.27/arch/avr32/include/asm/
H A Daddrspace.h16 /* Memory segments when segmentation is enabled */
H A Dcache.h8 * Memory returned by kmalloc() may be used for DMA, so we must make
/linux-4.1.27/arch/arm/mach-s3c24xx/
H A Danubis.h8 * ANUBIS - Memory map definitions
H A Dosiris.h7 * OSIRIS - Memory map definitions
H A Dregs-mem.h9 * S3C2410 Memory Control register definitions
/linux-4.1.27/arch/arm/plat-samsung/include/plat/
H A Dmap-s5p.h6 * S5P - Memory map definitions
H A Dmap-base.h7 * S3C - Memory map definitions (virtual addresses)
H A Dmap-s3c.h6 * S3C24XX - Memory map definitions
/linux-4.1.27/arch/arm/mach-exynos/include/mach/
H A Dmap.h5 * EXYNOS4 - Memory map definitions
/linux-4.1.27/arch/arm/mach-mmp/include/mach/
H A Daddr-map.h28 /* Static Memory Controller - Chip Select 0 and 1 */
H A Dregs-smc.h4 * Static Memory Controller Registers
/linux-4.1.27/include/linux/can/platform/
H A Dcc770.h9 #define CPUIF_DMC 0x20 /* Divide Memory Clock */
/linux-4.1.27/drivers/staging/dgnc/
H A Ddgnc_pci.h63 /* Size of Memory and I/O for PCI (4 K) */
66 /* Size of Memory (2MB) */
/linux-4.1.27/arch/sparc/kernel/
H A Dleon_pci.c20 * PCI Memory and Prefetchable Memory is direct-mapped. However I/O Space is
/linux-4.1.27/arch/mips/include/asm/fw/arc/
H A Dhinv.h38 Memory, enumerator in enum:configtype
69 Memory, enumerator in enum:configtype
/linux-4.1.27/include/soc/at91/
H A Dat91sam9_sdramc.h80 #define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */
81 #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
H A Dat91rm9200_sdramc.h7 * Memory Controllers (SDRAMC only) - System peripherals registers.
H A Dat91sam9_ddrsdr.h94 #define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
95 #define AT91_DDRSDRC_MD (7 << 0) /* Memory Device Type */
/linux-4.1.27/include/linux/
H A Dsuperhyway.h27 u8 bot_mb; /* Bottom Memory block */
28 u8 top_mb; /* Top Memory block */
H A Ddma-contiguous.h5 * Contiguous Memory Allocator for DMA mapping framework
18 * Contiguous Memory Allocator
20 * The Contiguous Memory Allocator (CMA) makes it possible to
H A Ddm-io.h61 struct dm_io_memory mem; /* Memory to use for io */
/linux-4.1.27/arch/parisc/include/asm/
H A Dpdcpat.h150 #define PDC_PAT_MEM_SETGM 9L /* Set Golden Memory value */
153 /* Memory Address */
160 #define PDC_PAT_MEM_GET_TBL_SIZE 131L /* Get Memory Table Size */
161 #define PDC_PAT_MEM_GET_TBL 132L /* Get Memory Table */
164 /* PDC PAT NVOLATILE -- Access Non-Volatile Memory */
167 #define PDC_PAT_NVOLATILE_READ 0L /* Read Non-Volatile Memory */
168 #define PDC_PAT_NVOLATILE_WRITE 1L /* Write Non-Volatile Memory */
216 unsigned char entry_type; /* 1 = Memory Descriptor Entry Type */
/linux-4.1.27/arch/avr32/mach-at32ap/include/mach/
H A Dsmc.h2 * Static Memory Controller for AT32 chips
6 * Inspired by the OMAP2 General-Purpose Memory Controller interface
/linux-4.1.27/arch/arm/mach-sa1100/
H A Djornada720.c65 {0x0010,0x01}, // Memory Clock Configuration Register
69 {0x001E,0x01}, // CPU To Memory Wait State Select Register
70 {0x0020,0x00}, // Memory Configuration Register
90 {0x0046,0x80}, // LCD Memory Address Offset Register 0
91 {0x0047,0x02}, // LCD Memory Address Offset Register 1
109 {0x0066,0x40}, // CRT/TV Memory Address Offset Register 0
110 {0x0067,0x01}, // CRT/TV Memory Address Offset Register 1
150 {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
151 {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
167 {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
H A Dnanoengine.c74 /* Internal PCI Memory Read/Write */
/linux-4.1.27/drivers/acpi/acpica/
H A Drsaddr.c213 /* Resource Type (Memory, Io, bus_number, etc.) */
240 * acpi_rs_convert_mem_flags - Flags common to Memory address descriptors
248 /* Memory-specific flags */
325 /* Get the Type-Specific Flags (Memory and I/O descriptors only) */ acpi_rs_get_address_common()
368 /* Set the Type-Specific Flags (Memory and I/O descriptors only) */ acpi_rs_set_address_common()
H A Dutaddress.c63 * The only supported Space IDs are Memory and I/O. Called when
129 * supported Space IDs are Memory and I/O. Called when an
192 * returned for Space IDs other than Memory or I/O.
196 * Space IDs are Memory and I/O.
/linux-4.1.27/drivers/tty/serial/jsm/
H A Djsm_driver.c139 * 0 PLX Memory Mapped Config jsm_probe_one()
142 * 3 Memory Mapped VPD jsm_probe_one()
143 * 4 Memory Mapped UARTs and Status jsm_probe_one()
169 "Card has no PCI Memory resources, failing board.\n"); jsm_probe_one()
217 "Card has no PCI Memory resources, failing board.\n"); jsm_probe_one()
/linux-4.1.27/arch/microblaze/include/asm/
H A Dmmu.h35 unsigned long m:1; /* Memory coherence */
121 # define TLB_M 0x00000002 /* Memory is coherent */
122 # define TLB_G 0x00000001 /* Memory is guarded from prefetch */
/linux-4.1.27/arch/arm/mach-dove/include/mach/
H A Ddove.h19 * e0000000 @runtime 128M PCIe-0 Memory space
20 * e8000000 @runtime 128M PCIe-1 Memory space
172 /* Memory Controller */
/linux-4.1.27/samples/bpf/
H A Dlibbpf.h114 /* Memory load, dst_reg = *(uint *) (src_reg + off16) */
124 /* Memory store, *(uint *) (dst_reg + off16) = src_reg */
134 /* Memory store, *(uint *) (dst_reg + off16) = imm32 */
/linux-4.1.27/sound/synth/emux/
H A Demux_proc.c49 snd_iprintf(buf, "Memory Size: %d\n", emu->memhdr->size); snd_emux_proc_info_read()
50 snd_iprintf(buf, "Memory Available: %d\n", snd_util_mem_avail(emu->memhdr)); snd_emux_proc_info_read()
53 snd_iprintf(buf, "Memory Size: 0\n"); snd_emux_proc_info_read()
/linux-4.1.27/arch/mips/include/asm/
H A Dnile4.h53 * Memory-Interface Registers
56 #define NILE4_MEMCTRL 0x00C0 /* Memory Control */
57 #define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */
58 #define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */
183 #define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */
263 #define NILE4_PCICMD_MEM 3 /* PCI Memory Space */
H A Daddrspace.h60 * Memory segments (64bit kernel mode addresses)
94 * Memory segments (32bit kernel mode addresses)
/linux-4.1.27/drivers/atm/
H A DuPD98401.h41 #define uPD98401_IA_TGT_CM 0 /* - Control Memory */
118 #define uPD98401_GMR_CPE 0x00008000 /* Control Memory Parity Enable */
142 #define uPD98401_INT_CPE 0x04000000 /* Control Memory Parity Error */
188 #define uPD98401_TOS 0x40100 /* Top of Stack Control Memory Address */
189 #define uPD98401_SMA 0x40200 /* Shapers Control Memory Start Address */
190 #define uPD98401_PMA 0x40201 /* Receive Pool Control Memory Start Address */
/linux-4.1.27/drivers/spi/
H A Dspi-dw-mmio.c2 * Memory-mapped interface driver for DW SPI Core
147 MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
/linux-4.1.27/arch/mips/fw/arc/
H A Dmemory.c46 "Bad Memory",
56 "Bad Memory",
/linux-4.1.27/drivers/net/ethernet/intel/i40e/
H A Di40e_alloc.h32 /* Memory allocation types */
/linux-4.1.27/drivers/net/ethernet/intel/i40evf/
H A Di40e_alloc.h32 /* Memory allocation types */
/linux-4.1.27/drivers/media/platform/omap3isp/
H A Dispccp2.h53 /* Memory channel configuration */
/linux-4.1.27/drivers/net/ethernet/atheros/atl1e/
H A Datl1e_param.c48 /* Transmit Memory count
59 /* Receive Memory Block Count
211 { /* Receive Memory Block Count */ atl1e_check_options()
214 .name = "Memory size of rx buffer(KB)", atl1e_check_options()
/linux-4.1.27/drivers/infiniband/hw/ehca/
H A Dhipz_hw.h50 /* QP Table Entry Memory Map */
170 /* MRMWPT Entry Memory Map */
243 /* CQ Table Entry Memory Map */
273 /* EQ Table Entry Memory Map */
/linux-4.1.27/arch/x86/kernel/
H A Dcrash_dump_64.c2 * Memory preserving reboot related code.
H A Dcrash_dump_32.c2 * Memory preserving reboot related code.
/linux-4.1.27/arch/xtensa/platforms/xtfpga/include/platform/
H A Dhardware.h18 /* Memory configuration. */
/linux-4.1.27/arch/sh/kernel/
H A Dcrash_dump.c2 * crash_dump.c - Memory preserving reboot related code.
/linux-4.1.27/arch/unicore32/include/mach/
H A Dregs-dmac.h2 * PKUnity Direct Memory Access Controller (DMAC)
/linux-4.1.27/arch/x86/include/asm/
H A Dimr.h2 * imr.h: Isolated Memory Region API
/linux-4.1.27/arch/mips/include/asm/mach-malta/
H A Dspaces.h15 * Traditional Malta Board Memory Map for EVA
/linux-4.1.27/arch/mips/include/asm/mips-boards/
H A Dpiix4.h33 /* Top Of Memory */
/linux-4.1.27/arch/powerpc/platforms/chrp/
H A Dgg2.h20 * Memory Map (CHRP mode)
/linux-4.1.27/arch/sh/kernel/cpu/
H A Dfpu.c16 * Memory allocation at the first usage of the FPU and other state. init_fpu()
/linux-4.1.27/arch/avr32/mach-at32ap/
H A Dsdramc.h68 /* MDR - Memory Device Register */
H A Dhsmc.c2 * Static Memory Controller for AT32 chips
252 dev_info(&pdev->dev, "Atmel Static Memory Controller at 0x%08lx\n", hsmc_probe()
H A Dhsmc.h2 * Register definitions for Atmel Static Memory Controller (SMC)
/linux-4.1.27/arch/cris/kernel/
H A Dcrisksyms.c46 /* Memory functions */
/linux-4.1.27/arch/ia64/include/asm/sn/
H A Dmspec.h35 * Each Atomic Memory Operation (amo, formerly known as fetchop)
/linux-4.1.27/arch/ia64/kernel/
H A Dcrash_dump.c2 * kernel/crash_dump.c - Memory preserving reboot related code.
/linux-4.1.27/arch/arm/mach-pxa/
H A Dsmemc.c2 * Static Memory Controller
/linux-4.1.27/arch/arm/mach-shmobile/
H A Ddma-register.h20 * Direct Memory Access Controller
/linux-4.1.27/arch/arm/mach-gemini/include/mach/
H A Dhardware.h16 * Memory Map definitions
/linux-4.1.27/arch/arm/mach-omap1/include/mach/
H A Dserial.h17 * Memory entry used for the DEBUG_LL UART configuration, relative to
/linux-4.1.27/tools/perf/util/
H A Dlzma.c13 return "Memory allocation failed"; lzma_strerror()
/linux-4.1.27/include/linux/decompress/
H A Dmm.h4 * Memory management for pre-boot and ramdisk uncompressors
/linux-4.1.27/drivers/mtd/devices/
H A Dlart.c3 * MTD driver for the 28F160F3 Flash Memory (non-CFI) on LART.
15 * [1] 3 Volt Fast Boot Block Flash Memory" Intel Datasheet
25 * Block Flash Memory, it is rather specific to LART. With
54 * See section 2.3.1 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
62 * See section 2.3.2 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
92 * See section 4.0 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
106 * See section 4.2 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
/linux-4.1.27/arch/powerpc/platforms/pseries/
H A Dhotplug-memory.c2 * pseries Memory Hotplug infrastructure.
293 pr_err("Memory hot-remove failed, adding LMB's back\n"); dlpar_memory_remove_by_count()
313 pr_info("Memory at %llx was hot-removed\n", dlpar_memory_remove_by_count()
353 pr_info("Memory at %llx was hot-removed\n", lmbs[i].base_addr); dlpar_memory_remove_by_index()
480 pr_err("Memory hot-add failed, removing any added LMBs\n"); dlpar_memory_add_by_count()
497 pr_info("Memory at %llx (drc index %x) was hot-added\n", dlpar_memory_add_by_count()
534 pr_info("Memory at %llx (drc index %x) was hot-added\n", dlpar_memory_add_by_index()
/linux-4.1.27/drivers/firmware/efi/
H A Defi.c475 "Conventional Memory",
476 "Unusable Memory",
477 "ACPI Reclaim Memory",
478 "ACPI Memory NVS",
479 "Memory Mapped I/O",
/linux-4.1.27/drivers/video/fbdev/mbx/
H A Dreg_bits.h60 /* Memory clock control register */
122 /* LMRST - Local Memory (SDRAM) Reset */
125 /* LMCFG - Local Memory (SDRAM) Configuration Register */
133 /* LMPWR - Local Memory (SDRAM) Power Control Register */
139 /* LMPWRSTAT - Local Memory (SDRAM) Power Status Register */
145 /* LMTYPE - Local Memory (SDRAM) Type Register */
165 /* LMTIM - Local Memory (SDRAM) Timing Register */
177 /* LMREFRESH - Local Memory (SDRAM) tREF Control Register */
504 /* DMCTRL - Display Memory Control Register */
/linux-4.1.27/arch/blackfin/include/asm/
H A Ddef_LPBlackfin.h235 /* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
316 /* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
318 #define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
534 *Data Memory L1
540 #define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
542 #define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
551 * Data Memory L1
563 #define ENIM_P 0x00 /* Enable L1 Code Memory */
579 #define ENIM 0x00000001 /* Enable L1 Code Memory */
/linux-4.1.27/drivers/gpu/drm/i915/
H A Di915_gem_stolen.c51 /* Almost universally we can find the Graphics Base of Stolen Memory i915_stolen_to_physical()
56 * Memory (or Top of Usable DRAM). Note it appears that TOUD is only i915_stolen_to_physical()
64 /* Read Graphics Base of Stolen Memory directly */ i915_stolen_to_physical()
69 /* Stolen is immediately above Top of Memory */ i915_stolen_to_physical()
127 "Graphics Stolen Memory"); i915_stolen_to_physical()
139 "Graphics Stolen Memory"); i915_stolen_to_physical()
H A Di915_suspend.c121 /* Memory Arbitration state */ i915_save_state()
156 /* Memory arbitration state */ i915_restore_state()
/linux-4.1.27/arch/arm/mach-cns3xxx/
H A Dcns3xxx.h13 * Memory map
15 #define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */
18 #define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */
20 #define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
164 #define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
182 #define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */
/linux-4.1.27/drivers/net/wireless/prism54/
H A Disl_38xx.h43 /* PCI Memory Area */
117 /* Memory Manager definitions */
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Dplx9080.h110 #define RGN_MWS 0x0000003C /* Memory Access Wait States */
118 #define RGN_MRE 0x00000040 /* Memory Space Ready Input Enable */
119 #define RGN_MBE 0x00000080 /* Memory Space Bterm Input Enable */
126 #define RGN_MBEN 0x01000000 /* Memory Space Burst Enable */
140 #define DMM_MAE 0x00000001 /* Direct Mstr Memory Acc Enable */
198 #define CTL_RMEM 0x00000600 /* Memory Read Command */
199 #define CTL_WMEM 0x00007000 /* Memory Write Command */
335 #define MBX_MEMSZ_MASK 0xffff0000 /* PUTS Memory Size Register bits */
/linux-4.1.27/drivers/staging/fbtft/
H A Dfb_ili9340.c110 /* Memory write */ set_addr_win()
137 /* Memory Access Control */ set_var()
H A Dfb_s6d02a1.c114 /* Memory write */ set_addr_win()
125 /* MADCTL - Memory data access control set_var()
H A Dfb_st7735r.c108 /* Memory write */ set_addr_win()
119 /* MADCTL - Memory data access control set_var()
H A Dfb_ili9163.c57 #define CMD_RAMWR 0x2C /* Memory Write */
58 #define CMD_RAMRD 0x2E /* Memory Read */
64 #define CMD_MADCTL 0x36 /* Memory Access Control */
144 write_reg(par, CMD_RAMWR); /* Memory Write */ init_display()
/linux-4.1.27/drivers/gpio/
H A Dgpio-zevio.c22 * Memory layout:
27 * http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#90000000_-_General_Purpose_I.2FO_.28GPIO.29
H A Dgpio-iop.c30 /* Memory base offset */
/linux-4.1.27/arch/sparc/include/uapi/asm/
H A Dpstate.h17 #define PSTATE_MM _AC(0x00000000000000c0,UL) /* Memory Model. */
54 #define TSTATE_MM _AC(0x000000000000c000,UL) /* Memory Model. */
/linux-4.1.27/drivers/char/
H A Dbfin-otp.c2 * Blackfin On-Chip OTP Memory Interface
274 MODULE_DESCRIPTION("Blackfin OTP Memory Interface");
H A Duv_mmtimer.c33 MODULE_DESCRIPTION("SGI UV Memory Mapped RTC Timer");
38 #define UV_MMTIMER_DESC "SGI UV Memory Mapped RTC Timer"
/linux-4.1.27/include/ras/
H A Dras_event.h90 * Hardware-independent Memory Controller specific events
94 * Default error mechanisms for Memory Controller errors (CE and UE)
/linux-4.1.27/arch/powerpc/platforms/embedded6xx/
H A Dmpc10x.h26 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000
32 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000
/linux-4.1.27/arch/arm/mach-ep93xx/
H A Dsoc.h19 * EP93xx Physical Memory Map:
31 * There is known errata for the EP93xx dealing with External Memory
/linux-4.1.27/drivers/misc/mei/
H A Dhw-txe-regs.h136 * This register resides also in SeC's PCI-E Memory space.
178 * This register is both an ICR to Host from PCI Memory Space
192 /* This register is both an ICR to Host from PCI Memory Space
242 /* SEC Memory Space IPC output payload.
/linux-4.1.27/drivers/staging/lustre/include/linux/libcfs/
H A Dlibcfs_prim.h59 * Memory
/linux-4.1.27/drivers/net/wireless/ti/wl1251/
H A Dio.h70 /* Memory target IO, address is translated to partition 0 */
/linux-4.1.27/arch/xtensa/include/asm/
H A Dpci-bridge.h55 /* Host bridge I/O and Memory space
/linux-4.1.27/drivers/char/tpm/
H A Dtpm_acpi.c91 printk("%s: ERROR - Not enough Memory for BIOS measurements\n", read_log()
/linux-4.1.27/arch/mips/include/asm/mach-rc32434/
H A Dpci.h275 * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
397 #define KORINA_BAR0 0x00000008 /* 128 MB Memory */
401 #define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
/linux-4.1.27/arch/mips/include/asm/sgi/
H A Dmc.h6 * mc.h: Definitions for SGI Memory Controller
20 #define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */
101 volatile u32 mconfig0; /* Memory config register zero */
103 volatile u32 mconfig1; /* Memory config register one */
/linux-4.1.27/arch/arm/plat-omap/
H A Dsram.c39 * Memory allocator for SRAM: calculates the new ceiling address
/linux-4.1.27/arch/alpha/include/asm/
H A Dcore_polaris.h67 * Memory functions. Polaris allows all accesses (byte/word
/linux-4.1.27/include/linux/bcma/
H A Dbcma_driver_pci.h105 #define BCMA_CORE_PCI_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */
107 #define BCMA_CORE_PCI_SBTOPCI_RC_READ 0x00000000 /* Memory read */
108 #define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
109 #define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */

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