1/*
2 *  IBM eServer eHCA Infiniband device driver for Linux on POWER
3 *
4 *  eHCA register definitions
5 *
6 *  Authors: Waleri Fomin <fomin@de.ibm.com>
7 *           Christoph Raisch <raisch@de.ibm.com>
8 *           Reinhard Ernst <rernst@de.ibm.com>
9 *
10 *  Copyright (c) 2005 IBM Corporation
11 *
12 *  All rights reserved.
13 *
14 *  This source code is distributed under a dual license of GPL v2.0 and OpenIB
15 *  BSD.
16 *
17 * OpenIB BSD License
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are met:
21 *
22 * Redistributions of source code must retain the above copyright notice, this
23 * list of conditions and the following disclaimer.
24 *
25 * Redistributions in binary form must reproduce the above copyright notice,
26 * this list of conditions and the following disclaimer in the documentation
27 * and/or other materials
28 * provided with the distribution.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
34 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
35 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
36 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
37 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
38 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGE.
41 */
42
43#ifndef __HIPZ_HW_H__
44#define __HIPZ_HW_H__
45
46#include "ehca_tools.h"
47
48#define EHCA_MAX_MTU 4
49
50/* QP Table Entry Memory Map */
51struct hipz_qptemm {
52	u64 qpx_hcr;
53	u64 qpx_c;
54	u64 qpx_herr;
55	u64 qpx_aer;
56/* 0x20*/
57	u64 qpx_sqa;
58	u64 qpx_sqc;
59	u64 qpx_rqa;
60	u64 qpx_rqc;
61/* 0x40*/
62	u64 qpx_st;
63	u64 qpx_pmstate;
64	u64 qpx_pmfa;
65	u64 qpx_pkey;
66/* 0x60*/
67	u64 qpx_pkeya;
68	u64 qpx_pkeyb;
69	u64 qpx_pkeyc;
70	u64 qpx_pkeyd;
71/* 0x80*/
72	u64 qpx_qkey;
73	u64 qpx_dqp;
74	u64 qpx_dlidp;
75	u64 qpx_portp;
76/* 0xa0*/
77	u64 qpx_slidp;
78	u64 qpx_slidpp;
79	u64 qpx_dlida;
80	u64 qpx_porta;
81/* 0xc0*/
82	u64 qpx_slida;
83	u64 qpx_slidpa;
84	u64 qpx_slvl;
85	u64 qpx_ipd;
86/* 0xe0*/
87	u64 qpx_mtu;
88	u64 qpx_lato;
89	u64 qpx_rlimit;
90	u64 qpx_rnrlimit;
91/* 0x100*/
92	u64 qpx_t;
93	u64 qpx_sqhp;
94	u64 qpx_sqptp;
95	u64 qpx_nspsn;
96/* 0x120*/
97	u64 qpx_nspsnhwm;
98	u64 reserved1;
99	u64 qpx_sdsi;
100	u64 qpx_sdsbc;
101/* 0x140*/
102	u64 qpx_sqwsize;
103	u64 qpx_sqwts;
104	u64 qpx_lsn;
105	u64 qpx_nssn;
106/* 0x160 */
107	u64 qpx_mor;
108	u64 qpx_cor;
109	u64 qpx_sqsize;
110	u64 qpx_erc;
111/* 0x180*/
112	u64 qpx_rnrrc;
113	u64 qpx_ernrwt;
114	u64 qpx_rnrresp;
115	u64 qpx_lmsna;
116/* 0x1a0 */
117	u64 qpx_sqhpc;
118	u64 qpx_sqcptp;
119	u64 qpx_sigt;
120	u64 qpx_wqecnt;
121/* 0x1c0*/
122	u64 qpx_rqhp;
123	u64 qpx_rqptp;
124	u64 qpx_rqsize;
125	u64 qpx_nrr;
126/* 0x1e0*/
127	u64 qpx_rdmac;
128	u64 qpx_nrpsn;
129	u64 qpx_lapsn;
130	u64 qpx_lcr;
131/* 0x200*/
132	u64 qpx_rwc;
133	u64 qpx_rwva;
134	u64 qpx_rdsi;
135	u64 qpx_rdsbc;
136/* 0x220*/
137	u64 qpx_rqwsize;
138	u64 qpx_crmsn;
139	u64 qpx_rdd;
140	u64 qpx_larpsn;
141/* 0x240*/
142	u64 qpx_pd;
143	u64 qpx_scqn;
144	u64 qpx_rcqn;
145	u64 qpx_aeqn;
146/* 0x260*/
147	u64 qpx_aaelog;
148	u64 qpx_ram;
149	u64 qpx_rdmaqe0;
150	u64 qpx_rdmaqe1;
151/* 0x280*/
152	u64 qpx_rdmaqe2;
153	u64 qpx_rdmaqe3;
154	u64 qpx_nrpsnhwm;
155/* 0x298*/
156	u64 reserved[(0x400 - 0x298) / 8];
157/* 0x400 extended data */
158	u64 reserved_ext[(0x500 - 0x400) / 8];
159/* 0x500 */
160	u64 reserved2[(0x1000 - 0x500) / 8];
161/* 0x1000      */
162};
163
164#define QPX_SQADDER EHCA_BMASK_IBM(48, 63)
165#define QPX_RQADDER EHCA_BMASK_IBM(48, 63)
166#define QPX_AAELOG_RESET_SRQ_LIMIT EHCA_BMASK_IBM(3, 3)
167
168#define QPTEMM_OFFSET(x) offsetof(struct hipz_qptemm, x)
169
170/* MRMWPT Entry Memory Map */
171struct hipz_mrmwmm {
172	/* 0x00 */
173	u64 mrx_hcr;
174
175	u64 mrx_c;
176	u64 mrx_herr;
177	u64 mrx_aer;
178	/* 0x20 */
179	u64 mrx_pp;
180	u64 reserved1;
181	u64 reserved2;
182	u64 reserved3;
183	/* 0x40 */
184	u64 reserved4[(0x200 - 0x40) / 8];
185	/* 0x200 */
186	u64 mrx_ctl[64];
187
188};
189
190#define MRMWMM_OFFSET(x) offsetof(struct hipz_mrmwmm, x)
191
192struct hipz_qpedmm {
193	/* 0x00 */
194	u64 reserved0[(0x400) / 8];
195	/* 0x400 */
196	u64 qpedx_phh;
197	u64 qpedx_ppsgp;
198	/* 0x410 */
199	u64 qpedx_ppsgu;
200	u64 qpedx_ppdgp;
201	/* 0x420 */
202	u64 qpedx_ppdgu;
203	u64 qpedx_aph;
204	/* 0x430 */
205	u64 qpedx_apsgp;
206	u64 qpedx_apsgu;
207	/* 0x440 */
208	u64 qpedx_apdgp;
209	u64 qpedx_apdgu;
210	/* 0x450 */
211	u64 qpedx_apav;
212	u64 qpedx_apsav;
213	/* 0x460  */
214	u64 qpedx_hcr;
215	u64 reserved1[4];
216	/* 0x488 */
217	u64 qpedx_rrl0;
218	/* 0x490 */
219	u64 qpedx_rrrkey0;
220	u64 qpedx_rrva0;
221	/* 0x4a0 */
222	u64 reserved2;
223	u64 qpedx_rrl1;
224	/* 0x4b0 */
225	u64 qpedx_rrrkey1;
226	u64 qpedx_rrva1;
227	/* 0x4c0 */
228	u64 reserved3;
229	u64 qpedx_rrl2;
230	/* 0x4d0 */
231	u64 qpedx_rrrkey2;
232	u64 qpedx_rrva2;
233	/* 0x4e0 */
234	u64 reserved4;
235	u64 qpedx_rrl3;
236	/* 0x4f0 */
237	u64 qpedx_rrrkey3;
238	u64 qpedx_rrva3;
239};
240
241#define QPEDMM_OFFSET(x) offsetof(struct hipz_qpedmm, x)
242
243/* CQ Table Entry Memory Map */
244struct hipz_cqtemm {
245	u64 cqx_hcr;
246	u64 cqx_c;
247	u64 cqx_herr;
248	u64 cqx_aer;
249/* 0x20  */
250	u64 cqx_ptp;
251	u64 cqx_tp;
252	u64 cqx_fec;
253	u64 cqx_feca;
254/* 0x40  */
255	u64 cqx_ep;
256	u64 cqx_eq;
257/* 0x50  */
258	u64 reserved1;
259	u64 cqx_n0;
260/* 0x60  */
261	u64 cqx_n1;
262	u64 reserved2[(0x1000 - 0x60) / 8];
263/* 0x1000 */
264};
265
266#define CQX_FEC_CQE_CNT           EHCA_BMASK_IBM(32, 63)
267#define CQX_FECADDER              EHCA_BMASK_IBM(32, 63)
268#define CQX_N0_GENERATE_SOLICITED_COMP_EVENT EHCA_BMASK_IBM(0, 0)
269#define CQX_N1_GENERATE_COMP_EVENT EHCA_BMASK_IBM(0, 0)
270
271#define CQTEMM_OFFSET(x) offsetof(struct hipz_cqtemm, x)
272
273/* EQ Table Entry Memory Map */
274struct hipz_eqtemm {
275	u64 eqx_hcr;
276	u64 eqx_c;
277
278	u64 eqx_herr;
279	u64 eqx_aer;
280/* 0x20 */
281	u64 eqx_ptp;
282	u64 eqx_tp;
283	u64 eqx_ssba;
284	u64 eqx_psba;
285
286/* 0x40 */
287	u64 eqx_cec;
288	u64 eqx_meql;
289	u64 eqx_xisbi;
290	u64 eqx_xisc;
291/* 0x60 */
292	u64 eqx_it;
293
294};
295
296#define EQTEMM_OFFSET(x) offsetof(struct hipz_eqtemm, x)
297
298/* access control defines for MR/MW */
299#define HIPZ_ACCESSCTRL_L_WRITE  0x00800000
300#define HIPZ_ACCESSCTRL_R_WRITE  0x00400000
301#define HIPZ_ACCESSCTRL_R_READ   0x00200000
302#define HIPZ_ACCESSCTRL_R_ATOMIC 0x00100000
303#define HIPZ_ACCESSCTRL_MW_BIND  0x00080000
304
305/* query hca response block */
306struct hipz_query_hca {
307	u32 cur_reliable_dg;
308	u32 cur_qp;
309	u32 cur_cq;
310	u32 cur_eq;
311	u32 cur_mr;
312	u32 cur_mw;
313	u32 cur_ee_context;
314	u32 cur_mcast_grp;
315	u32 cur_qp_attached_mcast_grp;
316	u32 reserved1;
317	u32 cur_ipv6_qp;
318	u32 cur_eth_qp;
319	u32 cur_hp_mr;
320	u32 reserved2[3];
321	u32 max_rd_domain;
322	u32 max_qp;
323	u32 max_cq;
324	u32 max_eq;
325	u32 max_mr;
326	u32 max_hp_mr;
327	u32 max_mw;
328	u32 max_mrwpte;
329	u32 max_special_mrwpte;
330	u32 max_rd_ee_context;
331	u32 max_mcast_grp;
332	u32 max_total_mcast_qp_attach;
333	u32 max_mcast_qp_attach;
334	u32 max_raw_ipv6_qp;
335	u32 max_raw_ethy_qp;
336	u32 internal_clock_frequency;
337	u32 max_pd;
338	u32 max_ah;
339	u32 max_cqe;
340	u32 max_wqes_wq;
341	u32 max_partitions;
342	u32 max_rr_ee_context;
343	u32 max_rr_qp;
344	u32 max_rr_hca;
345	u32 max_act_wqs_ee_context;
346	u32 max_act_wqs_qp;
347	u32 max_sge;
348	u32 max_sge_rd;
349	u32 memory_page_size_supported;
350	u64 max_mr_size;
351	u32 local_ca_ack_delay;
352	u32 num_ports;
353	u32 vendor_id;
354	u32 vendor_part_id;
355	u32 hw_ver;
356	u64 node_guid;
357	u64 hca_cap_indicators;
358	u32 data_counter_register_size;
359	u32 max_shared_rq;
360	u32 max_isns_eq;
361	u32 max_neq;
362} __attribute__ ((packed));
363
364#define HCA_CAP_AH_PORT_NR_CHECK      EHCA_BMASK_IBM( 0,  0)
365#define HCA_CAP_ATOMIC                EHCA_BMASK_IBM( 1,  1)
366#define HCA_CAP_AUTO_PATH_MIG         EHCA_BMASK_IBM( 2,  2)
367#define HCA_CAP_BAD_P_KEY_CTR         EHCA_BMASK_IBM( 3,  3)
368#define HCA_CAP_SQD_RTS_PORT_CHANGE   EHCA_BMASK_IBM( 4,  4)
369#define HCA_CAP_CUR_QP_STATE_MOD      EHCA_BMASK_IBM( 5,  5)
370#define HCA_CAP_INIT_TYPE             EHCA_BMASK_IBM( 6,  6)
371#define HCA_CAP_PORT_ACTIVE_EVENT     EHCA_BMASK_IBM( 7,  7)
372#define HCA_CAP_Q_KEY_VIOL_CTR        EHCA_BMASK_IBM( 8,  8)
373#define HCA_CAP_WQE_RESIZE            EHCA_BMASK_IBM( 9,  9)
374#define HCA_CAP_RAW_PACKET_MCAST      EHCA_BMASK_IBM(10, 10)
375#define HCA_CAP_SHUTDOWN_PORT         EHCA_BMASK_IBM(11, 11)
376#define HCA_CAP_RC_LL_QP              EHCA_BMASK_IBM(12, 12)
377#define HCA_CAP_SRQ                   EHCA_BMASK_IBM(13, 13)
378#define HCA_CAP_UD_LL_QP              EHCA_BMASK_IBM(16, 16)
379#define HCA_CAP_RESIZE_MR             EHCA_BMASK_IBM(17, 17)
380#define HCA_CAP_MINI_QP               EHCA_BMASK_IBM(18, 18)
381#define HCA_CAP_H_ALLOC_RES_SYNC      EHCA_BMASK_IBM(19, 19)
382
383/* query port response block */
384struct hipz_query_port {
385	u32 state;
386	u32 bad_pkey_cntr;
387	u32 lmc;
388	u32 lid;
389	u32 subnet_timeout;
390	u32 qkey_viol_cntr;
391	u32 sm_sl;
392	u32 sm_lid;
393	u32 capability_mask;
394	u32 init_type_reply;
395	u32 pkey_tbl_len;
396	u32 gid_tbl_len;
397	u64 gid_prefix;
398	u32 port_nr;
399	u16 pkey_entries[16];
400	u8  reserved1[32];
401	u32 trent_size;
402	u32 trbuf_size;
403	u64 max_msg_sz;
404	u32 max_mtu;
405	u32 vl_cap;
406	u32 phys_pstate;
407	u32 phys_state;
408	u32 phys_speed;
409	u32 phys_width;
410	u8  reserved2[1884];
411	u64 guid_entries[255];
412} __attribute__ ((packed));
413
414#endif
415