1/*
2 * DO NOT EDIT THIS FILE
3 * This file is under version control at
4 *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE
7 *
8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the Clear BSD license.
10 */
11
12/* This file should be up to date with:
13 *  - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
14 */
15
16#ifndef _MACH_ANOMALY_H_
17#define _MACH_ANOMALY_H_
18
19/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
20#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
21# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
22#endif
23
24/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
25#define ANOMALY_05000074 (1)
26/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
27#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
28/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
29#define ANOMALY_05000120 (1)
30/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
31#define ANOMALY_05000122 (1)
32/* SIGNBITS Instruction Not Functional under Certain Conditions */
33#define ANOMALY_05000127 (1)
34/* IMDMA S1/D1 Channel May Stall */
35#define ANOMALY_05000149 (1)
36/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
37#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
38/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
39#define ANOMALY_05000166 (1)
40/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
41#define ANOMALY_05000167 (1)
42/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
43#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
44/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
45#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
46/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
47#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
48/* Cache Fill Buffer Data lost */
49#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
50/* Overlapping Sequencer and Memory Stalls */
51#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
52/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
53#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
54/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
55#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
56/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
57#define ANOMALY_05000180 (1)
58/* Disabling the PPI Resets the PPI Configuration Registers */
59#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
60/* Internal Memory DMA Does Not Operate at Full Speed */
61#define ANOMALY_05000182 (1)
62/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
63#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
64/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
65#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
66/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */
67#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
68/* IMDMA Corrupted Data after a Halt */
69#define ANOMALY_05000187 (1)
70/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
71#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
72/* False Protection Exceptions when Speculative Fetch Is Cancelled */
73#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
74/* PPI Not Functional at Core Voltage < 1Volt */
75#define ANOMALY_05000190 (1)
76/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
77#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
78/* Restarting SPORT in Specific Modes May Cause Data Corruption */
79#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
80/* Failing MMR Accesses when Preceding Memory Read Stalls */
81#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
82/* Current DMA Address Shows Wrong Value During Carry Fix */
83#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
84/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
85#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
86/* Possible Infinite Stall with Specific Dual-DAG Situation */
87#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
88/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
89#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
90/* Specific Sequence that Can Cause DMA Error or DMA Stopping */
91#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
92/* Recovery from "Brown-Out" Condition */
93#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
94/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
95#define ANOMALY_05000208 (1)
96/* Speed Path in Computational Unit Affects Certain Instructions */
97#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
98/* UART TX Interrupt Masked Erroneously */
99#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
100/* NMI Event at Boot Time Results in Unpredictable State */
101#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
102/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
103#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
104/* Incorrect Pulse-Width of UART Start Bit */
105#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
106/* Scratchpad Memory Bank Reads May Return Incorrect Data */
107#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
108/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
109#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
110/* UART STB Bit Incorrectly Affects Receiver Setting */
111#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
112/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
113#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
114/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
115#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
116/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
117#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
118/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
119#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
120/* TESTSET Operation Forces Stall on the Other Core */
121#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
122/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
123#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
124/* Exception Not Generated for MMR Accesses in Reserved Region */
125#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
126/* Maximum External Clock Speed for Timers */
127#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
128/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
129#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
130/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
131/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception
132 * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change
133 * after the behavior and the root cause are confirmed with hardware team.
134 */
135#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP))
136/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
137#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
138/* ICPLB_STATUS MMR Register May Be Corrupted */
139#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
140/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
141#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
142/* Stores To Data Cache May Be Lost */
143#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
144/* Hardware Loop Corrupted When Taking an ICPLB Exception */
145#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
146/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
147#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
148/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
149#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
150/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */
151#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
152/* IMDMA May Corrupt Data under Certain Conditions */
153#define ANOMALY_05000267 (1)
154/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
155#define ANOMALY_05000269 (1)
156/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
157#define ANOMALY_05000270 (1)
158/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
159#define ANOMALY_05000272 (1)
160/* Data Cache Write Back to External Synchronous Memory May Be Lost */
161#define ANOMALY_05000274 (1)
162/* PPI Timing and Sampling Information Updates */
163#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
164/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
165#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
166/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
167#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
168/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
169#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
170/* False Hardware Error when ISR Context Is Not Restored */
171/* Temporarily walk around for bug 5423 till this issue is confirmed by
172 * official anomaly document. It looks 05000281 still exists on bf561
173 * v0.5.
174 */
175#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5)
176/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
177#define ANOMALY_05000283 (1)
178/* Reads Will Receive Incorrect Data under Certain Conditions */
179#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
180/* SPORTs May Receive Bad Data If FIFOs Fill Up */
181#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
182/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
183#define ANOMALY_05000301 (1)
184/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
185#define ANOMALY_05000302 (1)
186/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
187#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
188/* SCKELOW Bit Does Not Maintain State Through Hibernate */
189#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
190/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
191#define ANOMALY_05000310 (1)
192/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
193#define ANOMALY_05000312 (1)
194/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
195#define ANOMALY_05000313 (1)
196/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
197#define ANOMALY_05000315 (1)
198/* PF2 Output Remains Asserted after SPI Master Boot */
199#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
200/* Erroneous GPIO Flag Pin Operations under Specific Sequences */
201#define ANOMALY_05000323 (1)
202/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */
203#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
204/* 24-Bit SPI Boot Mode Is Not Functional */
205#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
206/* Slave SPI Boot Mode Is Not Functional */
207#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
208/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */
209#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
210/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */
211#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
212/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
213#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
214/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
215#define ANOMALY_05000357 (1)
216/* Conflicting Column Address Widths Causes SDRAM Errors */
217#define ANOMALY_05000362 (1)
218/* UART Break Signal Issues */
219#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
220/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
221#define ANOMALY_05000366 (1)
222/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
223#define ANOMALY_05000371 (1)
224/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
225#define ANOMALY_05000403 (1)
226/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
227#define ANOMALY_05000412 (1)
228/* Speculative Fetches Can Cause Undesired External FIFO Operations */
229#define ANOMALY_05000416 (1)
230/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
231#define ANOMALY_05000425 (1)
232/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
233#define ANOMALY_05000426 (1)
234/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
235#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
236/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
237#define ANOMALY_05000443 (1)
238/* SCKELOW Feature Is Not Functional */
239#define ANOMALY_05000458 (1)
240/* False Hardware Error when RETI Points to Invalid Memory */
241#define ANOMALY_05000461 (1)
242/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
243#define ANOMALY_05000462 (1)
244/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
245#define ANOMALY_05000471 (1)
246/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
247#define ANOMALY_05000473 (1)
248/* Possible Lockup Condition when Modifying PLL from External Memory */
249#define ANOMALY_05000475 (1)
250/* TESTSET Instruction Cannot Be Interrupted */
251#define ANOMALY_05000477 (1)
252/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
253#define ANOMALY_05000481 (1)
254/* PLL May Latch Incorrect Values Coming Out of Reset */
255#define ANOMALY_05000489 (1)
256/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
257#define ANOMALY_05000491 (1)
258/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
259#define ANOMALY_05000494 (1)
260/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
261#define ANOMALY_05000501 (1)
262
263/*
264 * These anomalies have been "phased" out of analog.com anomaly sheets and are
265 * here to show running on older silicon just isn't feasible.
266 */
267
268/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
269#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
270/* Erroneous Exception when Enabling Cache */
271#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
272/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
273#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
274/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
275#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
276/* Stall in multi-unit DMA operations */
277#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
278/* Allowing the SPORT RX FIFO to fill will cause an overflow */
279#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
280/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
281#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
282/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
283#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
284/* DMA and TESTSET conflict when both are accessing external memory */
285#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
286/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
287#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
288/* MDMA may lose the first few words of a descriptor chain */
289#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
290/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
291#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
292/* DMA engine may lose data due to incorrect handshaking */
293#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
294/* DMA stalls when all three controllers read data from the same source */
295#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
296/* Execution stall when executing in L2 and doing external accesses */
297#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
298/* Frame Delay in SPORT Multichannel Mode */
299#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
300/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
301#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
302/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
303#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
304/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
305#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
306/* A read from external memory may return a wrong value with data cache enabled */
307#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
308/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
309#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
310/* DMEM_CONTROL<12> is not set on Reset */
311#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
312/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
313#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
314/* DSPID register values incorrect */
315#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
316/* DMA vs Core accesses to external memory */
317#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
318/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
319#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
320/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
321#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
322
323/* Anomalies that don't exist on this proc */
324#define ANOMALY_05000119 (0)
325#define ANOMALY_05000158 (0)
326#define ANOMALY_05000183 (0)
327#define ANOMALY_05000233 (0)
328#define ANOMALY_05000234 (0)
329#define ANOMALY_05000273 (0)
330#define ANOMALY_05000311 (0)
331#define ANOMALY_05000353 (1)
332#define ANOMALY_05000364 (0)
333#define ANOMALY_05000380 (0)
334#define ANOMALY_05000383 (0)
335#define ANOMALY_05000386 (1)
336#define ANOMALY_05000389 (0)
337#define ANOMALY_05000400 (0)
338#define ANOMALY_05000430 (0)
339#define ANOMALY_05000432 (0)
340#define ANOMALY_05000435 (0)
341#define ANOMALY_05000440 (0)
342#define ANOMALY_05000447 (0)
343#define ANOMALY_05000448 (0)
344#define ANOMALY_05000456 (0)
345#define ANOMALY_05000450 (0)
346#define ANOMALY_05000465 (0)
347#define ANOMALY_05000467 (0)
348#define ANOMALY_05000474 (0)
349#define ANOMALY_05000480 (0)
350#define ANOMALY_05000485 (0)
351#define ANOMALY_16000030 (0)
352
353#endif
354