1/* 2 * CPM2 Internal Memory Map 3 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) 4 * 5 * The Internal Memory Map for devices with CPM2 on them. This 6 * is the superset of all CPM2 devices (8260, 8266, 8280, 8272, 7 * 8560). 8 */ 9#ifdef __KERNEL__ 10#ifndef __IMMAP_CPM2__ 11#define __IMMAP_CPM2__ 12 13#include <linux/types.h> 14 15/* System configuration registers. 16*/ 17typedef struct sys_82xx_conf { 18 u32 sc_siumcr; 19 u32 sc_sypcr; 20 u8 res1[6]; 21 u16 sc_swsr; 22 u8 res2[20]; 23 u32 sc_bcr; 24 u8 sc_ppc_acr; 25 u8 res3[3]; 26 u32 sc_ppc_alrh; 27 u32 sc_ppc_alrl; 28 u8 sc_lcl_acr; 29 u8 res4[3]; 30 u32 sc_lcl_alrh; 31 u32 sc_lcl_alrl; 32 u32 sc_tescr1; 33 u32 sc_tescr2; 34 u32 sc_ltescr1; 35 u32 sc_ltescr2; 36 u32 sc_pdtea; 37 u8 sc_pdtem; 38 u8 res5[3]; 39 u32 sc_ldtea; 40 u8 sc_ldtem; 41 u8 res6[163]; 42} sysconf_82xx_cpm2_t; 43 44typedef struct sys_85xx_conf { 45 u32 sc_cear; 46 u16 sc_ceer; 47 u16 sc_cemr; 48 u8 res1[70]; 49 u32 sc_smaer; 50 u8 res2[4]; 51 u32 sc_smevr; 52 u32 sc_smctr; 53 u32 sc_lmaer; 54 u8 res3[4]; 55 u32 sc_lmevr; 56 u32 sc_lmctr; 57 u8 res4[144]; 58} sysconf_85xx_cpm2_t; 59 60typedef union sys_conf { 61 sysconf_82xx_cpm2_t siu_82xx; 62 sysconf_85xx_cpm2_t siu_85xx; 63} sysconf_cpm2_t; 64 65 66 67/* Memory controller registers. 68*/ 69typedef struct mem_ctlr { 70 u32 memc_br0; 71 u32 memc_or0; 72 u32 memc_br1; 73 u32 memc_or1; 74 u32 memc_br2; 75 u32 memc_or2; 76 u32 memc_br3; 77 u32 memc_or3; 78 u32 memc_br4; 79 u32 memc_or4; 80 u32 memc_br5; 81 u32 memc_or5; 82 u32 memc_br6; 83 u32 memc_or6; 84 u32 memc_br7; 85 u32 memc_or7; 86 u32 memc_br8; 87 u32 memc_or8; 88 u32 memc_br9; 89 u32 memc_or9; 90 u32 memc_br10; 91 u32 memc_or10; 92 u32 memc_br11; 93 u32 memc_or11; 94 u8 res1[8]; 95 u32 memc_mar; 96 u8 res2[4]; 97 u32 memc_mamr; 98 u32 memc_mbmr; 99 u32 memc_mcmr; 100 u8 res3[8]; 101 u16 memc_mptpr; 102 u8 res4[2]; 103 u32 memc_mdr; 104 u8 res5[4]; 105 u32 memc_psdmr; 106 u32 memc_lsdmr; 107 u8 memc_purt; 108 u8 res6[3]; 109 u8 memc_psrt; 110 u8 res7[3]; 111 u8 memc_lurt; 112 u8 res8[3]; 113 u8 memc_lsrt; 114 u8 res9[3]; 115 u32 memc_immr; 116 u32 memc_pcibr0; 117 u32 memc_pcibr1; 118 u8 res10[16]; 119 u32 memc_pcimsk0; 120 u32 memc_pcimsk1; 121 u8 res11[52]; 122} memctl_cpm2_t; 123 124/* System Integration Timers. 125*/ 126typedef struct sys_int_timers { 127 u8 res1[32]; 128 u16 sit_tmcntsc; 129 u8 res2[2]; 130 u32 sit_tmcnt; 131 u8 res3[4]; 132 u32 sit_tmcntal; 133 u8 res4[16]; 134 u16 sit_piscr; 135 u8 res5[2]; 136 u32 sit_pitc; 137 u32 sit_pitr; 138 u8 res6[94]; 139 u8 res7[390]; 140} sit_cpm2_t; 141 142#define PISCR_PIRQ_MASK ((u16)0xff00) 143#define PISCR_PS ((u16)0x0080) 144#define PISCR_PIE ((u16)0x0004) 145#define PISCR_PTF ((u16)0x0002) 146#define PISCR_PTE ((u16)0x0001) 147 148/* PCI Controller. 149*/ 150typedef struct pci_ctlr { 151 u32 pci_omisr; 152 u32 pci_omimr; 153 u8 res1[8]; 154 u32 pci_ifqpr; 155 u32 pci_ofqpr; 156 u8 res2[8]; 157 u32 pci_imr0; 158 u32 pci_imr1; 159 u32 pci_omr0; 160 u32 pci_omr1; 161 u32 pci_odr; 162 u8 res3[4]; 163 u32 pci_idr; 164 u8 res4[20]; 165 u32 pci_imisr; 166 u32 pci_imimr; 167 u8 res5[24]; 168 u32 pci_ifhpr; 169 u8 res6[4]; 170 u32 pci_iftpr; 171 u8 res7[4]; 172 u32 pci_iphpr; 173 u8 res8[4]; 174 u32 pci_iptpr; 175 u8 res9[4]; 176 u32 pci_ofhpr; 177 u8 res10[4]; 178 u32 pci_oftpr; 179 u8 res11[4]; 180 u32 pci_ophpr; 181 u8 res12[4]; 182 u32 pci_optpr; 183 u8 res13[8]; 184 u32 pci_mucr; 185 u8 res14[8]; 186 u32 pci_qbar; 187 u8 res15[12]; 188 u32 pci_dmamr0; 189 u32 pci_dmasr0; 190 u32 pci_dmacdar0; 191 u8 res16[4]; 192 u32 pci_dmasar0; 193 u8 res17[4]; 194 u32 pci_dmadar0; 195 u8 res18[4]; 196 u32 pci_dmabcr0; 197 u32 pci_dmandar0; 198 u8 res19[86]; 199 u32 pci_dmamr1; 200 u32 pci_dmasr1; 201 u32 pci_dmacdar1; 202 u8 res20[4]; 203 u32 pci_dmasar1; 204 u8 res21[4]; 205 u32 pci_dmadar1; 206 u8 res22[4]; 207 u32 pci_dmabcr1; 208 u32 pci_dmandar1; 209 u8 res23[88]; 210 u32 pci_dmamr2; 211 u32 pci_dmasr2; 212 u32 pci_dmacdar2; 213 u8 res24[4]; 214 u32 pci_dmasar2; 215 u8 res25[4]; 216 u32 pci_dmadar2; 217 u8 res26[4]; 218 u32 pci_dmabcr2; 219 u32 pci_dmandar2; 220 u8 res27[88]; 221 u32 pci_dmamr3; 222 u32 pci_dmasr3; 223 u32 pci_dmacdar3; 224 u8 res28[4]; 225 u32 pci_dmasar3; 226 u8 res29[4]; 227 u32 pci_dmadar3; 228 u8 res30[4]; 229 u32 pci_dmabcr3; 230 u32 pci_dmandar3; 231 u8 res31[344]; 232 u32 pci_potar0; 233 u8 res32[4]; 234 u32 pci_pobar0; 235 u8 res33[4]; 236 u32 pci_pocmr0; 237 u8 res34[4]; 238 u32 pci_potar1; 239 u8 res35[4]; 240 u32 pci_pobar1; 241 u8 res36[4]; 242 u32 pci_pocmr1; 243 u8 res37[4]; 244 u32 pci_potar2; 245 u8 res38[4]; 246 u32 pci_pobar2; 247 u8 res39[4]; 248 u32 pci_pocmr2; 249 u8 res40[50]; 250 u32 pci_ptcr; 251 u32 pci_gpcr; 252 u32 pci_gcr; 253 u32 pci_esr; 254 u32 pci_emr; 255 u32 pci_ecr; 256 u32 pci_eacr; 257 u8 res41[4]; 258 u32 pci_edcr; 259 u8 res42[4]; 260 u32 pci_eccr; 261 u8 res43[44]; 262 u32 pci_pitar1; 263 u8 res44[4]; 264 u32 pci_pibar1; 265 u8 res45[4]; 266 u32 pci_picmr1; 267 u8 res46[4]; 268 u32 pci_pitar0; 269 u8 res47[4]; 270 u32 pci_pibar0; 271 u8 res48[4]; 272 u32 pci_picmr0; 273 u8 res49[4]; 274 u32 pci_cfg_addr; 275 u32 pci_cfg_data; 276 u32 pci_int_ack; 277 u8 res50[756]; 278} pci_cpm2_t; 279 280/* Interrupt Controller. 281*/ 282typedef struct interrupt_controller { 283 u16 ic_sicr; 284 u8 res1[2]; 285 u32 ic_sivec; 286 u32 ic_sipnrh; 287 u32 ic_sipnrl; 288 u32 ic_siprr; 289 u32 ic_scprrh; 290 u32 ic_scprrl; 291 u32 ic_simrh; 292 u32 ic_simrl; 293 u32 ic_siexr; 294 u8 res2[88]; 295} intctl_cpm2_t; 296 297/* Clocks and Reset. 298*/ 299typedef struct clk_and_reset { 300 u32 car_sccr; 301 u8 res1[4]; 302 u32 car_scmr; 303 u8 res2[4]; 304 u32 car_rsr; 305 u32 car_rmr; 306 u8 res[104]; 307} car_cpm2_t; 308 309/* Input/Output Port control/status registers. 310 * Names consistent with processor manual, although they are different 311 * from the original 8xx names....... 312 */ 313typedef struct io_port { 314 u32 iop_pdira; 315 u32 iop_ppara; 316 u32 iop_psora; 317 u32 iop_podra; 318 u32 iop_pdata; 319 u8 res1[12]; 320 u32 iop_pdirb; 321 u32 iop_pparb; 322 u32 iop_psorb; 323 u32 iop_podrb; 324 u32 iop_pdatb; 325 u8 res2[12]; 326 u32 iop_pdirc; 327 u32 iop_pparc; 328 u32 iop_psorc; 329 u32 iop_podrc; 330 u32 iop_pdatc; 331 u8 res3[12]; 332 u32 iop_pdird; 333 u32 iop_ppard; 334 u32 iop_psord; 335 u32 iop_podrd; 336 u32 iop_pdatd; 337 u8 res4[12]; 338} iop_cpm2_t; 339 340/* Communication Processor Module Timers 341*/ 342typedef struct cpm_timers { 343 u8 cpmt_tgcr1; 344 u8 res1[3]; 345 u8 cpmt_tgcr2; 346 u8 res2[11]; 347 u16 cpmt_tmr1; 348 u16 cpmt_tmr2; 349 u16 cpmt_trr1; 350 u16 cpmt_trr2; 351 u16 cpmt_tcr1; 352 u16 cpmt_tcr2; 353 u16 cpmt_tcn1; 354 u16 cpmt_tcn2; 355 u16 cpmt_tmr3; 356 u16 cpmt_tmr4; 357 u16 cpmt_trr3; 358 u16 cpmt_trr4; 359 u16 cpmt_tcr3; 360 u16 cpmt_tcr4; 361 u16 cpmt_tcn3; 362 u16 cpmt_tcn4; 363 u16 cpmt_ter1; 364 u16 cpmt_ter2; 365 u16 cpmt_ter3; 366 u16 cpmt_ter4; 367 u8 res3[584]; 368} cpmtimer_cpm2_t; 369 370/* DMA control/status registers. 371*/ 372typedef struct sdma_csr { 373 u8 res0[24]; 374 u8 sdma_sdsr; 375 u8 res1[3]; 376 u8 sdma_sdmr; 377 u8 res2[3]; 378 u8 sdma_idsr1; 379 u8 res3[3]; 380 u8 sdma_idmr1; 381 u8 res4[3]; 382 u8 sdma_idsr2; 383 u8 res5[3]; 384 u8 sdma_idmr2; 385 u8 res6[3]; 386 u8 sdma_idsr3; 387 u8 res7[3]; 388 u8 sdma_idmr3; 389 u8 res8[3]; 390 u8 sdma_idsr4; 391 u8 res9[3]; 392 u8 sdma_idmr4; 393 u8 res10[707]; 394} sdma_cpm2_t; 395 396/* Fast controllers 397*/ 398typedef struct fcc { 399 u32 fcc_gfmr; 400 u32 fcc_fpsmr; 401 u16 fcc_ftodr; 402 u8 res1[2]; 403 u16 fcc_fdsr; 404 u8 res2[2]; 405 u16 fcc_fcce; 406 u8 res3[2]; 407 u16 fcc_fccm; 408 u8 res4[2]; 409 u8 fcc_fccs; 410 u8 res5[3]; 411 u8 fcc_ftirr_phy[4]; 412} fcc_t; 413 414/* Fast controllers continued 415 */ 416typedef struct fcc_c { 417 u32 fcc_firper; 418 u32 fcc_firer; 419 u32 fcc_firsr_hi; 420 u32 fcc_firsr_lo; 421 u8 fcc_gfemr; 422 u8 res1[15]; 423} fcc_c_t; 424 425/* TC Layer 426 */ 427typedef struct tclayer { 428 u16 tc_tcmode; 429 u16 tc_cdsmr; 430 u16 tc_tcer; 431 u16 tc_rcc; 432 u16 tc_tcmr; 433 u16 tc_fcc; 434 u16 tc_ccc; 435 u16 tc_icc; 436 u16 tc_tcc; 437 u16 tc_ecc; 438 u8 res1[12]; 439} tclayer_t; 440 441 442/* I2C 443*/ 444typedef struct i2c { 445 u8 i2c_i2mod; 446 u8 res1[3]; 447 u8 i2c_i2add; 448 u8 res2[3]; 449 u8 i2c_i2brg; 450 u8 res3[3]; 451 u8 i2c_i2com; 452 u8 res4[3]; 453 u8 i2c_i2cer; 454 u8 res5[3]; 455 u8 i2c_i2cmr; 456 u8 res6[331]; 457} i2c_cpm2_t; 458 459typedef struct scc { /* Serial communication channels */ 460 u32 scc_gsmrl; 461 u32 scc_gsmrh; 462 u16 scc_psmr; 463 u8 res1[2]; 464 u16 scc_todr; 465 u16 scc_dsr; 466 u16 scc_scce; 467 u8 res2[2]; 468 u16 scc_sccm; 469 u8 res3; 470 u8 scc_sccs; 471 u8 res4[8]; 472} scc_t; 473 474typedef struct smc { /* Serial management channels */ 475 u8 res1[2]; 476 u16 smc_smcmr; 477 u8 res2[2]; 478 u8 smc_smce; 479 u8 res3[3]; 480 u8 smc_smcm; 481 u8 res4[5]; 482} smc_t; 483 484/* Serial Peripheral Interface. 485*/ 486typedef struct spi_ctrl { 487 u16 spi_spmode; 488 u8 res1[4]; 489 u8 spi_spie; 490 u8 res2[3]; 491 u8 spi_spim; 492 u8 res3[2]; 493 u8 spi_spcom; 494 u8 res4[82]; 495} spictl_cpm2_t; 496 497/* CPM Mux. 498*/ 499typedef struct cpmux { 500 u8 cmx_si1cr; 501 u8 res1; 502 u8 cmx_si2cr; 503 u8 res2; 504 u32 cmx_fcr; 505 u32 cmx_scr; 506 u8 cmx_smr; 507 u8 res3; 508 u16 cmx_uar; 509 u8 res4[16]; 510} cpmux_t; 511 512/* SIRAM control 513*/ 514typedef struct siram { 515 u16 si_amr; 516 u16 si_bmr; 517 u16 si_cmr; 518 u16 si_dmr; 519 u8 si_gmr; 520 u8 res1; 521 u8 si_cmdr; 522 u8 res2; 523 u8 si_str; 524 u8 res3; 525 u16 si_rsr; 526} siramctl_t; 527 528typedef struct mcc { 529 u16 mcc_mcce; 530 u8 res1[2]; 531 u16 mcc_mccm; 532 u8 res2[2]; 533 u8 mcc_mccf; 534 u8 res3[7]; 535} mcc_t; 536 537typedef struct comm_proc { 538 u32 cp_cpcr; 539 u32 cp_rccr; 540 u8 res1[14]; 541 u16 cp_rter; 542 u8 res2[2]; 543 u16 cp_rtmr; 544 u16 cp_rtscr; 545 u8 res3[2]; 546 u32 cp_rtsr; 547 u8 res4[12]; 548} cpm_cpm2_t; 549 550/* USB Controller. 551*/ 552typedef struct cpm_usb_ctlr { 553 u8 usb_usmod; 554 u8 usb_usadr; 555 u8 usb_uscom; 556 u8 res1[1]; 557 __be16 usb_usep[4]; 558 u8 res2[4]; 559 __be16 usb_usber; 560 u8 res3[2]; 561 __be16 usb_usbmr; 562 u8 usb_usbs; 563 u8 res4[7]; 564} usb_cpm2_t; 565 566/* ...and the whole thing wrapped up.... 567*/ 568 569typedef struct immap { 570 /* Some references are into the unique and known dpram spaces, 571 * others are from the generic base. 572 */ 573#define im_dprambase im_dpram1 574 u8 im_dpram1[16*1024]; 575 u8 res1[16*1024]; 576 u8 im_dpram2[4*1024]; 577 u8 res2[8*1024]; 578 u8 im_dpram3[4*1024]; 579 u8 res3[16*1024]; 580 581 sysconf_cpm2_t im_siu_conf; /* SIU Configuration */ 582 memctl_cpm2_t im_memctl; /* Memory Controller */ 583 sit_cpm2_t im_sit; /* System Integration Timers */ 584 pci_cpm2_t im_pci; /* PCI Controller */ 585 intctl_cpm2_t im_intctl; /* Interrupt Controller */ 586 car_cpm2_t im_clkrst; /* Clocks and reset */ 587 iop_cpm2_t im_ioport; /* IO Port control/status */ 588 cpmtimer_cpm2_t im_cpmtimer; /* CPM timers */ 589 sdma_cpm2_t im_sdma; /* SDMA control/status */ 590 591 fcc_t im_fcc[3]; /* Three FCCs */ 592 u8 res4z[32]; 593 fcc_c_t im_fcc_c[3]; /* Continued FCCs */ 594 595 u8 res4[32]; 596 597 tclayer_t im_tclayer[8]; /* Eight TCLayers */ 598 u16 tc_tcgsr; 599 u16 tc_tcger; 600 601 /* First set of baud rate generators. 602 */ 603 u8 res[236]; 604 u32 im_brgc5; 605 u32 im_brgc6; 606 u32 im_brgc7; 607 u32 im_brgc8; 608 609 u8 res5[608]; 610 611 i2c_cpm2_t im_i2c; /* I2C control/status */ 612 cpm_cpm2_t im_cpm; /* Communication processor */ 613 614 /* Second set of baud rate generators. 615 */ 616 u32 im_brgc1; 617 u32 im_brgc2; 618 u32 im_brgc3; 619 u32 im_brgc4; 620 621 scc_t im_scc[4]; /* Four SCCs */ 622 smc_t im_smc[2]; /* Couple of SMCs */ 623 spictl_cpm2_t im_spi; /* A SPI */ 624 cpmux_t im_cpmux; /* CPM clock route mux */ 625 siramctl_t im_siramctl1; /* First SI RAM Control */ 626 mcc_t im_mcc1; /* First MCC */ 627 siramctl_t im_siramctl2; /* Second SI RAM Control */ 628 mcc_t im_mcc2; /* Second MCC */ 629 usb_cpm2_t im_usb; /* USB Controller */ 630 631 u8 res6[1153]; 632 633 u16 im_si1txram[256]; 634 u8 res7[512]; 635 u16 im_si1rxram[256]; 636 u8 res8[512]; 637 u16 im_si2txram[256]; 638 u8 res9[512]; 639 u16 im_si2rxram[256]; 640 u8 res10[512]; 641 u8 res11[4096]; 642} cpm2_map_t; 643 644extern cpm2_map_t __iomem *cpm2_immr; 645 646#endif /* __IMMAP_CPM2__ */ 647#endif /* __KERNEL__ */ 648