1/*
2 * arch/xtensa/platform/xtavnet/include/platform/hardware.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License.  See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2006 Tensilica Inc.
9 */
10
11/*
12 * This file contains the hardware configuration of the XTAVNET boards.
13 */
14
15#ifndef __XTENSA_XTAVNET_HARDWARE_H
16#define __XTENSA_XTAVNET_HARDWARE_H
17
18/* Memory configuration. */
19
20#define PLATFORM_DEFAULT_MEM_START CONFIG_DEFAULT_MEM_START
21#define PLATFORM_DEFAULT_MEM_SIZE  CONFIG_DEFAULT_MEM_SIZE
22
23/* Interrupt configuration. */
24
25#define PLATFORM_NR_IRQS	10
26
27/* Default assignment of LX60 devices to external interrupts. */
28
29#ifdef CONFIG_XTENSA_MX
30#define DUART16552_INTNUM	XCHAL_EXTINT3_NUM
31#define OETH_IRQ		XCHAL_EXTINT4_NUM
32#else
33#define DUART16552_INTNUM	XCHAL_EXTINT0_NUM
34#define OETH_IRQ		XCHAL_EXTINT1_NUM
35#endif
36
37/*
38 *  Device addresses and parameters.
39 */
40
41/* UART */
42#define DUART16552_PADDR	(XCHAL_KIO_PADDR + 0x0D050020)
43
44/* Misc. */
45#define XTFPGA_FPGAREGS_VADDR	IOADDR(0x0D020000)
46/* Clock frequency in Hz (read-only):  */
47#define XTFPGA_CLKFRQ_VADDR	(XTFPGA_FPGAREGS_VADDR + 0x04)
48/* Setting of 8 DIP switches:  */
49#define DIP_SWITCHES_VADDR	(XTFPGA_FPGAREGS_VADDR + 0x0C)
50/* Software reset (write 0xdead):  */
51#define XTFPGA_SWRST_VADDR	(XTFPGA_FPGAREGS_VADDR + 0x10)
52
53/*  OpenCores Ethernet controller:  */
54				/* regs + RX/TX descriptors */
55#define OETH_REGS_PADDR		(XCHAL_KIO_PADDR + 0x0D030000)
56#define OETH_REGS_SIZE		0x1000
57#define OETH_SRAMBUFF_PADDR	(XCHAL_KIO_PADDR + 0x0D800000)
58
59				/* 5*rx buffs + 5*tx buffs */
60#define OETH_SRAMBUFF_SIZE	(5 * 0x600 + 5 * 0x600)
61
62#define C67X00_PADDR		(XCHAL_KIO_PADDR + 0x0D0D0000)
63#define C67X00_SIZE		0x10
64#define C67X00_IRQ		5
65#endif /* __XTENSA_XTAVNET_HARDWARE_H */
66