1/* 2 * Copyright (C) 2002 Intersil Americas Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 */ 17 18#ifndef _ISL_38XX_H 19#define _ISL_38XX_H 20 21#include <asm/io.h> 22#include <asm/byteorder.h> 23 24#define ISL38XX_CB_RX_QSIZE 8 25#define ISL38XX_CB_TX_QSIZE 32 26 27/* ISL38XX Access Point Specific definitions */ 28#define ISL38XX_MAX_WDS_LINKS 8 29 30/* ISL38xx Client Specific definitions */ 31#define ISL38XX_PSM_ACTIVE_STATE 0 32#define ISL38XX_PSM_POWERSAVE_STATE 1 33 34/* ISL38XX Host Interface Definitions */ 35#define ISL38XX_PCI_MEM_SIZE 0x02000 36#define ISL38XX_MEMORY_WINDOW_SIZE 0x01000 37#define ISL38XX_DEV_FIRMWARE_ADDRES 0x20000 38#define ISL38XX_WRITEIO_DELAY 10 /* in us */ 39#define ISL38XX_RESET_DELAY 50 /* in ms */ 40#define ISL38XX_WAIT_CYCLE 10 /* in 10ms */ 41#define ISL38XX_MAX_WAIT_CYCLES 10 42 43/* PCI Memory Area */ 44#define ISL38XX_HARDWARE_REG 0x0000 45#define ISL38XX_CARDBUS_CIS 0x0800 46#define ISL38XX_DIRECT_MEM_WIN 0x1000 47 48/* Hardware registers */ 49#define ISL38XX_DEV_INT_REG 0x0000 50#define ISL38XX_INT_IDENT_REG 0x0010 51#define ISL38XX_INT_ACK_REG 0x0014 52#define ISL38XX_INT_EN_REG 0x0018 53#define ISL38XX_GEN_PURP_COM_REG_1 0x0020 54#define ISL38XX_GEN_PURP_COM_REG_2 0x0024 55#define ISL38XX_CTRL_BLK_BASE_REG ISL38XX_GEN_PURP_COM_REG_1 56#define ISL38XX_DIR_MEM_BASE_REG 0x0030 57#define ISL38XX_CTRL_STAT_REG 0x0078 58 59/* High end mobos queue up pci writes, the following 60 * is used to "read" from after a write to force flush */ 61#define ISL38XX_PCI_POSTING_FLUSH ISL38XX_INT_EN_REG 62 63/** 64 * isl38xx_w32_flush - PCI iomem write helper 65 * @base: (host) memory base address of the device 66 * @val: 32bit value (host order) to write 67 * @offset: byte offset into @base to write value to 68 * 69 * This helper takes care of writing a 32bit datum to the 70 * specified offset into the device's pci memory space, and making sure 71 * the pci memory buffers get flushed by performing one harmless read 72 * from the %ISL38XX_PCI_POSTING_FLUSH offset. 73 */ 74static inline void 75isl38xx_w32_flush(void __iomem *base, u32 val, unsigned long offset) 76{ 77 writel(val, base + offset); 78 (void) readl(base + ISL38XX_PCI_POSTING_FLUSH); 79} 80 81/* Device Interrupt register bits */ 82#define ISL38XX_DEV_INT_RESET 0x0001 83#define ISL38XX_DEV_INT_UPDATE 0x0002 84#define ISL38XX_DEV_INT_WAKEUP 0x0008 85#define ISL38XX_DEV_INT_SLEEP 0x0010 86 87/* Interrupt Identification/Acknowledge/Enable register bits */ 88#define ISL38XX_INT_IDENT_UPDATE 0x0002 89#define ISL38XX_INT_IDENT_INIT 0x0004 90#define ISL38XX_INT_IDENT_WAKEUP 0x0008 91#define ISL38XX_INT_IDENT_SLEEP 0x0010 92#define ISL38XX_INT_SOURCES 0x001E 93 94/* Control/Status register bits */ 95/* Looks like there are other meaningful bits 96 0x20004400 seen in normal operation, 97 0x200044db at 'timeout waiting for mgmt response' 98*/ 99#define ISL38XX_CTRL_STAT_SLEEPMODE 0x00000200 100#define ISL38XX_CTRL_STAT_CLKRUN 0x00800000 101#define ISL38XX_CTRL_STAT_RESET 0x10000000 102#define ISL38XX_CTRL_STAT_RAMBOOT 0x20000000 103#define ISL38XX_CTRL_STAT_STARTHALTED 0x40000000 104#define ISL38XX_CTRL_STAT_HOST_OVERRIDE 0x80000000 105 106/* Control Block definitions */ 107#define ISL38XX_CB_RX_DATA_LQ 0 108#define ISL38XX_CB_TX_DATA_LQ 1 109#define ISL38XX_CB_RX_DATA_HQ 2 110#define ISL38XX_CB_TX_DATA_HQ 3 111#define ISL38XX_CB_RX_MGMTQ 4 112#define ISL38XX_CB_TX_MGMTQ 5 113#define ISL38XX_CB_QCOUNT 6 114#define ISL38XX_CB_MGMT_QSIZE 4 115#define ISL38XX_MIN_QTHRESHOLD 4 /* fragments */ 116 117/* Memory Manager definitions */ 118#define MGMT_FRAME_SIZE 1500 /* >= size struct obj_bsslist */ 119#define MGMT_TX_FRAME_COUNT 24 /* max 4 + spare 4 + 8 init */ 120#define MGMT_RX_FRAME_COUNT 24 /* 4*4 + spare 8 */ 121#define MGMT_FRAME_COUNT (MGMT_TX_FRAME_COUNT + MGMT_RX_FRAME_COUNT) 122#define CONTROL_BLOCK_SIZE 1024 /* should be enough */ 123#define PSM_FRAME_SIZE 1536 124#define PSM_MINIMAL_STATION_COUNT 64 125#define PSM_FRAME_COUNT PSM_MINIMAL_STATION_COUNT 126#define PSM_BUFFER_SIZE PSM_FRAME_SIZE * PSM_FRAME_COUNT 127#define MAX_TRAP_RX_QUEUE 4 128#define HOST_MEM_BLOCK CONTROL_BLOCK_SIZE + PSM_BUFFER_SIZE 129 130/* Fragment package definitions */ 131#define FRAGMENT_FLAG_MF 0x0001 132#define MAX_FRAGMENT_SIZE 1536 133 134/* In monitor mode frames have a header. I don't know exactly how big those 135 * frame can be but I've never seen any frame bigger than 1584... : 136 */ 137#define MAX_FRAGMENT_SIZE_RX 1600 138 139typedef struct { 140 __le32 address; /* physical address on host */ 141 __le16 size; /* packet size */ 142 __le16 flags; /* set of bit-wise flags */ 143} isl38xx_fragment; 144 145struct isl38xx_cb { 146 __le32 driver_curr_frag[ISL38XX_CB_QCOUNT]; 147 __le32 device_curr_frag[ISL38XX_CB_QCOUNT]; 148 isl38xx_fragment rx_data_low[ISL38XX_CB_RX_QSIZE]; 149 isl38xx_fragment tx_data_low[ISL38XX_CB_TX_QSIZE]; 150 isl38xx_fragment rx_data_high[ISL38XX_CB_RX_QSIZE]; 151 isl38xx_fragment tx_data_high[ISL38XX_CB_TX_QSIZE]; 152 isl38xx_fragment rx_data_mgmt[ISL38XX_CB_MGMT_QSIZE]; 153 isl38xx_fragment tx_data_mgmt[ISL38XX_CB_MGMT_QSIZE]; 154}; 155 156typedef struct isl38xx_cb isl38xx_control_block; 157 158/* determine number of entries currently in queue */ 159int isl38xx_in_queue(isl38xx_control_block *cb, int queue); 160 161void isl38xx_disable_interrupts(void __iomem *); 162void isl38xx_enable_common_interrupts(void __iomem *); 163 164void isl38xx_handle_sleep_request(isl38xx_control_block *, int *, 165 void __iomem *); 166void isl38xx_handle_wakeup(isl38xx_control_block *, int *, void __iomem *); 167void isl38xx_trigger_device(int, void __iomem *); 168void isl38xx_interface_reset(void __iomem *, dma_addr_t); 169 170#endif /* _ISL_38XX_H */ 171