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Searched refs:sclk (Results 1 – 119 of 119) sorted by relevance

/linux-4.4.14/drivers/clk/hisilicon/
Dclkgate-separated.c48 struct clkgate_separated *sclk; in clkgate_separated_enable() local
52 sclk = container_of(hw, struct clkgate_separated, hw); in clkgate_separated_enable()
53 if (sclk->lock) in clkgate_separated_enable()
54 spin_lock_irqsave(sclk->lock, flags); in clkgate_separated_enable()
55 reg = BIT(sclk->bit_idx); in clkgate_separated_enable()
56 writel_relaxed(reg, sclk->enable); in clkgate_separated_enable()
57 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); in clkgate_separated_enable()
58 if (sclk->lock) in clkgate_separated_enable()
59 spin_unlock_irqrestore(sclk->lock, flags); in clkgate_separated_enable()
65 struct clkgate_separated *sclk; in clkgate_separated_disable() local
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/linux-4.4.14/drivers/clk/
Dclk-u300.c455 static void syscon_block_reset_enable(struct clk_syscon *sclk) in syscon_block_reset_enable() argument
461 if (!sclk->res_reg) in syscon_block_reset_enable()
464 val = readw(sclk->res_reg); in syscon_block_reset_enable()
465 val |= BIT(sclk->res_bit); in syscon_block_reset_enable()
466 writew(val, sclk->res_reg); in syscon_block_reset_enable()
468 sclk->reset = true; in syscon_block_reset_enable()
471 static void syscon_block_reset_disable(struct clk_syscon *sclk) in syscon_block_reset_disable() argument
477 if (!sclk->res_reg) in syscon_block_reset_disable()
480 val = readw(sclk->res_reg); in syscon_block_reset_disable()
481 val &= ~BIT(sclk->res_bit); in syscon_block_reset_disable()
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Dclk-scpi.c151 struct scpi_clk *sclk, const char *name) in scpi_clk_ops_init() argument
161 sclk->hw.init = &init; in scpi_clk_ops_init()
162 sclk->scpi_ops = get_scpi_ops(); in scpi_clk_ops_init()
165 sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id); in scpi_clk_ops_init()
166 if (IS_ERR(sclk->info)) in scpi_clk_ops_init()
169 if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max) in scpi_clk_ops_init()
175 clk = devm_clk_register(dev, &sclk->hw); in scpi_clk_ops_init()
177 clk_hw_set_rate_range(&sclk->hw, min, max); in scpi_clk_ops_init()
189 struct scpi_clk *sclk; in scpi_of_clk_src_get() local
194 sclk = clk_data->clk[count]; in scpi_of_clk_src_get()
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Dclk-nomadik.c302 struct clk_src *sclk = to_src(hw); in src_clk_enable() local
303 u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0; in src_clk_enable()
304 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; in src_clk_enable()
306 writel(sclk->clkbit, src_base + enreg); in src_clk_enable()
308 while (!(readl(src_base + sreg) & sclk->clkbit)) in src_clk_enable()
315 struct clk_src *sclk = to_src(hw); in src_clk_disable() local
316 u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0; in src_clk_disable()
317 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; in src_clk_disable()
319 writel(sclk->clkbit, src_base + disreg); in src_clk_disable()
321 while (readl(src_base + sreg) & sclk->clkbit) in src_clk_disable()
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/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgk104.c68 u32 sclk; in read_pll() local
77 sclk = device->crystal; in read_pll()
81 sclk = read_pll(clk, 0x132020); in read_pll()
85 sclk = read_div(clk, 0, 0x137320, 0x137330); in read_pll()
92 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
101 sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13); in read_pll()
102 return sclk / (M * P); in read_pll()
121 u32 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div() local
123 return (sclk * 2) / sdiv; in read_div()
149 u32 sclk, sdiv; in read_clk() local
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Dgf100.c67 u32 sclk; in read_pll() local
75 sclk = device->crystal; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
88 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
94 return sclk * N / M / P; in read_pll()
113 u32 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div() local
115 return (sclk * 2) / sdiv; in read_div()
130 u32 sclk, sdiv; in read_clk() local
134 sclk = read_pll(clk, 0x137000 + (idx * 0x20)); in read_clk()
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Dgt215.c64 u32 sctl, sdiv, sclk; in read_clk() local
99 sclk = read_vco(clk, idx); in read_clk()
101 return (sclk * 2) / sdiv; in read_clk()
112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll() local
127 sclk = read_clk(clk, 0x00 + idx, false); in read_pll()
130 sclk = read_clk(clk, 0x10 + idx, false); in read_pll()
134 return sclk * N / (M * P); in read_pll()
188 u32 oclk, sclk, sdiv; in gt215_clk_info() local
204 sclk = read_vco(clk, idx); in gt215_clk_info()
205 sdiv = min((sclk * 2) / khz, (u32)65); in gt215_clk_info()
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Dnv40.c150 int sclk = cstate->domain[nv_clk_src_shader]; in nv40_clk_calc() local
169 if (sclk && sclk != gclk) { in nv40_clk_calc()
170 ret = nv40_clk_calc_pll(clk, 0x004008, sclk, in nv40_clk_calc()
/linux-4.4.14/drivers/gpu/drm/radeon/
Drv730_dpm.c42 RV770_SMC_SCLK_VALUE *sclk) in rv730_populate_sclk_value() argument
109 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value()
110 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_sclk_value()
111 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_sclk_value()
112 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_sclk_value()
113 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv730_populate_sclk_value()
114 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv730_populate_sclk_value()
305 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_smc_acpi_state()
306 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_smc_acpi_state()
307 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_smc_acpi_state()
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Dbtc_dpm.c1244 u32 *sclk, u32 *mclk) in btc_skip_blacklist_clocks() argument
1248 if ((sclk == NULL) || (mclk == NULL)) in btc_skip_blacklist_clocks()
1254 if ((btc_blacklist_clocks[i].sclk == *sclk) && in btc_skip_blacklist_clocks()
1261 *sclk = btc_get_valid_sclk(rdev, max_sclk, *sclk + 1); in btc_skip_blacklist_clocks()
1263 if (*sclk < max_sclk) in btc_skip_blacklist_clocks()
1264 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk); in btc_skip_blacklist_clocks()
1274 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
1277 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
1280 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
1281 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
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Drv770_dpm.c272 a_n = (int)state->medium.sclk * pi->lmp + in rv770_populate_smc_t()
273 (int)state->low.sclk * (R600_AH_DFLT - pi->rlp); in rv770_populate_smc_t()
274 a_d = (int)state->low.sclk * (100 - (int)pi->rlp) + in rv770_populate_smc_t()
275 (int)state->medium.sclk * pi->lmp; in rv770_populate_smc_t()
280 a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk * in rv770_populate_smc_t()
282 a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) + in rv770_populate_smc_t()
283 (int)state->high.sclk * pi->lhp; in rv770_populate_smc_t()
486 RV770_SMC_SCLK_VALUE *sclk) in rv770_populate_sclk_value() argument
556 sclk->sclk_value = cpu_to_be32(engine_clock); in rv770_populate_sclk_value()
557 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv770_populate_sclk_value()
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Dtrinity_dpm.c583 u32 index, u32 sclk) in trinity_set_divider_value() argument
591 sclk, false, &dividers); in trinity_set_divider_value()
601 sclk/2, false, &dividers); in trinity_set_divider_value()
721 trinity_set_divider_value(rdev, index, pl->sclk); in trinity_program_power_level()
968 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
969 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
982 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
983 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1333 static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk) in trinity_calculate_vce_wm() argument
1335 if (sclk < 20000) in trinity_calculate_vce_wm()
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Drv740_dpm.c122 RV770_SMC_SCLK_VALUE *sclk) in rv740_populate_sclk_value() argument
177 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
178 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_sclk_value()
179 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_sclk_value()
180 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_sclk_value()
181 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv740_populate_sclk_value()
182 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv740_populate_sclk_value()
383 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_smc_acpi_state()
384 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_smc_acpi_state()
385 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_smc_acpi_state()
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Dni_dpm.c810 if (ps->performance_levels[i].sclk > max_limits->sclk) in ni_apply_state_adjust_rules()
811 ps->performance_levels[i].sclk = max_limits->sclk; in ni_apply_state_adjust_rules()
829 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules()
830 &ps->performance_levels[0].sclk, in ni_apply_state_adjust_rules()
834 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in ni_apply_state_adjust_rules()
835 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in ni_apply_state_adjust_rules()
864 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules()
865 &ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules()
874 ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules()
1621 (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk); in ni_populate_memory_timing_parameters()
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Dkv_dpm.c534 u32 index, u32 sclk) in kv_set_divider_value() argument
541 sclk, false, &dividers); in kv_set_divider_value()
546 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
723 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
737 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
1716 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || in kv_set_valid_clock_range()
1724 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1730 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1731 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1741 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || in kv_set_valid_clock_range()
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Dsumo_dpm.c348 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
351 highest_engine_clock = pi->boost_pl.sclk; in sumo_program_bsp()
412 m_a = asi * ps->levels[i].sclk / 100; in sumo_program_at()
422 m_a = asi * pi->boost_pl.sclk / 100; in sumo_program_at()
556 pl->sclk, false, &dividers); in sumo_program_power_level()
672 pi->boost_pl.sclk = pi->sys_info.boost_sclk; in sumo_patch_boost_state()
791 pi->acpi_pl.sclk, in sumo_program_acpi_power_level()
845 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in sumo_set_uvd_clock_before_set_eng_clock()
846 current_ps->levels[current_ps->num_levels - 1].sclk) in sumo_set_uvd_clock_before_set_eng_clock()
863 if (new_ps->levels[new_ps->num_levels - 1].sclk < in sumo_set_uvd_clock_after_set_eng_clock()
[all …]
Dsi_dpm.c1758 SISLANDS_SMC_SCLK_VALUE *sclk);
2322 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values()
2323 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values()
2342 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2343 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2417 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
2852 u32 sclk = 0; in si_init_smc_spll_table() local
2865 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); in si_init_smc_spll_table()
2898 sclk += 512; in si_init_smc_spll_table()
2995 u32 mclk, sclk; in si_apply_state_adjust_rules() local
[all …]
Drv6xx_dpm.c440 state->low.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
442 state->medium.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
444 state->high.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
1028 rv6xx_calculate_t(state->low.sclk, in rv6xx_calculate_ap()
1029 state->medium.sclk, in rv6xx_calculate_ap()
1036 rv6xx_calculate_t(state->medium.sclk, in rv6xx_calculate_ap()
1037 state->high.sclk, in rv6xx_calculate_ap()
1427 old_state->low.sclk, in rv6xx_generate_transition_stepping()
1428 new_state->low.sclk, in rv6xx_generate_transition_stepping()
1440 new_state->low.sclk, in rv6xx_generate_low_step()
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Drs690.c268 fixed20_12 sclk; member
280 fixed20_12 sclk, core_bandwidth, max_bandwidth; in rs690_crtc_bandwidth_compute() local
297 sclk.full = dfixed_const(selected_sclk); in rs690_crtc_bandwidth_compute()
298 sclk.full = dfixed_div(sclk, a); in rs690_crtc_bandwidth_compute()
302 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); in rs690_crtc_bandwidth_compute()
386 sclk.full = dfixed_mul(max_bandwidth, a); in rs690_crtc_bandwidth_compute()
388 sclk.full = dfixed_div(a, sclk); in rs690_crtc_bandwidth_compute()
395 chunk_time.full = dfixed_mul(sclk, a); in rs690_crtc_bandwidth_compute()
483 fill_rate.full = dfixed_div(wm0->sclk, a); in rs690_compute_mode_priority()
531 fill_rate.full = dfixed_div(wm0->sclk, a); in rs690_compute_mode_priority()
[all …]
Dci_dpm.c793 u32 sclk, mclk; in ci_apply_state_adjust_rules() local
824 if (ps->performance_levels[i].sclk > max_limits->sclk) in ci_apply_state_adjust_rules()
825 ps->performance_levels[i].sclk = max_limits->sclk; in ci_apply_state_adjust_rules()
833 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
836 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
840 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in ci_apply_state_adjust_rules()
841 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in ci_apply_state_adjust_rules()
846 ps->performance_levels[0].sclk = sclk; in ci_apply_state_adjust_rules()
849 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk) in ci_apply_state_adjust_rules()
850 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
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Drs780_dpm.c752 u32 sclk; in rs780_parse_pplib_clock_info() local
754 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); in rs780_parse_pplib_clock_info()
755 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; in rs780_parse_pplib_clock_info()
756 ps->sclk_low = sclk; in rs780_parse_pplib_clock_info()
757 sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow); in rs780_parse_pplib_clock_info()
758 sclk |= clock_info->rs780.ucHighEngineClockHigh << 16; in rs780_parse_pplib_clock_info()
759 ps->sclk_high = sclk; in rs780_parse_pplib_clock_info()
990 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_debugfs_print_current_performance_level() local
996 if (sclk < (ps->sclk_low + 500)) in rs780_dpm_debugfs_print_current_performance_level()
1012 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_get_current_sclk() local
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Dradeon_atombios.c2143 rdev->pm.power_state[state_index].clock_info[0].sclk = in radeon_atombios_parse_power_table_1_3()
2147 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) in radeon_atombios_parse_power_table_1_3()
2178 rdev->pm.power_state[state_index].clock_info[0].sclk = in radeon_atombios_parse_power_table_1_3()
2182 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) in radeon_atombios_parse_power_table_1_3()
2214 rdev->pm.power_state[state_index].clock_info[0].sclk = in radeon_atombios_parse_power_table_1_3()
2218 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) in radeon_atombios_parse_power_table_1_3()
2442 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; in radeon_atombios_parse_pplib_non_clock_info()
2457 rdev->pm.power_state[state_index].clock_info[j].sclk = in radeon_atombios_parse_pplib_non_clock_info()
2474 u32 sclk, mclk; in radeon_atombios_parse_pplib_clock_info() local
2479 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); in radeon_atombios_parse_pplib_clock_info()
[all …]
Drv770_dpm.h142 u32 sclk; member
181 RV770_SMC_SCLK_VALUE *sclk);
202 RV770_SMC_SCLK_VALUE *sclk);
Dcypress_dpm.c691 ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk); in cypress_convert_power_level_to_smc()
725 pl->sclk, in cypress_convert_power_level_to_smc()
732 pl->sclk, in cypress_convert_power_level_to_smc()
933 new_state->low.sclk, in cypress_program_memory_timing_parameters()
936 new_state->medium.sclk, in cypress_program_memory_timing_parameters()
939 new_state->high.sclk, in cypress_program_memory_timing_parameters()
1264 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = in cypress_populate_smc_initial_state()
1266 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = in cypress_populate_smc_initial_state()
1268 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = in cypress_populate_smc_initial_state()
1270 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = in cypress_populate_smc_initial_state()
[all …]
Dsumo_dpm.h32 u32 sclk; member
207 u32 sclk,
Dradeon_clocks.c38 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
51 sclk = fb_div / ref_div; in radeon_legacy_get_engine_clock()
55 sclk >>= 1; in radeon_legacy_get_engine_clock()
57 sclk >>= 2; in radeon_legacy_get_engine_clock()
59 sclk >>= 3; in radeon_legacy_get_engine_clock()
61 return sclk; in radeon_legacy_get_engine_clock()
Dbtc_dpm.h43 u32 *sclk, u32 *mclk);
Drv6xx_dpm.h80 u32 sclk; member
Drv515.c950 fixed20_12 sclk; member
962 fixed20_12 sclk; in rv515_crtc_bandwidth_compute() local
980 sclk.full = dfixed_const(selected_sclk); in rv515_crtc_bandwidth_compute()
981 sclk.full = dfixed_div(sclk, a); in rv515_crtc_bandwidth_compute()
1048 chunk_time.full = dfixed_div(a, sclk); in rv515_crtc_bandwidth_compute()
1133 fill_rate.full = dfixed_div(wm0->sclk, a); in rv515_compute_mode_priority()
1181 fill_rate.full = dfixed_div(wm0->sclk, a); in rv515_compute_mode_priority()
1208 fill_rate.full = dfixed_div(wm1->sclk, a); in rv515_compute_mode_priority()
Dradeon_pm.c169 u32 sclk, mclk; in radeon_set_power_state() local
177 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. in radeon_set_power_state()
178 clock_info[rdev->pm.requested_clock_mode_index].sclk; in radeon_set_power_state()
179 if (sclk > rdev->pm.default_sclk) in radeon_set_power_state()
180 sclk = rdev->pm.default_sclk; in radeon_set_power_state()
201 if (sclk < rdev->pm.current_sclk) in radeon_set_power_state()
218 if (sclk != rdev->pm.current_sclk) { in radeon_set_power_state()
220 radeon_set_engine_clock(rdev, sclk); in radeon_set_power_state()
222 rdev->pm.current_sclk = sclk; in radeon_set_power_state()
223 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); in radeon_set_power_state()
[all …]
Dtrinity_dpm.h31 u32 sclk; member
Dradeon_i2c.c238 u32 sclk = rdev->pm.current_sclk; in radeon_get_i2c_prescale() local
258 nm = (sclk * 10) / (i2c_clock * 4); in radeon_get_i2c_prescale()
273 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; in radeon_get_i2c_prescale()
288 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); in radeon_get_i2c_prescale()
290 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; in radeon_get_i2c_prescale()
Dradeon_device.c708 u32 sclk = rdev->pm.current_sclk; in radeon_update_bandwidth_info() local
713 rdev->pm.sclk.full = dfixed_const(sclk); in radeon_update_bandwidth_info()
714 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); in radeon_update_bandwidth_info()
721 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); in radeon_update_bandwidth_info()
Drv770_smc.h108 RV770_SMC_SCLK_VALUE sclk; member
Dkv_dpm.h71 u32 sclk; member
Dnislands_smc.h108 NISLANDS_SMC_SCLK_VALUE sclk; member
Dsi.c2000 u32 sclk; /* engine clock in kHz */ member
2057 fixed20_12 sclk, bandwidth; in dce6_data_return_bandwidth() local
2061 sclk.full = dfixed_const(wm->sclk); in dce6_data_return_bandwidth()
2062 sclk.full = dfixed_div(sclk, a); in dce6_data_return_bandwidth()
2067 bandwidth.full = dfixed_mul(a, sclk); in dce6_data_return_bandwidth()
2082 fixed20_12 disp_clk, sclk, bandwidth; in dce6_dmif_request_bandwidth() local
2093 sclk.full = dfixed_const(wm->sclk); in dce6_dmif_request_bandwidth()
2094 sclk.full = dfixed_div(sclk, a); in dce6_dmif_request_bandwidth()
2096 b2.full = dfixed_mul(a, sclk); in dce6_dmif_request_bandwidth()
2282 wm_high.sclk = in dce6_program_watermarks()
[all …]
Dci_dpm.h40 u32 sclk; member
Dradeon_combios.c739 uint16_t sclk, mclk; in radeon_combios_get_clock_info() local
793 sclk = RBIOS16(pll_info + 0xa); in radeon_combios_get_clock_info()
795 if (sclk == 0) in radeon_combios_get_clock_info()
796 sclk = 200 * 100; in radeon_combios_get_clock_info()
800 rdev->clock.default_sclk = sclk; in radeon_combios_get_clock_info()
2733 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); in radeon_combios_get_power_modes()
2735 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) in radeon_combios_get_power_modes()
2807 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; in radeon_combios_get_power_modes()
Dsislands_smc.h153 SISLANDS_SMC_SCLK_VALUE sclk; member
Devergreen.c2028 u32 sclk; /* engine clock in kHz */ member
2085 fixed20_12 sclk, bandwidth; in evergreen_data_return_bandwidth() local
2089 sclk.full = dfixed_const(wm->sclk); in evergreen_data_return_bandwidth()
2090 sclk.full = dfixed_div(sclk, a); in evergreen_data_return_bandwidth()
2095 bandwidth.full = dfixed_mul(a, sclk); in evergreen_data_return_bandwidth()
2280 wm_high.sclk = in evergreen_program_watermarks()
2284 wm_high.sclk = rdev->pm.current_sclk * 10; in evergreen_program_watermarks()
2307 wm_low.sclk = in evergreen_program_watermarks()
2311 wm_low.sclk = rdev->pm.current_sclk * 10; in evergreen_program_watermarks()
Dradeon.h1295 u32 sclk; member
1382 u32 sclk; member
1388 u32 sclk; member
1428 u32 sclk; member
1542 u32 sclk; member
1619 fixed20_12 sclk; member
Dcik.c9194 u32 sclk; /* engine clock in kHz */ member
9278 fixed20_12 sclk, bandwidth; in dce8_data_return_bandwidth() local
9282 sclk.full = dfixed_const(wm->sclk); in dce8_data_return_bandwidth()
9283 sclk.full = dfixed_div(sclk, a); in dce8_data_return_bandwidth()
9288 bandwidth.full = dfixed_mul(a, sclk); in dce8_data_return_bandwidth()
9555 wm_high.sclk = in dce8_program_watermarks()
9559 wm_high.sclk = rdev->pm.current_sclk * 10; in dce8_program_watermarks()
9595 wm_low.sclk = in dce8_program_watermarks()
9599 wm_low.sclk = rdev->pm.current_sclk * 10; in dce8_program_watermarks()
Dradeon_kfd.c326 return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100; in get_max_engine_clock_in_mhz()
Dr600_dpm.c970 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = in r600_parse_extended_power_table()
1000 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk = in r600_parse_extended_power_table()
Dradeon_kms.c511 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; in radeon_info_ioctl()
Dr100.c282 clock_info[rdev->pm.requested_clock_mode_index].sclk, in r100_pm_get_dynpm_state()
3256 sclk_ff = rdev->pm.sclk; in r100_bandwidth_update()
Dr600.c522 clock_info[rdev->pm.requested_clock_mode_index].sclk, in r600_pm_get_dynpm_state()
/linux-4.4.14/drivers/tty/serial/8250/
D8250_em.c35 struct clk *sclk; member
107 priv->sclk = devm_clk_get(&pdev->dev, "sclk"); in serial8250_em_probe()
108 if (IS_ERR(priv->sclk)) { in serial8250_em_probe()
110 return PTR_ERR(priv->sclk); in serial8250_em_probe()
121 clk_prepare_enable(priv->sclk); in serial8250_em_probe()
122 up.port.uartclk = clk_get_rate(priv->sclk); in serial8250_em_probe()
133 clk_disable_unprepare(priv->sclk); in serial8250_em_probe()
147 clk_disable_unprepare(priv->sclk); in serial8250_em_remove()
/linux-4.4.14/drivers/power/reset/
Dat91-reset.c50 static struct clk *sclk; variable
210 sclk = devm_clk_get(&pdev->dev, NULL); in at91_reset_probe()
211 if (IS_ERR(sclk)) in at91_reset_probe()
212 return PTR_ERR(sclk); in at91_reset_probe()
214 ret = clk_prepare_enable(sclk); in at91_reset_probe()
222 clk_disable_unprepare(sclk); in at91_reset_probe()
234 clk_disable_unprepare(sclk); in at91_reset_remove()
Dat91-poweroff.c52 static struct clk *sclk; variable
136 sclk = devm_clk_get(&pdev->dev, NULL); in at91_poweroff_probe()
137 if (IS_ERR(sclk)) in at91_poweroff_probe()
138 return PTR_ERR(sclk); in at91_poweroff_probe()
140 ret = clk_prepare_enable(sclk); in at91_poweroff_probe()
161 clk_disable_unprepare(sclk); in at91_poweroff_remove()
/linux-4.4.14/drivers/cpufreq/
Dblackfin-cpufreq.c59 static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk) in bfin_init_tables() argument
69 min_cclk = sclk * 2; in bfin_init_tables()
71 min_cclk = sclk; in bfin_init_tables()
180 unsigned long cclk, sclk; in __bfin_cpu_init() local
183 sclk = get_sclk() / 1000; in __bfin_cpu_init()
186 bfin_init_tables(cclk, sclk); in __bfin_cpu_init()
/linux-4.4.14/sound/soc/cirrus/
Dep93xx-i2s.c64 struct clk *sclk; member
105 clk_enable(info->sclk); in ep93xx_i2s_enable()
141 clk_disable(info->sclk); in ep93xx_i2s_disable()
293 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv); in ep93xx_i2s_hw_params()
297 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv); in ep93xx_i2s_hw_params()
401 info->sclk = clk_get(&pdev->dev, "sclk"); in ep93xx_i2s_probe()
402 if (IS_ERR(info->sclk)) { in ep93xx_i2s_probe()
403 err = PTR_ERR(info->sclk); in ep93xx_i2s_probe()
431 clk_put(info->sclk); in ep93xx_i2s_probe()
444 clk_put(info->sclk); in ep93xx_i2s_remove()
/linux-4.4.14/drivers/media/dvb-frontends/
Dcx24110.c557 s32 afc; unsigned sclk; in cx24110_get_frontend() local
561 sclk = cx24110_readreg (state, 0x07) & 0x03; in cx24110_get_frontend()
564 if (sclk==0) sclk=90999000L/2L; in cx24110_get_frontend()
565 else if (sclk==1) sclk=60666000L; in cx24110_get_frontend()
566 else if (sclk==2) sclk=80888000L; in cx24110_get_frontend()
567 else sclk=90999000L; in cx24110_get_frontend()
568 sclk>>=8; in cx24110_get_frontend()
569 afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+ in cx24110_get_frontend()
570 ((sclk*cx24110_readreg (state, 0x45))>>8)+ in cx24110_get_frontend()
571 ((sclk*cx24110_readreg (state, 0x46))>>16); in cx24110_get_frontend()
/linux-4.4.14/Documentation/devicetree/bindings/rtc/
Dmoxa,moxart-rtc.txt6 - gpio-rtc-sclk : RTC sclk gpio, with zero flags
14 gpio-rtc-sclk = <&gpio 5 0>;
/linux-4.4.14/drivers/clocksource/
Dtimer-atmel-st.c199 struct clk *sclk; in atmel_st_timer_init() local
224 sclk = of_clk_get(node, 0); in atmel_st_timer_init()
225 if (IS_ERR(sclk)) in atmel_st_timer_init()
228 clk_prepare_enable(sclk); in atmel_st_timer_init()
232 sclk_rate = clk_get_rate(sclk); in atmel_st_timer_init()
/linux-4.4.14/drivers/i2c/busses/
Di2c-emev2.c73 struct clk *sclk; member
264 priv->sclk = devm_clk_get(&pdev->dev, "sclk"); in em_i2c_probe()
265 if (IS_ERR(priv->sclk)) in em_i2c_probe()
266 return PTR_ERR(priv->sclk); in em_i2c_probe()
268 clk_prepare_enable(priv->sclk); in em_i2c_probe()
300 clk_disable_unprepare(priv->sclk); in em_i2c_probe()
309 clk_disable_unprepare(priv->sclk); in em_i2c_remove()
/linux-4.4.14/drivers/gpu/drm/armada/
Darmada_510.c45 const struct drm_display_mode *mode, uint32_t *sclk) in armada510_crtc_compute_clock() argument
63 if (sclk) { in armada510_crtc_compute_clock()
73 *sclk = div | SCLK_510_EXTCLK1; in armada510_crtc_compute_clock()
Darmada_crtc.c539 uint32_t lm, rm, tm, bm, val, sclk; in armada_drm_crtc_mode_set() local
587 dcrtc->variant->compute_clock(dcrtc, adj, &sclk); in armada_drm_crtc_mode_set()
591 armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV); in armada_drm_crtc_mode_set()
/linux-4.4.14/drivers/watchdog/
Dat91sam9_wdt.c94 struct clk *sclk; member
357 wdt->sclk = devm_clk_get(&pdev->dev, NULL); in at91wdt_probe()
358 if (IS_ERR(wdt->sclk)) in at91wdt_probe()
359 return PTR_ERR(wdt->sclk); in at91wdt_probe()
361 err = clk_prepare_enable(wdt->sclk); in at91wdt_probe()
385 clk_disable_unprepare(wdt->sclk); in at91wdt_probe()
397 clk_disable_unprepare(wdt->sclk); in at91wdt_remove()
Dbfin_wdt.c115 u32 cnt, max_t, sclk; in bfin_wdt_set_timeout() local
118 sclk = get_sclk(); in bfin_wdt_set_timeout()
119 max_t = -1 / sclk; in bfin_wdt_set_timeout()
120 cnt = t * sclk; in bfin_wdt_set_timeout()
/linux-4.4.14/arch/blackfin/kernel/
Dnmi.c122 u32 cnt, max_t, sclk; in nmi_wdt_set_timeout() local
125 sclk = get_sclk(); in nmi_wdt_set_timeout()
126 max_t = -1 / sclk; in nmi_wdt_set_timeout()
127 cnt = t * sclk; in nmi_wdt_set_timeout()
Dsetup.c915 unsigned long sclk, cclk; local
981 sclk = get_sclk();
983 if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
1072 cclk / 1000000, sclk / 1000000);
1251 unsigned long sclk_to_usecs(unsigned long sclk) argument
1253 u64 tmp = USEC_PER_SEC * (u64)sclk;
1275 u_long sclk, cclk; local
1284 sclk = get_sclk();
1306 cpu, cclk/1000000, sclk/1000000,
1325 sclk/1000000, sclk%1000000);
/linux-4.4.14/sound/soc/codecs/
Dpcm512x.c45 struct clk *sclk; member
534 if (IS_ERR(pcm512x->sclk)) { in pcm512x_dai_startup_master()
536 PTR_ERR(pcm512x->sclk)); in pcm512x_dai_startup_master()
537 return PTR_ERR(pcm512x->sclk); in pcm512x_dai_startup_master()
557 rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64; in pcm512x_dai_startup_master()
575 if (IS_ERR(pcm512x->sclk)) { in pcm512x_dai_startup_slave()
577 PTR_ERR(pcm512x->sclk)); in pcm512x_dai_startup_slave()
864 sck_rate = clk_get_rate(pcm512x->sclk); in pcm512x_set_dividers()
881 pllin_rate = clk_get_rate(pcm512x->sclk); in pcm512x_set_dividers()
1441 pcm512x->sclk = devm_clk_get(dev, NULL); in pcm512x_probe()
[all …]
Drl6231.c189 int rl6231_get_clk_info(int sclk, int rate) in rl6231_get_clk_info() argument
193 if (sclk <= 0 || rate <= 0) in rl6231_get_clk_info()
198 if (sclk == rate * pd[i]) in rl6231_get_clk_info()
Drl6231.h32 int rl6231_get_clk_info(int sclk, int rate);
Dtas5086.c250 unsigned int mclk, sclk; member
316 priv->sclk = freq; in tas5086_set_dai_sysclk()
403 (priv->sclk == 48 * priv->rate) ? in tas5086_hw_params()
/linux-4.4.14/arch/arm/boot/dts/
Demev2.dtsi163 clock-names = "sclk";
171 clock-names = "sclk";
179 clock-names = "sclk";
187 clock-names = "sclk";
195 clock-names = "sclk";
271 clock-names = "sclk";
282 clock-names = "sclk";
Dmoxart.dtsi75 gpio-rtc-sclk = <&gpio 5 0>;
Dexynos3250.dtsi267 clock-names = "jpeg", "sclk";
403 clock-names = "adc", "sclk";
Dexynos4415.dtsi417 clock-names = "adc", "sclk";
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dkv_dpm.c667 u32 index, u32 sclk) in kv_set_divider_value() argument
674 sclk, false, &dividers); in kv_set_divider_value()
679 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
812 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
826 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
1812 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || in kv_set_valid_clock_range()
1820 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1826 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1827 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1837 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || in kv_set_valid_clock_range()
[all …]
Dci_dpm.c910 u32 sclk, mclk; in ci_apply_state_adjust_rules() local
941 if (ps->performance_levels[i].sclk > max_limits->sclk) in ci_apply_state_adjust_rules()
942 ps->performance_levels[i].sclk = max_limits->sclk; in ci_apply_state_adjust_rules()
950 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
953 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
957 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) in ci_apply_state_adjust_rules()
958 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; in ci_apply_state_adjust_rules()
963 ps->performance_levels[0].sclk = sclk; in ci_apply_state_adjust_rules()
966 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk) in ci_apply_state_adjust_rules()
967 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
[all …]
Dcz_dpm.c78 table->sclk = dep_table->entries[dep_table->count - 1].clk; in cz_construct_max_power_limits_table()
210 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; in cz_construct_boot_state()
246 pl->sclk = table->entries[clock_info->carrizo.index].clk; in cz_parse_pplib_clock_info()
521 u32 sclk, vclk, dclk, ecclk, tmp; in cz_dpm_debugfs_print_current_performance_level() local
527 sclk = table->entries[sclk_index].clk; in cz_dpm_debugfs_print_current_performance_level()
528 seq_printf(m, "%u sclk: %u\n", sclk_index, sclk); in cz_dpm_debugfs_print_current_performance_level()
575 i, pl->sclk, in cz_dpm_print_power_state()
1518 stable_ps_clock = limits->sclk * 75 / 100; in cz_dpm_update_sclk_limit()
1790 return requested_state->levels[0].sclk; in cz_dpm_get_sclk()
1792 return requested_state->levels[requested_state->num_levels - 1].sclk; in cz_dpm_get_sclk()
Dkv_dpm.h97 u32 sclk; member
Dcz_dpm.h82 uint32_t sclk; member
Damdgpu_amdkfd.c268 return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100; in get_max_engine_clock_in_mhz()
Ddce_v8_0.c846 u32 sclk; /* engine clock in kHz */ member
930 fixed20_12 sclk, bandwidth; in dce_v8_0_data_return_bandwidth() local
934 sclk.full = dfixed_const(wm->sclk); in dce_v8_0_data_return_bandwidth()
935 sclk.full = dfixed_div(sclk, a); in dce_v8_0_data_return_bandwidth()
940 bandwidth.full = dfixed_mul(a, sclk); in dce_v8_0_data_return_bandwidth()
1206 wm_high.sclk = in dce_v8_0_program_watermarks()
1210 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v8_0_program_watermarks()
1245 wm_low.sclk = in dce_v8_0_program_watermarks()
1249 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v8_0_program_watermarks()
Ddce_v11_0.c891 u32 sclk; /* engine clock in kHz */ member
975 fixed20_12 sclk, bandwidth; in dce_v11_0_data_return_bandwidth() local
979 sclk.full = dfixed_const(wm->sclk); in dce_v11_0_data_return_bandwidth()
980 sclk.full = dfixed_div(sclk, a); in dce_v11_0_data_return_bandwidth()
985 bandwidth.full = dfixed_mul(a, sclk); in dce_v11_0_data_return_bandwidth()
1251 wm_high.sclk = in dce_v11_0_program_watermarks()
1255 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v11_0_program_watermarks()
1290 wm_low.sclk = in dce_v11_0_program_watermarks()
1294 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v11_0_program_watermarks()
Ddce_v10_0.c903 u32 sclk; /* engine clock in kHz */ member
987 fixed20_12 sclk, bandwidth; in dce_v10_0_data_return_bandwidth() local
991 sclk.full = dfixed_const(wm->sclk); in dce_v10_0_data_return_bandwidth()
992 sclk.full = dfixed_div(sclk, a); in dce_v10_0_data_return_bandwidth()
997 bandwidth.full = dfixed_mul(a, sclk); in dce_v10_0_data_return_bandwidth()
1263 wm_high.sclk = in dce_v10_0_program_watermarks()
1267 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()
1302 wm_low.sclk = in dce_v10_0_program_watermarks()
1306 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()
Dci_dpm.h41 u32 sclk; member
Damdgpu.h1405 u32 sclk; member
1411 u32 sclk; member
1451 u32 sclk; member
1566 u32 sclk; member
Damdgpu_dpm.c411 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = in amdgpu_parse_extended_power_table()
441 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk = in amdgpu_parse_extended_power_table()
Damdgpu_kms.c442 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; in amdgpu_info_ioctl()
/linux-4.4.14/drivers/rtc/
Drtc-at91sam9.c80 struct clk *sclk; member
424 rtc->sclk = devm_clk_get(&pdev->dev, NULL); in at91_rtc_probe()
425 if (IS_ERR(rtc->sclk)) in at91_rtc_probe()
426 return PTR_ERR(rtc->sclk); in at91_rtc_probe()
428 ret = clk_prepare_enable(rtc->sclk); in at91_rtc_probe()
434 sclk_rate = clk_get_rate(rtc->sclk); in at91_rtc_probe()
482 clk_disable_unprepare(rtc->sclk); in at91_rtc_probe()
498 clk_disable_unprepare(rtc->sclk); in at91_rtc_remove()
Drtc-at91rm9200.c63 static struct clk *sclk; variable
412 sclk = devm_clk_get(&pdev->dev, NULL); in at91_rtc_probe()
413 if (IS_ERR(sclk)) in at91_rtc_probe()
414 return PTR_ERR(sclk); in at91_rtc_probe()
416 ret = clk_prepare_enable(sclk); in at91_rtc_probe()
461 clk_disable_unprepare(sclk); in at91_rtc_probe()
476 clk_disable_unprepare(sclk); in at91_rtc_remove()
/linux-4.4.14/Documentation/devicetree/bindings/i2c/
Di2c-emev2.txt8 - clock-names : must be "sclk"
21 clock-names = "sclk";
/linux-4.4.14/sound/soc/samsung/
Dspdif.c89 struct clk *sclk; member
395 spdif->sclk = devm_clk_get(&pdev->dev, "sclk_spdif"); in spdif_probe()
396 if (IS_ERR(spdif->sclk)) { in spdif_probe()
401 clk_prepare_enable(spdif->sclk); in spdif_probe()
445 clk_disable_unprepare(spdif->sclk); in spdif_probe()
463 clk_disable_unprepare(spdif->sclk); in spdif_remove()
/linux-4.4.14/drivers/iio/adc/
Dexynos_adc.c104 struct clk *sclk; member
130 clk_unprepare(info->sclk); in exynos_adc_unprepare_clk()
145 ret = clk_prepare(info->sclk); in exynos_adc_prepare_clk()
160 clk_disable(info->sclk); in exynos_adc_disable_clk()
175 ret = clk_enable(info->sclk); in exynos_adc_enable_clk()
630 info->sclk = devm_clk_get(&pdev->dev, "sclk"); in exynos_adc_probe()
631 if (IS_ERR(info->sclk)) { in exynos_adc_probe()
634 PTR_ERR(info->sclk)); in exynos_adc_probe()
635 return PTR_ERR(info->sclk); in exynos_adc_probe()
/linux-4.4.14/drivers/spi/
Dspi-adi-v3.c92 unsigned long sclk; member
130 static u32 hz_to_spi_clock(u32 sclk, u32 speed_hz) in hz_to_spi_clock() argument
132 u32 spi_clock = sclk / speed_hz; in hz_to_spi_clock()
435 iowrite32(hz_to_spi_clock(drv->sclk, t->speed_hz), &drv->regs->clock); in adi_spi_setup_transfer()
712 chip->clock = hz_to_spi_clock(drv_data->sclk, spi->max_speed_hz); in adi_spi_setup()
803 struct clk *sclk; in adi_spi_probe() local
811 sclk = devm_clk_get(dev, "spi"); in adi_spi_probe()
812 if (IS_ERR(sclk)) { in adi_spi_probe()
814 return PTR_ERR(sclk); in adi_spi_probe()
855 drv_data->sclk = clk_get_rate(sclk); in adi_spi_probe()
Dspi-bfin-sport.c129 u_long clk, sclk = get_sclk(); in bfin_sport_hz_to_spi_baud() local
130 int div = (sclk / (2 * speed_hz)) - 1; in bfin_sport_hz_to_spi_baud()
135 clk = sclk / (2 * (div + 1)); in bfin_sport_hz_to_spi_baud()
Dspi-bfin5xx.c139 u_long sclk = get_sclk(); in hz_to_spi_baud() local
140 u16 spi_baud = (sclk / (2 * speed_hz)); in hz_to_spi_baud()
142 if ((sclk % (2 * speed_hz)) > 0) in hz_to_spi_baud()
/linux-4.4.14/arch/mips/txx9/generic/
Dsetup_tx3927.c116 void __init tx3927_sio_init(unsigned int sclk, unsigned int cts_mask) in tx3927_sio_init() argument
123 i, sclk, (1 << i) & cts_mask); in tx3927_sio_init()
Dsetup_tx4927.c234 void __init tx4927_sio_init(unsigned int sclk, unsigned int cts_mask) in tx4927_sio_init() argument
241 i, sclk, (1 << i) & cts_mask); in tx4927_sio_init()
Dsetup_tx4938.c291 void __init tx4938_sio_init(unsigned int sclk, unsigned int cts_mask) in tx4938_sio_init() argument
303 i, sclk, (1 << i) & cts_mask); in tx4938_sio_init()
Dsetup_tx4939.c298 void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask) in tx4939_sio_init() argument
316 i, sclk, (1 << i) & cts_mask); in tx4939_sio_init()
Dsetup.c478 unsigned int line, unsigned int sclk, int nocts) in txx9_sio_init() argument
491 if (sclk) { in txx9_sio_init()
493 req.uartclk = sclk; in txx9_sio_init()
/linux-4.4.14/Documentation/devicetree/bindings/arm/samsung/
Dexynos-adc.txt44 - "sclk" : ADC special clock (only for Exynos3250 and
69 Example: adding device info in dtsi file for Exynos3250 with additional sclk
79 clock-names = "adc", "sclk";
/linux-4.4.14/drivers/mmc/host/
Dmtk-sd.c324 u32 sclk; /* SD/MS bus clock frequency */ member
487 if (host->sclk == 0) { in msdc_set_timeout()
490 clk_ns = 1000000000UL / host->sclk; in msdc_set_timeout()
522 u32 sclk; in msdc_set_mclk() local
544 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ in msdc_set_mclk()
547 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
555 sclk = host->src_clk_freq >> 1; in msdc_set_mclk()
561 sclk = host->src_clk_freq; in msdc_set_mclk()
566 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ in msdc_set_mclk()
569 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
[all …]
Dbfin_sdh.c71 unsigned long sclk; member
145 cycle_ns = 1000000000 / (host->sclk / (2 * (host->clk_div + 1))); in sdh_setup_data()
563 host->sclk = get_sclk(); in sdh_probe()
/linux-4.4.14/Documentation/devicetree/bindings/media/
Dexynos-jpeg-codec.txt13 - "sclk" for the special clock (optional).
/linux-4.4.14/drivers/video/fbdev/aty/
Dradeon_base.c566 rinfo->pll.sclk = (*val) / 10; in radeon_read_xtal_OF()
583 unsigned sclk, mclk, tmp, ref_div; in radeon_probe_pll_params() local
702 sclk = round_div((2 * Ns * xtal), (2 * M)); in radeon_probe_pll_params()
708 rinfo->pll.sclk = sclk; in radeon_probe_pll_params()
730 rinfo->pll.sclk = 23000; in radeon_get_pllinfo()
741 rinfo->pll.sclk = 27500; in radeon_get_pllinfo()
751 rinfo->pll.sclk = 25000; in radeon_get_pllinfo()
761 rinfo->pll.sclk = 27000; in radeon_get_pllinfo()
772 rinfo->pll.sclk = 16600; in radeon_get_pllinfo()
796 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08); in radeon_get_pllinfo()
[all …]
Datyfb.h49 int sclk, mclk, mclk_pm, xclk; member
Dradeonfb.h140 int sclk, mclk; member
Datyfb_base.c3405 par->pll_limits.sclk = pll_block.SCLK_freq/100; in init_from_bios()
/linux-4.4.14/arch/blackfin/include/asm/
Dbfin-global.h49 extern unsigned long sclk_to_usecs(unsigned long sclk);
/linux-4.4.14/arch/mips/include/asm/txx9/
Dgeneric.h51 unsigned int line, unsigned int sclk, int nocts);
Dtx4927.h264 void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);
Dtx4938.h283 void tx4938_sio_init(unsigned int sclk, unsigned int cts_mask);
Dtx3927.h333 void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask);
Dtx4939.h533 void tx4939_sio_init(unsigned int sclk, unsigned int cts_mask);
/linux-4.4.14/drivers/input/keyboard/
Dbf54x-keys.c114 u32 sclk = get_sclk(); in bfin_kpad_get_prescale() local
116 return ((((sclk / 1000) * timescale) / 1024) - 1); in bfin_kpad_get_prescale()
/linux-4.4.14/Documentation/devicetree/bindings/pinctrl/
Dmarvell,dove-pinctrl.txt30 mpp10 10 gpio, pmu, ssp(sclk), pmu*
51 lcd-spi(sck), ssp(sclk)
/linux-4.4.14/drivers/tty/serial/
Dbfin_sport_uart.c122 unsigned int sclk = get_sclk(); in sport_uart_setup() local
134 tclkdiv = sclk / (2 * baud_rate) - 1; in sport_uart_setup()
140 rclkdiv = sclk / (2 * baud_rate * 2 * 97 / 100) - 1; in sport_uart_setup()
145 __func__, sclk, baud_rate, tclkdiv, rclkdiv); in sport_uart_setup()
/linux-4.4.14/drivers/thermal/samsung/
Dexynos_tmu.c202 struct clk *clk, *clk_sec, *sclk; member
1346 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk"); in exynos_tmu_probe()
1347 if (IS_ERR(data->sclk)) { in exynos_tmu_probe()
1351 ret = clk_prepare_enable(data->sclk); in exynos_tmu_probe()
1393 clk_disable_unprepare(data->sclk); in exynos_tmu_probe()
1414 clk_disable_unprepare(data->sclk); in exynos_tmu_remove()
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Demev2-clock.txt60 clock-names = "sclk";
/linux-4.4.14/drivers/video/fbdev/
Dbf54x-lq043fb.c178 u32 sclk = get_sclk(); in get_eppi_clkdiv() local
182 return (((sclk / target_ppi_clk) / 2) - 1); in get_eppi_clkdiv()
/linux-4.4.14/sound/aoa/soundbus/i2sbus/
Dpcm.c35 static int clock_and_divisors(int mclk, int sclk, int rate, int *out) in clock_and_divisors() argument
38 if (mclk % sclk) in clock_and_divisors()
41 if (i2s_sf_sclkdiv(mclk / sclk, out)) in clock_and_divisors()
/linux-4.4.14/drivers/net/ethernet/adi/
Dbfin_mac.c386 u32 sclk, mdc_div; in mii_probe() local
392 sclk = get_sclk(); in mii_probe()
393 mdc_div = ((sclk / MDC_CLK) / 2) - 1; in mii_probe()
450 MDC_CLK, mdc_div, sclk/1000000); in mii_probe()