1758 				    SISLANDS_SMC_SCLK_VALUE *sclk);
2322 		prev_sclk = state->performance_levels[i-1].sclk;  in si_populate_power_containment_values()
2323 		max_sclk  = state->performance_levels[i].sclk;  in si_populate_power_containment_values()
2342 		if (min_sclk < state->performance_levels[0].sclk)  in si_populate_power_containment_values()
2343 			min_sclk = state->performance_levels[0].sclk;  in si_populate_power_containment_values()
2417 		if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&  in si_populate_sq_ramping_values()
2852 	u32 sclk = 0;  in si_init_smc_spll_table()  local
2865 		ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);  in si_init_smc_spll_table()
2898 		sclk += 512;  in si_init_smc_spll_table()
2995 	u32 mclk, sclk;  in si_apply_state_adjust_rules()  local
3051 			if (ps->performance_levels[i].sclk > max_limits->sclk)  in si_apply_state_adjust_rules()
3052 				ps->performance_levels[i].sclk = max_limits->sclk;  in si_apply_state_adjust_rules()
3070 			if (ps->performance_levels[i].sclk > max_sclk_vddc)  in si_apply_state_adjust_rules()
3071 				ps->performance_levels[i].sclk = max_sclk_vddc;  in si_apply_state_adjust_rules()
3086 			if (ps->performance_levels[i].sclk > max_sclk)  in si_apply_state_adjust_rules()
3087 				ps->performance_levels[i].sclk = max_sclk;  in si_apply_state_adjust_rules()
3102 		sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;  in si_apply_state_adjust_rules()
3105 		sclk = ps->performance_levels[0].sclk;  in si_apply_state_adjust_rules()
3110 		if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)  in si_apply_state_adjust_rules()
3111 			sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;  in si_apply_state_adjust_rules()
3117 	ps->performance_levels[0].sclk = sclk;  in si_apply_state_adjust_rules()
3123 		sclk = ps->performance_levels[0].sclk;  in si_apply_state_adjust_rules()
3125 			if (sclk < ps->performance_levels[i].sclk)  in si_apply_state_adjust_rules()
3126 				sclk = ps->performance_levels[i].sclk;  in si_apply_state_adjust_rules()
3129 			ps->performance_levels[i].sclk = sclk;  in si_apply_state_adjust_rules()
3134 			if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)  in si_apply_state_adjust_rules()
3135 				ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;  in si_apply_state_adjust_rules()
3168 						   ps->performance_levels[i].sclk,  in si_apply_state_adjust_rules()
4223 					    u16 voltage, u32 sclk, u32 mclk,  in si_populate_phase_shedding_value()  argument
4230 		    (sclk <= limits->entries[i].sclk) &&  in si_populate_phase_shedding_value()
4314 		(u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);  in si_populate_memory_timing_parameters()
4317 					    pl->sclk,  in si_populate_memory_timing_parameters()
4411 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =  in si_populate_smc_initial_state()
4413 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =  in si_populate_smc_initial_state()
4415 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =  in si_populate_smc_initial_state()
4417 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =  in si_populate_smc_initial_state()
4419 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =  in si_populate_smc_initial_state()
4421 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =  in si_populate_smc_initial_state()
4424 	table->initialState.levels[0].sclk.sclk_value =  in si_populate_smc_initial_state()
4425 		cpu_to_be32(initial_state->performance_levels[0].sclk);  in si_populate_smc_initial_state()
4458 						 initial_state->performance_levels[0].sclk,  in si_populate_smc_initial_state()
4610 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =  in si_populate_smc_acpi_state()
4612 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =  in si_populate_smc_acpi_state()
4614 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =  in si_populate_smc_acpi_state()
4616 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =  in si_populate_smc_acpi_state()
4620 	table->ACPIState.levels[0].sclk.sclk_value = 0;  in si_populate_smc_acpi_state()
4796 				    SISLANDS_SMC_SCLK_VALUE *sclk)  in si_calculate_sclk_params()  argument
4853 	sclk->sclk_value = engine_clock;  in si_calculate_sclk_params()
4854 	sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;  in si_calculate_sclk_params()
4855 	sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;  in si_calculate_sclk_params()
4856 	sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;  in si_calculate_sclk_params()
4857 	sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;  in si_calculate_sclk_params()
4858 	sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;  in si_calculate_sclk_params()
4859 	sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;  in si_calculate_sclk_params()
4866 				  SISLANDS_SMC_SCLK_VALUE *sclk)  in si_populate_sclk_value()  argument
4873 		sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);  in si_populate_sclk_value()
4874 		sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);  in si_populate_sclk_value()
4875 		sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);  in si_populate_sclk_value()
4876 		sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);  in si_populate_sclk_value()
4877 		sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);  in si_populate_sclk_value()
4878 		sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);  in si_populate_sclk_value()
4879 		sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);  in si_populate_sclk_value()
5007 	ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);  in si_convert_power_level_to_smc()
5050 				     pl->sclk,  in si_convert_power_level_to_smc()
5084 						       pl->sclk,  in si_convert_power_level_to_smc()
5124 			state->performance_levels[i + 1].sclk,  in si_populate_smc_t()
5125 			state->performance_levels[i].sclk,  in si_populate_smc_t()
5216 	threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;  in si_convert_power_state_to_smc()
5250 				(state->performance_levels[i].sclk < threshold) ?  in si_convert_power_state_to_smc()
6756 	pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);  in si_parse_pplib_clock_info()
6757 	pl->sclk |= clock_info->si.ucEngineClockHigh << 16;  in si_parse_pplib_clock_info()
6803 		pl->sclk = rdev->clock.default_sclk;  in si_parse_pplib_clock_info()
6811 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;  in si_parse_pplib_clock_info()
6894 		u32 sclk, mclk;  in si_parse_power_table()  local
6898 		sclk = le16_to_cpu(clock_info->si.usEngineClockLow);  in si_parse_power_table()
6899 		sclk |= clock_info->si.ucEngineClockHigh << 16;  in si_parse_power_table()
6902 		rdev->pm.dpm.vce_states[i].sclk = sclk;  in si_parse_power_table()
7065 	if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||  in si_dpm_init()
7105 			   current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);  in si_dpm_debugfs_print_current_performance_level()
7123 		return pl->sclk;  in si_dpm_get_current_sclk()