793 	u32 sclk, mclk;  in ci_apply_state_adjust_rules()  local
824 			if (ps->performance_levels[i].sclk > max_limits->sclk)  in ci_apply_state_adjust_rules()
825 				ps->performance_levels[i].sclk = max_limits->sclk;  in ci_apply_state_adjust_rules()
833 		sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
836 		sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
840 		if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)  in ci_apply_state_adjust_rules()
841 			sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;  in ci_apply_state_adjust_rules()
846 	ps->performance_levels[0].sclk = sclk;  in ci_apply_state_adjust_rules()
849 	if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)  in ci_apply_state_adjust_rules()
850 		ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
2351 						  u32 sclk,  in ci_populate_phase_value_based_on_sclk()  argument
2359 		if (sclk < limits->entries[i].sclk) {  in ci_populate_phase_value_based_on_sclk()
2423 					     u32 sclk, u32 min_sclk_in_sr)  in ci_get_sleep_divider_id_from_clock()  argument
2430 	if (sclk < min)  in ci_get_sleep_divider_id_from_clock()
2434 		tmp = sclk / (1 << i);  in ci_get_sleep_divider_id_from_clock()
2493 						u32 sclk,  in ci_populate_memory_timing_parameters()  argument
2501 	radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);  in ci_populate_memory_timing_parameters()
2507 	ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2);  in ci_populate_memory_timing_parameters()
2565 		    boot_state->performance_levels[0].sclk) {  in ci_populate_smc_initial_state()
3131 				    SMU7_Discrete_GraphicsLevel *sclk)  in ci_calculate_sclk_params()  argument
3175 	sclk->SclkFrequency = engine_clock;  in ci_calculate_sclk_params()
3176 	sclk->CgSpllFuncCntl3 = spll_func_cntl_3;  in ci_calculate_sclk_params()
3177 	sclk->CgSpllFuncCntl4 = spll_func_cntl_4;  in ci_calculate_sclk_params()
3178 	sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;  in ci_calculate_sclk_params()
3179 	sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;  in ci_calculate_sclk_params()
3180 	sclk->SclkDid = (u8)dividers.post_divider;  in ci_calculate_sclk_params()
3736 				  state->performance_levels[0].sclk,  in ci_trim_dpm_states()
3737 				  state->performance_levels[high_limit_count].sclk);  in ci_trim_dpm_states()
3831 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_find_dpm_states_clocks_in_dpm_table()  local
3839 		if (sclk == sclk_table->dpm_levels[i].value)  in ci_find_dpm_states_clocks_in_dpm_table()
3869 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()  local
3878 		dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4913 	rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =  in ci_set_private_data_variables_based_on_pptable()
5449 	pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);  in ci_parse_pplib_clock_info()
5450 	pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;  in ci_parse_pplib_clock_info()
5475 		pl->sclk = pi->vbios_boot_state.sclk_bootup_value;  in ci_parse_pplib_clock_info()
5584 		u32 sclk, mclk;  in ci_parse_power_table()  local
5588 		sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);  in ci_parse_power_table()
5589 		sclk |= clock_info->ci.ucEngineClockHigh << 16;  in ci_parse_power_table()
5592 		rdev->pm.dpm.vce_states[i].sclk = sclk;  in ci_parse_power_table()
5883 	if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||  in ci_dpm_init()
5898 	u32 sclk = ci_get_average_sclk_freq(rdev);  in ci_dpm_debugfs_print_current_performance_level()  local
5904 		   sclk, mclk);  in ci_dpm_debugfs_print_current_performance_level()
5920 		       i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);  in ci_dpm_print_power_state()
5927 	u32 sclk = ci_get_average_sclk_freq(rdev);  in ci_dpm_get_current_sclk()  local
5929 	return sclk;  in ci_dpm_get_current_sclk()
5945 		return requested_state->performance_levels[0].sclk;  in ci_dpm_get_sclk()
5947 		return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;  in ci_dpm_get_sclk()