910 	u32 sclk, mclk;  in ci_apply_state_adjust_rules()  local
941 			if (ps->performance_levels[i].sclk > max_limits->sclk)  in ci_apply_state_adjust_rules()
942 				ps->performance_levels[i].sclk = max_limits->sclk;  in ci_apply_state_adjust_rules()
950 		sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
953 		sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
957 		if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)  in ci_apply_state_adjust_rules()
958 			sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;  in ci_apply_state_adjust_rules()
963 	ps->performance_levels[0].sclk = sclk;  in ci_apply_state_adjust_rules()
966 	if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)  in ci_apply_state_adjust_rules()
967 		ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
2482 						  u32 sclk,  in ci_populate_phase_value_based_on_sclk()  argument
2490 		if (sclk < limits->entries[i].sclk) {  in ci_populate_phase_value_based_on_sclk()
2554 					     u32 sclk, u32 min_sclk_in_sr)  in ci_get_sleep_divider_id_from_clock()  argument
2561 	if (sclk < min)  in ci_get_sleep_divider_id_from_clock()
2565 		tmp = sclk / (1 << i);  in ci_get_sleep_divider_id_from_clock()
2623 						u32 sclk,  in ci_populate_memory_timing_parameters()  argument
2631 	amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk);  in ci_populate_memory_timing_parameters()
2637 	ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2);  in ci_populate_memory_timing_parameters()
2695 		    boot_state->performance_levels[0].sclk) {  in ci_populate_smc_initial_state()
3269 				    SMU7_Discrete_GraphicsLevel *sclk)  in ci_calculate_sclk_params()  argument
3313 	sclk->SclkFrequency = engine_clock;  in ci_calculate_sclk_params()
3314 	sclk->CgSpllFuncCntl3 = spll_func_cntl_3;  in ci_calculate_sclk_params()
3315 	sclk->CgSpllFuncCntl4 = spll_func_cntl_4;  in ci_calculate_sclk_params()
3316 	sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;  in ci_calculate_sclk_params()
3317 	sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;  in ci_calculate_sclk_params()
3318 	sclk->SclkDid = (u8)dividers.post_divider;  in ci_calculate_sclk_params()
3872 				  state->performance_levels[0].sclk,  in ci_trim_dpm_states()
3873 				  state->performance_levels[high_limit_count].sclk);  in ci_trim_dpm_states()
3969 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_find_dpm_states_clocks_in_dpm_table()  local
3977 		if (sclk == sclk_table->dpm_levels[i].value)  in ci_find_dpm_states_clocks_in_dpm_table()
4007 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()  local
4016 		dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
5081 	adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =  in ci_set_private_data_variables_based_on_pptable()
5595 	pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);  in ci_parse_pplib_clock_info()
5596 	pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;  in ci_parse_pplib_clock_info()
5621 		pl->sclk = pi->vbios_boot_state.sclk_bootup_value;  in ci_parse_pplib_clock_info()
5730 		u32 sclk, mclk;  in ci_parse_power_table()  local
5734 		sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);  in ci_parse_power_table()
5735 		sclk |= clock_info->ci.ucEngineClockHigh << 16;  in ci_parse_power_table()
5738 		adev->pm.dpm.vce_states[i].sclk = sclk;  in ci_parse_power_table()
6069 	if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||  in ci_dpm_init()
6085 	u32 sclk = ci_get_average_sclk_freq(adev);  in ci_dpm_debugfs_print_current_performance_level()  local
6091 		   sclk, mclk);  in ci_dpm_debugfs_print_current_performance_level()
6107 		       i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);  in ci_dpm_print_power_state()
6118 		return requested_state->performance_levels[0].sclk;  in ci_dpm_get_sclk()
6120 		return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;  in ci_dpm_get_sclk()