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Searched refs:clks (Results 1 – 200 of 299) sorted by relevance

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/linux-4.4.14/drivers/clk/imx/
Dclk-imx7d.c25 static struct clk *clks[IMX7D_CLK_END]; variable
367 &clks[IMX7D_UART1_ROOT_CLK],
368 &clks[IMX7D_UART2_ROOT_CLK],
369 &clks[IMX7D_UART3_ROOT_CLK],
370 &clks[IMX7D_UART4_ROOT_CLK],
371 &clks[IMX7D_UART5_ROOT_CLK],
372 &clks[IMX7D_UART6_ROOT_CLK],
373 &clks[IMX7D_UART7_ROOT_CLK],
383 clks[IMX7D_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx7d_clocks_init()
384 clks[IMX7D_OSC_24M_CLK] = of_clk_get_by_name(ccm_node, "osc"); in imx7d_clocks_init()
[all …]
Dclk-imx6sx.c92 static struct clk *clks[IMX6SX_CLK_CLK_END]; variable
139 &clks[IMX6SX_CLK_UART_IPG],
140 &clks[IMX6SX_CLK_UART_SERIAL],
150 clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx6sx_clocks_init()
152 clks[IMX6SX_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); in imx6sx_clocks_init()
153 clks[IMX6SX_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); in imx6sx_clocks_init()
156 clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); in imx6sx_clocks_init()
157 clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); in imx6sx_clocks_init()
160 clks[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); in imx6sx_clocks_init()
166 …clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
[all …]
Dclk-imx6ul.c68 static struct clk *clks[IMX6UL_CLK_END]; variable
112 clks[IMX6UL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx6ul_clocks_init()
114 clks[IMX6UL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); in imx6ul_clocks_init()
115 clks[IMX6UL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); in imx6ul_clocks_init()
118 clks[IMX6UL_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); in imx6ul_clocks_init()
119 clks[IMX6UL_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); in imx6ul_clocks_init()
125 …clks[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
126 …clks[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
127 …clks[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
128 …clks[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
[all …]
Dclk-imx6sl.c102 static struct clk *clks[IMX6SL_CLK_END]; variable
189 &clks[IMX6SL_CLK_UART],
190 &clks[IMX6SL_CLK_UART_SERIAL],
201 clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx6sl_clocks_init()
202 clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); in imx6sl_clocks_init()
203 clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); in imx6sl_clocks_init()
205 clks[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); in imx6sl_clocks_init()
212 …clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
213 …clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
214 …clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
[all …]
Dclk.c10 void __init imx_check_clocks(struct clk *clks[], unsigned int count) in imx_check_clocks() argument
15 if (IS_ERR(clks[i])) in imx_check_clocks()
17 i, PTR_ERR(clks[i])); in imx_check_clocks()
91 void __init imx_register_uart_clocks(struct clk ** const clks[]) in imx_register_uart_clocks() argument
96 imx_uart_clocks = clks; in imx_register_uart_clocks()
Dclk.h9 void imx_check_clocks(struct clk *clks[], unsigned int count);
10 void imx_register_uart_clocks(struct clk ** const clks[]);
/linux-4.4.14/drivers/clk/hisilicon/
Dclk.c65 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
75 void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks, in hisi_clk_register_fixed_rate() argument
82 clk = clk_register_fixed_rate(NULL, clks[i].name, in hisi_clk_register_fixed_rate()
83 clks[i].parent_name, in hisi_clk_register_fixed_rate()
84 clks[i].flags, in hisi_clk_register_fixed_rate()
85 clks[i].fixed_rate); in hisi_clk_register_fixed_rate()
88 __func__, clks[i].name); in hisi_clk_register_fixed_rate()
91 data->clk_data.clks[clks[i].id] = clk; in hisi_clk_register_fixed_rate()
95 void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks, in hisi_clk_register_fixed_factor() argument
103 clk = clk_register_fixed_factor(NULL, clks[i].name, in hisi_clk_register_fixed_factor()
[all …]
Dclk-hix5hd2.c256 hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums, in hix5hd2_clk_register_complex() argument
271 init.name = clks[i].name; in hix5hd2_clk_register_complex()
272 if (clks[i].type == TYPE_ETHER) in hix5hd2_clk_register_complex()
279 (clks[i].parent_name ? &clks[i].parent_name : NULL); in hix5hd2_clk_register_complex()
280 init.num_parents = (clks[i].parent_name ? 1 : 0); in hix5hd2_clk_register_complex()
282 p_clk->ctrl_reg = base + clks[i].ctrl_reg; in hix5hd2_clk_register_complex()
283 p_clk->ctrl_clk_mask = clks[i].ctrl_clk_mask; in hix5hd2_clk_register_complex()
284 p_clk->ctrl_rst_mask = clks[i].ctrl_rst_mask; in hix5hd2_clk_register_complex()
285 p_clk->phy_reg = base + clks[i].phy_reg; in hix5hd2_clk_register_complex()
286 p_clk->phy_clk_mask = clks[i].phy_clk_mask; in hix5hd2_clk_register_complex()
[all …]
Dclk-hi3620.c485 clk_data->clks = kzalloc(sizeof(struct clk *) * num, GFP_KERNEL); in hi3620_mmc_clk_init()
486 if (!clk_data->clks) { in hi3620_mmc_clk_init()
493 clk_data->clks[mmc_clk->id] = in hi3620_mmc_clk_init()
/linux-4.4.14/drivers/clk/mmp/
Dclk.c20 unit->clk_data.clks = clk_table; in mmp_clk_init()
26 struct mmp_param_fixed_rate_clk *clks, in mmp_register_fixed_rate_clks() argument
33 clk = clk_register_fixed_rate(NULL, clks[i].name, in mmp_register_fixed_rate_clks()
34 clks[i].parent_name, in mmp_register_fixed_rate_clks()
35 clks[i].flags, in mmp_register_fixed_rate_clks()
36 clks[i].fixed_rate); in mmp_register_fixed_rate_clks()
39 __func__, clks[i].name); in mmp_register_fixed_rate_clks()
42 if (clks[i].id) in mmp_register_fixed_rate_clks()
43 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
48 struct mmp_param_fixed_factor_clk *clks, in mmp_register_fixed_factor_clks() argument
[all …]
Dclk.h150 struct mmp_param_fixed_rate_clk *clks,
162 struct mmp_param_fixed_factor_clk *clks,
176 struct mmp_param_general_gate_clk *clks,
192 struct mmp_param_gate_clk *clks,
208 struct mmp_param_mux_clk *clks,
223 struct mmp_param_div_clk *clks,
/linux-4.4.14/drivers/clk/mxs/
Dclk-imx28.c151 static struct clk *clks[clk_max]; variable
173 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx28_clocks_init()
174 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
175 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
176 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
177 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
178 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
179 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
180 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
181 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); in mx28_clocks_init()
[all …]
Dclk-imx23.c96 static struct clk *clks[clk_max]; variable
118 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx23_clocks_init()
119 clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); in mx23_clocks_init()
120 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); in mx23_clocks_init()
121 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); in mx23_clocks_init()
122 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); in mx23_clocks_init()
123 clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); in mx23_clocks_init()
124 clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll)); in mx23_clocks_init()
125 clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix)); in mx23_clocks_init()
126 clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io)); in mx23_clocks_init()
[all …]
/linux-4.4.14/arch/powerpc/platforms/512x/
Dclock-commonclk.c74 static struct clk *clks[MPC512x_CLK_LAST_PRIVATE]; variable
404 for (i = 0; i < ARRAY_SIZE(clks); i++) in mpc512x_clk_preset_data()
405 clks[i] = ERR_PTR(-ENODEV); in mpc512x_clk_preset_data()
447 clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1); in mpc512x_clk_setup_ref_clock()
448 calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]); in mpc512x_clk_setup_ref_clock()
462 clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq); in mpc512x_clk_setup_ref_clock()
651 div = clk_get_rate(clks[MPC512x_CLK_SYS]); in mpc512x_clk_setup_mclk()
652 div /= clk_get_rate(clks[MPC512x_CLK_IPS]); in mpc512x_clk_setup_mclk()
675 clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed( in mpc512x_clk_setup_mclk()
682 clks[clks_idx_int + MCLK_IDX_EN0] = mpc512x_clk_gated( in mpc512x_clk_setup_mclk()
[all …]
/linux-4.4.14/arch/arm/boot/dts/
Dimx27.dtsi73 clocks = <&clks IMX27_CLK_CPU_DIV>;
96 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
97 <&clks IMX27_CLK_DMA_AHB_GATE>;
107 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
114 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
115 <&clks IMX27_CLK_PER1_GATE>;
123 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
124 <&clks IMX27_CLK_PER1_GATE>;
132 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
133 <&clks IMX27_CLK_PER1_GATE>;
[all …]
Dimx6sx.dtsi74 clocks = <&clks IMX6SX_CLK_ARM>,
75 <&clks IMX6SX_CLK_PLL2_PFD2>,
76 <&clks IMX6SX_CLK_STEP>,
77 <&clks IMX6SX_CLK_PLL1_SW>,
78 <&clks IMX6SX_CLK_PLL1_SYS>;
147 clocks = <&clks IMX6SX_CLK_OCRAM>;
170 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
181 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
182 <&clks IMX6SX_CLK_GPMI_APB>,
183 <&clks IMX6SX_CLK_GPMI_BCH>,
[all …]
Dimx25.dtsi86 clocks = <&clks 48>;
97 clocks = <&clks 48>;
107 clocks = <&clks 75>, <&clks 75>;
116 clocks = <&clks 76>, <&clks 76>;
125 clocks = <&clks 120>, <&clks 57>;
134 clocks = <&clks 121>, <&clks 57>;
144 clocks = <&clks 48>;
154 clocks = <&clks 51>;
165 clocks = <&clks 78>, <&clks 78>;
176 clocks = <&clks 102>;
[all …]
Dimx6qdl.dtsi99 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
110 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
111 <&clks IMX6QDL_CLK_GPMI_APB>,
112 <&clks IMX6QDL_CLK_GPMI_BCH>,
113 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
114 <&clks IMX6QDL_CLK_PER1_BCH>;
128 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
129 <&clks IMX6QDL_CLK_HDMI_ISFR>;
155 clocks = <&clks IMX6QDL_CLK_TWD>;
188 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
[all …]
Dimx53.dtsi54 clocks = <&clks IMX5_CLK_ARM>;
120 clocks = <&clks IMX5_CLK_SATA_GATE>,
121 <&clks IMX5_CLK_SATA_REF>,
122 <&clks IMX5_CLK_AHB>;
133 clocks = <&clks IMX5_CLK_IPU_GATE>,
134 <&clks IMX5_CLK_IPU_DI0_GATE>,
135 <&clks IMX5_CLK_IPU_DI1_GATE>;
193 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
194 <&clks IMX5_CLK_DUMMY>,
195 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
[all …]
Dvfxxx.dtsi90 clocks = <&clks VF610_CLK_DMAMUX0>,
91 <&clks VF610_CLK_DMAMUX1>;
99 clocks = <&clks VF610_CLK_FLEXCAN0>,
100 <&clks VF610_CLK_FLEXCAN0>;
109 clocks = <&clks VF610_CLK_UART0>;
121 clocks = <&clks VF610_CLK_UART1>;
133 clocks = <&clks VF610_CLK_UART2>;
145 clocks = <&clks VF610_CLK_UART3>;
159 clocks = <&clks VF610_CLK_DSPI0>;
171 clocks = <&clks VF610_CLK_DSPI1>;
[all …]
Dimx51.dtsi85 clocks = <&clks IMX5_CLK_CPU_PODF>;
104 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
132 clocks = <&clks IMX5_CLK_IPU_GATE>,
133 <&clks IMX5_CLK_IPU_DI0_GATE>,
134 <&clks IMX5_CLK_IPU_DI1_GATE>;
171 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
172 <&clks IMX5_CLK_DUMMY>,
173 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
182 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
183 <&clks IMX5_CLK_DUMMY>,
[all …]
Dimx6ul.dtsi67 clocks = <&clks IMX6UL_CLK_ARM>,
68 <&clks IMX6UL_CLK_PLL2_BUS>,
69 <&clks IMX6UL_CLK_PLL2_PFD2>,
70 <&clks IMX6UL_CA7_SECONDARY_SEL>,
71 <&clks IMX6UL_CLK_STEP>,
72 <&clks IMX6UL_CLK_PLL1_SW>,
73 <&clks IMX6UL_CLK_PLL1_SYS>,
74 <&clks IMX6UL_PLL1_BYPASS>,
75 <&clks IMX6UL_CLK_PLL1>,
76 <&clks IMX6UL_PLL1_BYPASS_SRC>,
[all …]
Dimx50.dtsi105 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
106 <&clks IMX5_CLK_DUMMY>,
107 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
117 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
118 <&clks IMX5_CLK_DUMMY>,
119 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
129 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
130 <&clks IMX5_CLK_UART3_PER_GATE>;
141 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
142 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
[all …]
Dimx35.dtsi70 clocks = <&clks 51>;
81 clocks = <&clks 53>;
90 clocks = <&clks 9>, <&clks 70>;
99 clocks = <&clks 9>, <&clks 71>;
110 clocks = <&clks 52>;
121 clocks = <&clks 68>;
134 clocks = <&clks 35 &clks 35>;
156 clocks = <&clks 9>, <&clks 72>;
168 clocks = <&clks 36 &clks 36>;
176 clocks = <&clks 46>, <&clks 8>;
[all …]
Dimx6sl.dtsi58 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
59 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
60 <&clks IMX6SL_CLK_PLL1_SYS>;
105 clocks = <&clks IMX6SL_CLK_OCRAM>;
145 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
146 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
147 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
148 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
149 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
164 clocks = <&clks IMX6SL_CLK_ECSPI1>,
[all …]
Dimx1.dtsi49 clocks = <&clks IMX1_CLK_MCU>;
72 clocks = <&clks IMX1_CLK_HCLK>,
73 <&clks IMX1_CLK_PER1>;
81 clocks = <&clks IMX1_CLK_HCLK>,
82 <&clks IMX1_CLK_PER1>;
90 clocks = <&clks IMX1_CLK_DUMMY>,
91 <&clks IMX1_CLK_DUMMY>,
92 <&clks IMX1_CLK_PER2>;
101 clocks = <&clks IMX1_CLK_HCLK>,
102 <&clks IMX1_CLK_PER1>;
[all …]
Dimx7d.dtsi88 clocks = <&clks IMX7D_ARM_A7_ROOT_CLK>, <&clks IMX7D_ARM_A7_ROOT_SRC>,
89 <&clks IMX7D_PLL_ARM_MAIN_CLK>, <&clks IMX7D_PLL_SYS_MAIN_CLK>;
127 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
141 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
192 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
219 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
256 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
296 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
317 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
422 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
[all …]
Dimx6q.dtsi46 clocks = <&clks IMX6QDL_CLK_ARM>,
47 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
48 <&clks IMX6QDL_CLK_STEP>,
49 <&clks IMX6QDL_CLK_PLL1_SW>,
50 <&clks IMX6QDL_CLK_PLL1_SYS>;
84 clocks = <&clks IMX6QDL_CLK_OCRAM>;
95 clocks = <&clks IMX6Q_CLK_ECSPI5>,
96 <&clks IMX6Q_CLK_ECSPI5>;
149 clocks = <&clks IMX6QDL_CLK_SATA>,
150 <&clks IMX6QDL_CLK_SATA_REF_100M>,
[all …]
Dimx6dl.dtsi42 clocks = <&clks IMX6QDL_CLK_ARM>,
43 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44 <&clks IMX6QDL_CLK_STEP>,
45 <&clks IMX6QDL_CLK_PLL1_SW>,
46 <&clks IMX6QDL_CLK_PLL1_SYS>;
66 clocks = <&clks IMX6QDL_CLK_OCRAM>;
97 clocks = <&clks IMX6DL_CLK_I2C4>;
118 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
119 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
120 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
Dimx31.dtsi58 clocks = <&clks 10>, <&clks 30>;
67 clocks = <&clks 10>, <&clks 31>;
75 clocks = <&clks 10>, <&clks 49>;
85 clocks = <&clks 10>, <&clks 50>;
102 clocks = <&clks 10>, <&clks 48>;
111 clocks = <&clks 25>;
114 clks: ccm@53f80000{ label
133 clocks = <&clks 10>, <&clks 22>;
Datlas6.dtsi30 clocks = <&clks 12>;
66 clks: clock-controller@88000000 { label
87 clocks = <&clks 42>;
101 clocks = <&clks 5>;
108 clocks = <&clks 32>;
122 clocks = <&clks 34>;
133 clocks = <&clks 35>;
148 clocks = <&clks 32>;
162 clocks = <&clks 33>;
183 clocks = <&clks 9>;
[all …]
Dpxa27x.dtsi26 clocks = <&clks CLK_NONE>;
33 clocks = <&clks CLK_USBHOST>;
41 clocks = <&clks CLK_PWM0>;
48 clocks = <&clks CLK_PWM1>;
55 clocks = <&clks CLK_PWM0>;
62 clocks = <&clks CLK_PWM1>;
69 clocks = <&clks CLK_PWRI2C>;
79 clocks = <&clks CLK_USB>;
87 clocks = <&clks CLK_KEYPAD>;
100 clocks = <&clks CLK_CAMERA>;
[all …]
Dprima2.dtsi32 clocks = <&clks 12>;
77 clks: clock-controller@88000000 { label
98 clocks = <&clks 42>;
112 clocks = <&clks 5>;
119 clocks = <&clks 32>;
139 clocks = <&clks 35>;
154 clocks = <&clks 32>;
168 clocks = <&clks 33>;
189 clocks = <&clks 9>;
197 clocks = <&clks 8>;
[all …]
Dpxa3xx.dtsi22 clocks = <&clks CLK_PWRI2C>;
32 clocks = <&clks CLK_NAND>;
48 clocks = <&clks CLK_GPIO>;
61 clocks = <&clks CLK_MMC>;
72 clocks = <&clks CLK_MMC1>;
83 clocks = <&clks CLK_MMC2>;
94 clocks = <&clks CLK_USBHOST>;
108 clks: pxa3xx_clks@41300004 { label
119 clocks = <&clks CLK_OSTIMER>;
Daxm55xx.dtsi13 #include <dt-bindings/clock/lsi,axm5516-clks.h>
52 clks: clock-controller@2010020000 { label
53 compatible = "lsi,axm5516-clks";
119 clocks = <&clks AXXIA_CLK_PER>;
128 clocks = <&clks AXXIA_CLK_PER>;
137 clocks = <&clks AXXIA_CLK_PER>;
146 clocks = <&clks AXXIA_CLK_PER>;
163 clocks = <&clks AXXIA_CLK_PER>;
181 clocks = <&clks AXXIA_CLK_PER>;
192 clocks = <&clks AXXIA_CLK_PER>;
Dimx28.dtsi92 clocks = <&clks 25>;
109 clocks = <&clks 50>;
121 clocks = <&clks 46>;
132 clocks = <&clks 47>;
143 clocks = <&clks 48>;
154 clocks = <&clks 49>;
922 clocks = <&clks 26>;
943 clocks = <&clks 25>;
955 clocks = <&clks 55>;
965 clocks = <&clks 58>, <&clks 58>;
[all …]
Dimx23.dtsi69 clocks = <&clks 15>;
85 clocks = <&clks 34>;
95 clocks = <&clks 33>;
370 clocks = <&clks 16>;
390 clocks = <&clks 15>;
402 clocks = <&clks 38>;
409 clocks = <&clks 33>;
428 clks: clkctrl@80040000 { label
472 clocks = <&clks 26>;
504 clocks = <&clks 30>;
[all …]
Dpxa2xx.dtsi83 clocks = <&clks CLK_FFUART>;
91 clocks = <&clks CLK_BTUART>;
99 clocks = <&clks CLK_STUART>;
114 clocks = <&clks CLK_I2C>;
131 clocks = <&clks CLK_MMC>;
Dimx6qdl-sabreauto.dtsi113 &clks {
114 assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
115 <&clks IMX6QDL_PLL4_BYPASS>,
116 <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
117 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
118 <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
119 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
120 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
121 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
122 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
[all …]
Dimx7d-sdb.dts107 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
108 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
109 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
133 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
134 <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
135 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
259 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
268 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
269 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
299 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
Dimx6qdl-sabresd.dtsi144 &clks {
145 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
146 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
147 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
148 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
189 clocks = <&clks IMX6QDL_CLK_CKO>;
Dimx6qdl-sabrelite.dtsi236 &clks {
237 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
238 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
239 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
240 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
293 clocks = <&clks 201>;
Dimx6qdl-nit6xlite.dtsi213 &clks {
214 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
215 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
216 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
217 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
272 clocks = <&clks 201>;
Dimx6qdl-nitrogen6x.dtsi250 &clks {
251 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
252 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
253 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
254 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
307 clocks = <&clks 201>;
Dvf610-twr.dts96 &clks {
171 clocks = <&clks VF610_CLK_SAI2>;
305 assigned-clocks = <&clks VF610_CLK_NFC>;
Dphy3250.dts57 nxp,wdr-clks = <14>;
61 nxp,rdr-clks = <14>;
Dimx6qdl-nitrogen6_max.dtsi348 &clks {
349 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
350 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
351 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
352 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
405 clocks = <&clks 201>;
Dvf500.dtsi43 clocks = <&clks VF610_CLK_PLATFORM_BUS>;
Dea3250.dts53 nxp,wdr-clks = <14>;
57 nxp,rdr-clks = <14>;
Dimx28-m28evk.dts219 clocks = <&clks 57>, <&clks 57>;
Dvf610-cosmic.dts33 &clks {
/linux-4.4.14/arch/powerpc/boot/dts/
Dmpc5121.dtsi54 clocks = <&clks MPC512x_CLK_MBX_BUS>,
55 <&clks MPC512x_CLK_MBX_3D>,
56 <&clks MPC512x_CLK_MBX>;
71 clocks = <&clks MPC512x_CLK_NFC>;
138 clks: clock@f00 { label
163 clocks = <&clks MPC512x_CLK_BDLC>,
164 <&clks MPC512x_CLK_IPS>,
165 <&clks MPC512x_CLK_SYS>,
166 <&clks MPC512x_CLK_REF>,
167 <&clks MPC512x_CLK_MSCAN0_MCLK>;
[all …]
Dmpc5125twr.dts103 clks: clock@f00 { // Clock control label
133 clocks = <&clks MPC512x_CLK_BDLC>,
134 <&clks MPC512x_CLK_IPS>,
135 <&clks MPC512x_CLK_SYS>,
136 <&clks MPC512x_CLK_REF>,
137 <&clks MPC512x_CLK_MSCAN0_MCLK>;
145 clocks = <&clks MPC512x_CLK_BDLC>,
146 <&clks MPC512x_CLK_IPS>,
147 <&clks MPC512x_CLK_SYS>,
148 <&clks MPC512x_CLK_REF>,
[all …]
/linux-4.4.14/drivers/clk/
Dclk-clps711x.c45 struct clk *clks[CLPS711X_CLK_MAX]; member
109 clps711x_clk->clks[CLPS711X_CLK_DUMMY] = in _clps711x_clk_init()
111 clps711x_clk->clks[CLPS711X_CLK_CPU] = in _clps711x_clk_init()
113 clps711x_clk->clks[CLPS711X_CLK_BUS] = in _clps711x_clk_init()
115 clps711x_clk->clks[CLPS711X_CLK_PLL] = in _clps711x_clk_init()
117 clps711x_clk->clks[CLPS711X_CLK_TIMERREF] = in _clps711x_clk_init()
120 clps711x_clk->clks[CLPS711X_CLK_TIMER1] = in _clps711x_clk_init()
124 clps711x_clk->clks[CLPS711X_CLK_TIMER2] = in _clps711x_clk_init()
128 clps711x_clk->clks[CLPS711X_CLK_PWM] = in _clps711x_clk_init()
130 clps711x_clk->clks[CLPS711X_CLK_SPIREF] = in _clps711x_clk_init()
[all …]
Dclk-stm32f4.c139 static struct clk *clks[MAX_CLKS]; variable
292 return clks[i]; in stm32f4_rcc_lookup_clk()
349 clks[SYSTICK] = clk_register_fixed_factor(NULL, "systick", "ahb_div", in stm32f4_rcc_init()
351 clks[FCLK] = clk_register_fixed_factor(NULL, "fclk", "ahb_div", in stm32f4_rcc_init()
363 clks[idx] = clk_register_gate( in stm32f4_rcc_init()
367 if (IS_ERR(clks[n])) { in stm32f4_rcc_init()
Dclk-scpi.c205 struct clk **clks; in scpi_clk_add() local
225 clks = devm_kcalloc(dev, count, sizeof(*clks), GFP_KERNEL); in scpi_clk_add()
226 if (!clks) in scpi_clk_add()
252 clks[idx] = scpi_clk_ops_init(dev, match, sclk, name); in scpi_clk_add()
253 if (IS_ERR_OR_NULL(clks[idx])) in scpi_clk_add()
Dclk-asm9260.c71 static struct clk *clks[MAX_CLKS]; variable
314 clks[dc->idx] = clk_register_divider(NULL, dc->name, in asm9260_acc_init()
324 clks[gd->idx] = clk_register_gate(NULL, gd->name, in asm9260_acc_init()
331 if (!IS_ERR(clks[n])) in asm9260_acc_init()
340 clk_data.clks = clks; in asm9260_acc_init()
Dclk-axm5516.c535 struct clk *clks[]; member
560 priv = devm_kzalloc(dev, sizeof(*priv) + sizeof(*priv->clks) * num_clks, in axmclk_probe()
565 priv->onecell.clks = priv->clks; in axmclk_probe()
576 priv->clks[i] = clk; in axmclk_probe()
Dclk-cdce706.c85 struct clk *clks[6]; member
620 cdce->clks[i] = cdce->clkout[i].clk; in cdce706_register_clkouts()
660 cdce->onecell.clks = cdce->clks; in cdce706_probe()
661 cdce->onecell.clk_num = ARRAY_SIZE(cdce->clks); in cdce706_probe()
Dclk-efm32gg.c20 .clks = clk,
/linux-4.4.14/drivers/clk/zynq/
Dclkc.c72 static struct clk *clks[clk_max]; variable
158 clks[fclk] = clk_register_gate(NULL, clk_name, in zynq_clk_register_fclk()
163 if (clk_prepare_enable(clks[fclk])) in zynq_clk_register_fclk()
182 clks[fclk] = ERR_PTR(-ENOMEM); in zynq_clk_register_fclk()
209 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, in zynq_clk_register_periph_clk()
212 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, in zynq_clk_register_periph_clk()
221 clks[clk0] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
223 clks[clk1] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
274 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], in zynq_clk_setup()
280 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], in zynq_clk_setup()
[all …]
/linux-4.4.14/drivers/clk/versatile/
Dclk-impd1.c35 struct clk_lookup *clks[15]; member
109 imc->clks[0] = clkdev_alloc(pclk, "apb_pclk", "lm%x:01000", id); in integrator_impd1_clk_init()
110 imc->clks[1] = clkdev_alloc(clk, NULL, "lm%x:01000", id); in integrator_impd1_clk_init()
119 imc->clks[2] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00700", id); in integrator_impd1_clk_init()
120 imc->clks[3] = clkdev_alloc(clk, NULL, "lm%x:00700", id); in integrator_impd1_clk_init()
127 imc->clks[4] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00100", id); in integrator_impd1_clk_init()
128 imc->clks[5] = clkdev_alloc(clk, NULL, "lm%x:00100", id); in integrator_impd1_clk_init()
129 imc->clks[6] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00200", id); in integrator_impd1_clk_init()
130 imc->clks[7] = clkdev_alloc(clk, NULL, "lm%x:00200", id); in integrator_impd1_clk_init()
136 imc->clks[8] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00300", id); in integrator_impd1_clk_init()
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/sound/
Dfsl,asrc.txt43 clocks = <&clks 107>, <&clks 107>, <&clks 0>,
44 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
45 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
46 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
47 <&clks 107>, <&clks 0>, <&clks 0>;
Dfsl,spdif.txt45 clocks = <&clks 197>, <&clks 3>,
46 <&clks 197>, <&clks 107>,
47 <&clks 0>, <&clks 118>,
48 <&clks 62>, <&clks 139>,
49 <&clks 0>;
Dfsl-sai.txt64 clocks = <&clks VF610_CLK_PLATFORM_BUS>,
65 <&clks VF610_CLK_SAI2>,
66 <&clks 0>, <&clks 0>;
Dfsl,esai.txt50 clocks = <&clks 208>, <&clks 118>, <&clks 208>;
Dsirf-audio-codec.txt16 clocks = <&clks 27>;
Des8328.txt36 clocks = <&clks 169>;
Dda7213.txt32 clocks = <&clks 201>;
Dtlv320aic32x4.txt28 clocks = <&clks 201>;
Dsirf-usp.txt21 clocks = <&clks 28>;
Dsgtl5000.txt34 clocks = <&clks 150>;
/linux-4.4.14/drivers/clk/tegra/
Dclk.c78 static struct clk **clks; variable
211 clks = kzalloc(num * sizeof(struct clk *), GFP_KERNEL); in tegra_clk_init()
212 if (!clks) in tegra_clk_init()
217 return clks; in tegra_clk_init()
221 struct clk *clks[], int clk_max) in tegra_init_dup_clks() argument
226 clk = clks[dup_list->clk_id]; in tegra_init_dup_clks()
233 struct clk *clks[], int clk_max) in tegra_init_from_table() argument
238 clk = clks[tbl->clk_id]; in tegra_init_from_table()
248 struct clk *parent = clks[tbl->parent_id]; in tegra_init_from_table()
290 if (IS_ERR(clks[i])) { in tegra_add_of_provider()
[all …]
Dclk-tegra20.c166 static struct clk **clks; variable
642 clks[TEGRA20_CLK_PLL_C] = clk; in tegra20_pll_init()
651 clks[TEGRA20_CLK_PLL_C_OUT1] = clk; in tegra20_pll_init()
657 clks[TEGRA20_CLK_PLL_M] = clk; in tegra20_pll_init()
666 clks[TEGRA20_CLK_PLL_M_OUT1] = clk; in tegra20_pll_init()
671 clks[TEGRA20_CLK_PLL_X] = clk; in tegra20_pll_init()
676 clks[TEGRA20_CLK_PLL_U] = clk; in tegra20_pll_init()
681 clks[TEGRA20_CLK_PLL_D] = clk; in tegra20_pll_init()
686 clks[TEGRA20_CLK_PLL_D_OUT0] = clk; in tegra20_pll_init()
691 clks[TEGRA20_CLK_PLL_A] = clk; in tegra20_pll_init()
[all …]
Dclk-tegra124.c1023 static struct clk **clks; variable
1115 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk; in tegra124_periph_clk_init()
1119 clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk; in tegra124_periph_clk_init()
1124 clks[TEGRA124_CLK_DSIA] = clk; in tegra124_periph_clk_init()
1129 clks[TEGRA124_CLK_DSIB] = clk; in tegra124_periph_clk_init()
1133 clks[TEGRA124_CLK_MC] = clk; in tegra124_periph_clk_init()
1139 clks[TEGRA124_CLK_CML0] = clk; in tegra124_periph_clk_init()
1145 clks[TEGRA124_CLK_CML1] = clk; in tegra124_periph_clk_init()
1160 clks[TEGRA124_CLK_PLL_C] = clk; in tegra124_pll_init()
1170 clks[TEGRA124_CLK_PLL_C_OUT1] = clk; in tegra124_pll_init()
[all …]
Dclk-tegra114.c940 static struct clk **clks; variable
952 clks[TEGRA114_CLK_CLK_32K] = clk; in tegra114_fixed_clk_init()
957 clks[TEGRA114_CLK_CLK_M_DIV2] = clk; in tegra114_fixed_clk_init()
962 clks[TEGRA114_CLK_CLK_M_DIV4] = clk; in tegra114_fixed_clk_init()
1057 clks[TEGRA114_CLK_PLL_C] = clk; in tegra114_pll_init()
1066 clks[TEGRA114_CLK_PLL_C_OUT1] = clk; in tegra114_pll_init()
1071 clks[TEGRA114_CLK_PLL_C2] = clk; in tegra114_pll_init()
1076 clks[TEGRA114_CLK_PLL_C3] = clk; in tegra114_pll_init()
1082 clks[TEGRA114_CLK_PLL_M] = clk; in tegra114_pll_init()
1091 clks[TEGRA114_CLK_PLL_M_OUT1] = clk; in tegra114_pll_init()
[all …]
Dclk-tegra30.c208 static struct clk **clks; variable
929 clks[TEGRA30_CLK_PLL_C] = clk; in tegra30_pll_init()
938 clks[TEGRA30_CLK_PLL_C_OUT1] = clk; in tegra30_pll_init()
944 clks[TEGRA30_CLK_PLL_M] = clk; in tegra30_pll_init()
953 clks[TEGRA30_CLK_PLL_M_OUT1] = clk; in tegra30_pll_init()
958 clks[TEGRA30_CLK_PLL_X] = clk; in tegra30_pll_init()
963 clks[TEGRA30_CLK_PLL_X_OUT0] = clk; in tegra30_pll_init()
968 clks[TEGRA30_CLK_PLL_U] = clk; in tegra30_pll_init()
975 clks[TEGRA30_CLK_PLL_D] = clk; in tegra30_pll_init()
980 clks[TEGRA30_CLK_PLL_D_OUT0] = clk; in tegra30_pll_init()
[all …]
Dclk-tegra-fixed.c32 int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, in tegra_osc_clk_init() argument
58 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks); in tegra_osc_clk_init()
69 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, clks); in tegra_osc_clk_init()
Dclk.h625 struct clk *clks[], int clk_max);
628 struct clk *clks[], int clk_max);
649 int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
/linux-4.4.14/drivers/clk/pxa/
Dclk-pxa.c25 .clks = pxa_clocks,
80 int __init clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks) in clk_pxa_cken_init() argument
88 pxa_clk->is_in_low_power = clks[i].is_in_low_power; in clk_pxa_cken_init()
89 pxa_clk->lp = clks[i].lp; in clk_pxa_cken_init()
90 pxa_clk->hp = clks[i].hp; in clk_pxa_cken_init()
91 pxa_clk->gate = clks[i].gate; in clk_pxa_cken_init()
93 clk = clk_register_composite(NULL, clks[i].name, in clk_pxa_cken_init()
94 clks[i].parent_names, 2, in clk_pxa_cken_init()
98 clks[i].flags); in clk_pxa_cken_init()
99 clkdev_pxa_register(clks[i].ckid, clks[i].con_id, in clk_pxa_cken_init()
[all …]
Dclk-pxa25x.c60 unsigned long clks[5]; in pxa25x_get_clk_frequency_khz() local
66 clks[i] = 0; in pxa25x_get_clk_frequency_khz()
68 clks[i] = clk_get_rate(clk); in pxa25x_get_clk_frequency_khz()
75 clks[1] / 1000000, (clks[1] % 1000000) / 10000); in pxa25x_get_clk_frequency_khz()
77 clks[2] / 1000000, (clks[2] % 1000000) / 10000); in pxa25x_get_clk_frequency_khz()
79 clks[3] / 1000000, (clks[3] % 1000000) / 10000); in pxa25x_get_clk_frequency_khz()
82 return (unsigned int)clks[0] / KHz; in pxa25x_get_clk_frequency_khz()
Dclk-pxa27x.c61 unsigned long clks[5]; in pxa27x_get_clk_frequency_khz() local
67 clks[i] = 0; in pxa27x_get_clk_frequency_khz()
69 clks[i] = clk_get_rate(clk); in pxa27x_get_clk_frequency_khz()
75 clks[1] / 1000000, (clks[1] % 1000000) / 10000); in pxa27x_get_clk_frequency_khz()
77 clks[2] / 1000000, (clks[2] % 1000000) / 10000); in pxa27x_get_clk_frequency_khz()
79 clks[3] / 1000000, (clks[3] % 1000000) / 10000); in pxa27x_get_clk_frequency_khz()
81 clks[4] / 1000000, (clks[4] % 1000000) / 10000); in pxa27x_get_clk_frequency_khz()
83 return (unsigned int)clks[0] / KHz; in pxa27x_get_clk_frequency_khz()
Dclk-pxa3xx.c59 unsigned long clks[5]; in pxa3xx_get_clk_frequency_khz() local
65 clks[i] = 0; in pxa3xx_get_clk_frequency_khz()
67 clks[i] = clk_get_rate(clk); in pxa3xx_get_clk_frequency_khz()
73 clks[1] / 1000000, (clks[0] % 1000000) / 10000); in pxa3xx_get_clk_frequency_khz()
75 clks[2] / 1000000, (clks[1] % 1000000) / 10000); in pxa3xx_get_clk_frequency_khz()
77 clks[3] / 1000000, (clks[2] % 1000000) / 10000); in pxa3xx_get_clk_frequency_khz()
79 clks[4] / 1000000, (clks[4] % 1000000) / 10000); in pxa3xx_get_clk_frequency_khz()
81 return (unsigned int)clks[0] / KHz; in pxa3xx_get_clk_frequency_khz()
Dclk-pxa.h105 extern int clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks);
/linux-4.4.14/drivers/clk/sunxi/
Dclk-a10-pll2.c50 struct clk **clks, *base_clk, *prediv_clk; in sun4i_pll2_setup() local
65 clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL); in sun4i_pll2_setup()
66 if (!clks) in sun4i_pll2_setup()
130 clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
135 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X])); in sun4i_pll2_setup()
145 clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
149 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X])); in sun4i_pll2_setup()
154 clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
158 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X])); in sun4i_pll2_setup()
163 clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
[all …]
Dclk-sun6i-apb0-gates.c77 clk_data->clks = devm_kcalloc(&pdev->dev, (ngates + 1), in sun6i_a31_apb0_gates_clk_probe()
79 if (!clk_data->clks) in sun6i_a31_apb0_gates_clk_probe()
86 clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name, in sun6i_a31_apb0_gates_clk_probe()
89 WARN_ON(IS_ERR(clk_data->clks[i])); in sun6i_a31_apb0_gates_clk_probe()
90 clk_register_clkdev(clk_data->clks[i], clk_name, NULL); in sun6i_a31_apb0_gates_clk_probe()
Dclk-mod0.c326 clk_data->clks = kcalloc(3, sizeof(*clk_data->clks), GFP_KERNEL); in sunxi_mmc_setup()
327 if (!clk_data->clks) in sunxi_mmc_setup()
331 clk_data->clks[0] = sunxi_factors_register(node, data, lock, reg); in sunxi_mmc_setup()
332 if (!clk_data->clks[0]) in sunxi_mmc_setup()
335 parent = __clk_get_name(clk_data->clks[0]); in sunxi_mmc_setup()
362 clk_data->clks[i] = clk_register(NULL, &phase->hw); in sunxi_mmc_setup()
363 if (IS_ERR(clk_data->clks[i])) { in sunxi_mmc_setup()
374 kfree(clk_data->clks); in sunxi_mmc_setup()
Dclk-sun9i-mmc.c116 clk_data->clks = devm_kcalloc(&pdev->dev, count, sizeof(struct clk *), in sun9i_a80_mmc_config_clk_probe()
118 if (!clk_data->clks) in sun9i_a80_mmc_config_clk_probe()
144 clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name, in sun9i_a80_mmc_config_clk_probe()
150 if (IS_ERR(clk_data->clks[i])) { in sun9i_a80_mmc_config_clk_probe()
151 ret = PTR_ERR(clk_data->clks[i]); in sun9i_a80_mmc_config_clk_probe()
178 clk_unregister(clk_data->clks[i]); in sun9i_a80_mmc_config_clk_probe()
196 clk_unregister(clk_data->clks[i]); in sun9i_a80_mmc_config_clk_remove()
Dclk-simple-gates.c54 clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL); in sunxi_simple_gates_setup()
55 if (!clk_data->clks) in sunxi_simple_gates_setup()
65 clk_data->clks[index] = clk_register_gate(NULL, clk_name, in sunxi_simple_gates_setup()
72 if (IS_ERR(clk_data->clks[index])) { in sunxi_simple_gates_setup()
79 clk_prepare_enable(clk_data->clks[index]); in sunxi_simple_gates_setup()
Dclk-usb.c125 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL); in sunxi_usb_clk_setup()
126 if (!clk_data->clks) { in sunxi_usb_clk_setup()
135 clk_data->clks[i] = clk_register_gate(NULL, clk_name, in sunxi_usb_clk_setup()
138 WARN_ON(IS_ERR(clk_data->clks[i])); in sunxi_usb_clk_setup()
Dclk-sunxi.c980 struct clk **clks, *pclk; in sunxi_divs_clk_setup() local
1004 clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL); in sunxi_divs_clk_setup()
1005 if (!clks) in sunxi_divs_clk_setup()
1008 clk_data->clks = clks; in sunxi_divs_clk_setup()
1021 clk_data->clks[i] = pclk; in sunxi_divs_clk_setup()
1073 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1, in sunxi_divs_clk_setup()
1079 WARN_ON(IS_ERR(clk_data->clks[i])); in sunxi_divs_clk_setup()
1080 clk_register_clkdev(clks[i], clk_name, NULL); in sunxi_divs_clk_setup()
1093 kfree(clks); in sunxi_divs_clk_setup()
/linux-4.4.14/drivers/clk/mediatek/
Dclk-mtk.c36 clk_data->clks = kcalloc(clk_num, sizeof(*clk_data->clks), GFP_KERNEL); in mtk_alloc_clk_data()
37 if (!clk_data->clks) in mtk_alloc_clk_data()
43 clk_data->clks[i] = ERR_PTR(-ENOENT); in mtk_alloc_clk_data()
52 void __init mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, in mtk_clk_register_fixed_clks() argument
59 const struct mtk_fixed_clk *rc = &clks[i]; in mtk_clk_register_fixed_clks()
71 clk_data->clks[rc->id] = clk; in mtk_clk_register_fixed_clks()
75 void __init mtk_clk_register_factors(const struct mtk_fixed_factor *clks, in mtk_clk_register_factors() argument
82 const struct mtk_fixed_factor *ff = &clks[i]; in mtk_clk_register_factors()
94 clk_data->clks[ff->id] = clk; in mtk_clk_register_factors()
99 const struct mtk_gate *clks, in mtk_clk_register_gates() argument
[all …]
Dclk-mtk.h43 void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
62 void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
148 int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
Dclk-mt8173.c901 clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA15PLL]); in mtk_clk_enable_critical()
902 clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA7PLL]); in mtk_clk_enable_critical()
903 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_MEM_SEL]); in mtk_clk_enable_critical()
904 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); in mtk_clk_enable_critical()
905 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_CCI400_SEL]); in mtk_clk_enable_critical()
906 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_RTC_SEL]); in mtk_clk_enable_critical()
1091 clk_data->clks[cku->id] = clk; in mtk_apmixedsys_init()
/linux-4.4.14/arch/mips/ath79/
Dclock.c32 static struct clk *clks[3]; variable
34 .clks = clks,
35 .clk_num = ARRAY_SIZE(clks),
82 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate); in ar71xx_clocks_init()
83 clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate); in ar71xx_clocks_init()
84 clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate); in ar71xx_clocks_init()
118 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate); in ar724x_clocks_init()
119 clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate); in ar724x_clocks_init()
120 clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate); in ar724x_clocks_init()
151 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate); in ar913x_clocks_init()
[all …]
/linux-4.4.14/drivers/sh/clk/
Dcpg.c94 int __init sh_clk_mstp_register(struct clk *clks, int nr) in sh_clk_mstp_register() argument
101 clkp = clks + k; in sh_clk_mstp_register()
241 static int __init sh_clk_div_register_ops(struct clk *clks, int nr, in sh_clk_div_register_ops() argument
259 clkp = clks + k; in sh_clk_div_register_ops()
336 int __init sh_clk_div6_register(struct clk *clks, int nr) in sh_clk_div6_register() argument
338 return sh_clk_div_register_ops(clks, nr, &sh_clk_div6_table, in sh_clk_div6_register()
342 int __init sh_clk_div6_reparent_register(struct clk *clks, int nr) in sh_clk_div6_reparent_register() argument
344 return sh_clk_div_register_ops(clks, nr, &sh_clk_div6_table, in sh_clk_div6_reparent_register()
389 int __init sh_clk_div4_register(struct clk *clks, int nr, in sh_clk_div4_register() argument
392 return sh_clk_div_register_ops(clks, nr, table, &sh_clk_div_clk_ops); in sh_clk_div4_register()
[all …]
/linux-4.4.14/drivers/clk/pistachio/
Dclk.c27 p->clk_data.clks = kcalloc(num_clks, sizeof(struct clk *), GFP_KERNEL); in pistachio_clk_alloc_provider()
28 if (!p->clk_data.clks) in pistachio_clk_alloc_provider()
41 kfree(p->clk_data.clks); in pistachio_clk_alloc_provider()
52 if (IS_ERR(p->clk_data.clks[i])) in pistachio_clk_register_provider()
54 PTR_ERR(p->clk_data.clks[i])); in pistachio_clk_register_provider()
72 p->clk_data.clks[gate[i].id] = clk; in pistachio_clk_register_gate()
90 p->clk_data.clks[mux[i].id] = clk; in pistachio_clk_register_mux()
106 p->clk_data.clks[div[i].id] = clk; in pistachio_clk_register_div()
120 p->clk_data.clks[ff[i].id] = clk; in pistachio_clk_register_fixed_factor()
131 struct clk *clk = p->clk_data.clks[clk_ids[i]]; in pistachio_clk_force_enable()
/linux-4.4.14/drivers/clk/qcom/
Dcommon.c30 struct clk *clks[]; member
98 struct clk **clks; in qcom_cc_really_probe() local
102 struct clk_regmap **rclks = desc->clks; in qcom_cc_really_probe()
104 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks, in qcom_cc_really_probe()
109 clks = cc->clks; in qcom_cc_really_probe()
111 data->clks = clks; in qcom_cc_really_probe()
116 clks[i] = ERR_PTR(-ENOENT); in qcom_cc_really_probe()
122 clks[i] = clk; in qcom_cc_really_probe()
Dcommon.h27 struct clk_regmap **clks; member
/linux-4.4.14/drivers/clk/shmobile/
Dclk-rz.c71 struct clk **clks; in rz_cpg_clocks_init() local
80 clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL); in rz_cpg_clocks_init()
81 BUG_ON(!cpg || !clks); in rz_cpg_clocks_init()
83 cpg->data.clks = clks; in rz_cpg_clocks_init()
99 cpg->data.clks[i] = clk; in rz_cpg_clocks_init()
Dclk-mstp.c166 struct clk **clks; in cpg_mstp_clocks_init() local
170 clks = kmalloc(MSTP_MAX_CLOCKS * sizeof(*clks), GFP_KERNEL); in cpg_mstp_clocks_init()
171 if (group == NULL || clks == NULL) { in cpg_mstp_clocks_init()
173 kfree(clks); in cpg_mstp_clocks_init()
179 group->data.clks = clks; in cpg_mstp_clocks_init()
187 kfree(clks); in cpg_mstp_clocks_init()
192 clks[i] = ERR_PTR(-ENOENT); in cpg_mstp_clocks_init()
222 clks[clkidx] = cpg_mstp_clock_register(name, parent_name, in cpg_mstp_clocks_init()
224 if (!IS_ERR(clks[clkidx])) { in cpg_mstp_clocks_init()
235 clk_register_clkdev(clks[clkidx], name, NULL); in cpg_mstp_clocks_init()
[all …]
Dclk-r8a7778.c83 struct clk **clks; in r8a7778_cpg_clocks_init() local
94 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); in r8a7778_cpg_clocks_init()
95 if (cpg == NULL || clks == NULL) { in r8a7778_cpg_clocks_init()
104 cpg->data.clks = clks; in r8a7778_cpg_clocks_init()
123 cpg->data.clks[i] = clk; in r8a7778_cpg_clocks_init()
Dclk-r8a7779.c127 struct clk **clks; in r8a7779_cpg_clocks_init() local
138 clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL); in r8a7779_cpg_clocks_init()
139 if (cpg == NULL || clks == NULL) { in r8a7779_cpg_clocks_init()
148 cpg->data.clks = clks; in r8a7779_cpg_clocks_init()
167 cpg->data.clks[i] = clk; in r8a7779_cpg_clocks_init()
Dclk-r8a7740.c150 struct clk **clks; in r8a7740_cpg_clocks_init() local
164 clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL); in r8a7740_cpg_clocks_init()
165 if (cpg == NULL || clks == NULL) { in r8a7740_cpg_clocks_init()
174 cpg->data.clks = clks; in r8a7740_cpg_clocks_init()
193 cpg->data.clks[i] = clk; in r8a7740_cpg_clocks_init()
Dclk-sh73a0.c167 struct clk **clks; in sh73a0_cpg_clocks_init() local
178 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); in sh73a0_cpg_clocks_init()
179 if (cpg == NULL || clks == NULL) { in sh73a0_cpg_clocks_init()
188 cpg->data.clks = clks; in sh73a0_cpg_clocks_init()
212 cpg->data.clks[i] = clk; in sh73a0_cpg_clocks_init()
Dclk-r8a73a4.c195 struct clk **clks; in r8a73a4_cpg_clocks_init() local
206 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); in r8a73a4_cpg_clocks_init()
207 if (cpg == NULL || clks == NULL) { in r8a73a4_cpg_clocks_init()
216 cpg->data.clks = clks; in r8a73a4_cpg_clocks_init()
235 cpg->data.clks[i] = clk; in r8a73a4_cpg_clocks_init()
Dclk-rcar-gen2.c371 struct clk **clks; in rcar_gen2_cpg_clocks_init() local
382 clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL); in rcar_gen2_cpg_clocks_init()
383 if (cpg == NULL || clks == NULL) { in rcar_gen2_cpg_clocks_init()
393 cpg->data.clks = clks; in rcar_gen2_cpg_clocks_init()
414 cpg->data.clks[i] = clk; in rcar_gen2_cpg_clocks_init()
/linux-4.4.14/drivers/video/fbdev/
Dsimplefb.c175 struct clk **clks; member
212 par->clks = kcalloc(par->clk_count, sizeof(struct clk *), GFP_KERNEL); in simplefb_clocks_init()
213 if (!par->clks) in simplefb_clocks_init()
221 if (par->clks[i]) in simplefb_clocks_init()
222 clk_put(par->clks[i]); in simplefb_clocks_init()
224 kfree(par->clks); in simplefb_clocks_init()
231 par->clks[i] = clock; in simplefb_clocks_init()
235 if (par->clks[i]) { in simplefb_clocks_init()
236 ret = clk_prepare_enable(par->clks[i]); in simplefb_clocks_init()
241 clk_put(par->clks[i]); in simplefb_clocks_init()
[all …]
/linux-4.4.14/drivers/usb/host/
Dohci-st.c34 struct clk *clks[USB_MAX_CLKS]; member
70 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) { in st_ohci_platform_power_on()
71 ret = clk_prepare_enable(priv->clks[clk]); in st_ohci_platform_power_on()
90 clk_disable_unprepare(priv->clks[clk]); in st_ohci_platform_power_on()
115 if (priv->clks[clk]) in st_ohci_platform_power_off()
116 clk_disable_unprepare(priv->clks[clk]); in st_ohci_platform_power_off()
173 priv->clks[clk] = of_clk_get(dev->dev.of_node, clk); in st_ohci_platform_probe()
174 if (IS_ERR(priv->clks[clk])) { in st_ohci_platform_probe()
175 err = PTR_ERR(priv->clks[clk]); in st_ohci_platform_probe()
178 priv->clks[clk] = NULL; in st_ohci_platform_probe()
[all …]
Dehci-st.c35 struct clk *clks[USB_MAX_CLKS]; member
89 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) { in st_ehci_platform_power_on()
90 ret = clk_prepare_enable(priv->clks[clk]); in st_ehci_platform_power_on()
109 clk_disable_unprepare(priv->clks[clk]); in st_ehci_platform_power_on()
133 if (priv->clks[clk]) in st_ehci_platform_power_off()
134 clk_disable_unprepare(priv->clks[clk]); in st_ehci_platform_power_off()
191 priv->clks[clk] = of_clk_get(dev->dev.of_node, clk); in st_ehci_platform_probe()
192 if (IS_ERR(priv->clks[clk])) { in st_ehci_platform_probe()
193 err = PTR_ERR(priv->clks[clk]); in st_ehci_platform_probe()
196 priv->clks[clk] = NULL; in st_ehci_platform_probe()
[all …]
Dohci-platform.c39 struct clk *clks[OHCI_MAX_CLKS]; member
53 for (clk = 0; clk < OHCI_MAX_CLKS && priv->clks[clk]; clk++) { in ohci_platform_power_on()
54 ret = clk_prepare_enable(priv->clks[clk]); in ohci_platform_power_on()
79 clk_disable_unprepare(priv->clks[clk]); in ohci_platform_power_on()
96 if (priv->clks[clk]) in ohci_platform_power_off()
97 clk_disable_unprepare(priv->clks[clk]); in ohci_platform_power_off()
189 priv->clks[clk] = of_clk_get(dev->dev.of_node, clk); in ohci_platform_probe()
190 if (IS_ERR(priv->clks[clk])) { in ohci_platform_probe()
191 err = PTR_ERR(priv->clks[clk]); in ohci_platform_probe()
194 priv->clks[clk] = NULL; in ohci_platform_probe()
[all …]
Dehci-platform.c45 struct clk *clks[EHCI_MAX_CLKS]; member
85 for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++) { in ehci_platform_power_on()
86 ret = clk_prepare_enable(priv->clks[clk]); in ehci_platform_power_on()
111 clk_disable_unprepare(priv->clks[clk]); in ehci_platform_power_on()
128 if (priv->clks[clk]) in ehci_platform_power_off()
129 clk_disable_unprepare(priv->clks[clk]); in ehci_platform_power_off()
226 priv->clks[clk] = of_clk_get(dev->dev.of_node, clk); in ehci_platform_probe()
227 if (IS_ERR(priv->clks[clk])) { in ehci_platform_probe()
228 err = PTR_ERR(priv->clks[clk]); in ehci_platform_probe()
231 priv->clks[clk] = NULL; in ehci_platform_probe()
[all …]
/linux-4.4.14/drivers/clk/bcm/
Dclk-iproc-asiu.c41 struct iproc_asiu_clk *clks; member
201 asiu->clk_data.clks = kcalloc(num_clks, sizeof(*asiu->clk_data.clks), in iproc_asiu_setup()
203 if (WARN_ON(!asiu->clk_data.clks)) in iproc_asiu_setup()
206 asiu->clks = kcalloc(num_clks, sizeof(*asiu->clks), GFP_KERNEL); in iproc_asiu_setup()
207 if (WARN_ON(!asiu->clks)) in iproc_asiu_setup()
230 asiu_clk = &asiu->clks[i]; in iproc_asiu_setup()
246 asiu->clk_data.clks[i] = clk; in iproc_asiu_setup()
258 clk_unregister(asiu->clk_data.clks[i]); in iproc_asiu_setup()
265 kfree(asiu->clks); in iproc_asiu_setup()
268 kfree(asiu->clk_data.clks); in iproc_asiu_setup()
Dclk-bcm2835.c291 struct clk *clks[BCM2835_CLOCK_COUNT]; member
1477 struct clk **clks; in bcm2835_clk_probe() local
1499 cprman->onecell.clks = cprman->clks; in bcm2835_clk_probe()
1500 clks = cprman->clks; in bcm2835_clk_probe()
1502 clks[BCM2835_PLLA] = bcm2835_register_pll(cprman, &bcm2835_plla_data); in bcm2835_clk_probe()
1503 clks[BCM2835_PLLB] = bcm2835_register_pll(cprman, &bcm2835_pllb_data); in bcm2835_clk_probe()
1504 clks[BCM2835_PLLC] = bcm2835_register_pll(cprman, &bcm2835_pllc_data); in bcm2835_clk_probe()
1505 clks[BCM2835_PLLD] = bcm2835_register_pll(cprman, &bcm2835_plld_data); in bcm2835_clk_probe()
1506 clks[BCM2835_PLLH] = bcm2835_register_pll(cprman, &bcm2835_pllh_data); in bcm2835_clk_probe()
1508 clks[BCM2835_PLLA_CORE] = in bcm2835_clk_probe()
[all …]
Dclk-iproc-pll.c87 struct iproc_clk *clks; member
611 pll->clk_data.clks = kcalloc(num_clks, sizeof(*pll->clk_data.clks), in iproc_pll_clk_setup()
613 if (WARN_ON(!pll->clk_data.clks)) in iproc_pll_clk_setup()
616 pll->clks = kcalloc(num_clks, sizeof(*pll->clks), GFP_KERNEL); in iproc_pll_clk_setup()
617 if (WARN_ON(!pll->clks)) in iproc_pll_clk_setup()
647 iclk = &pll->clks[0]; in iproc_pll_clk_setup()
670 pll->clk_data.clks[0] = clk; in iproc_pll_clk_setup()
684 iclk = &pll->clks[i]; in iproc_pll_clk_setup()
700 pll->clk_data.clks[i] = clk; in iproc_pll_clk_setup()
711 clk_unregister(pll->clk_data.clks[i]); in iproc_pll_clk_setup()
[all …]
Dclk-kona-setup.c761 kona_clk_teardown(ccu->clk_data.clks[i]); in ccu_clks_teardown()
762 kfree(ccu->clk_data.clks); in ccu_clks_teardown()
767 kfree(ccu->clk_data.clks); in kona_ccu_teardown()
768 ccu->clk_data.clks = NULL; in kona_ccu_teardown()
810 size = ccu->clk_data.clk_num * sizeof(*ccu->clk_data.clks); in kona_dt_ccu_setup()
811 ccu->clk_data.clks = kzalloc(size, GFP_KERNEL); in kona_dt_ccu_setup()
812 if (!ccu->clk_data.clks) { in kona_dt_ccu_setup()
856 ccu->clk_data.clks[i] = kona_clk_setup(&ccu->kona_clks[i]); in kona_dt_ccu_setup()
/linux-4.4.14/include/linux/
Dsh_clk.h141 int sh_clk_mstp_register(struct clk *clks, int nr);
149 static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr) in sh_clk_mstp32_register() argument
151 return sh_clk_mstp_register(clks, nr); in sh_clk_mstp32_register()
171 int sh_clk_div4_register(struct clk *clks, int nr,
173 int sh_clk_div4_enable_register(struct clk *clks, int nr,
175 int sh_clk_div4_reparent_register(struct clk *clks, int nr,
200 int sh_clk_div6_register(struct clk *clks, int nr);
201 int sh_clk_div6_reparent_register(struct clk *clks, int nr);
214 int sh_clk_fsidiv_register(struct clk *clks, int nr);
/linux-4.4.14/drivers/clk/mvebu/
Dcommon.c129 clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *), in mvebu_coreclk_setup()
131 if (WARN_ON(!clk_data.clks)) { in mvebu_coreclk_setup()
140 clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL, in mvebu_coreclk_setup()
142 WARN_ON(IS_ERR(clk_data.clks[0])); in mvebu_coreclk_setup()
153 clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL, in mvebu_coreclk_setup()
155 WARN_ON(IS_ERR(clk_data.clks[1])); in mvebu_coreclk_setup()
165 clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name, in mvebu_coreclk_setup()
167 WARN_ON(IS_ERR(clk_data.clks[2+n])); in mvebu_coreclk_setup()
176 clk_data.clks[2 + desc->num_ratios] = in mvebu_coreclk_setup()
179 WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios])); in mvebu_coreclk_setup()
Dclk-cpu.c44 static struct clk **clks; variable
193 clks = kzalloc(ncpus * sizeof(*clks), GFP_KERNEL); in of_cpu_clk_setup()
194 if (WARN_ON(!clks)) in of_cpu_clk_setup()
229 clks[cpu] = clk; in of_cpu_clk_setup()
232 clk_data.clks = clks; in of_cpu_clk_setup()
237 kfree(clks); in of_cpu_clk_setup()
Dclk-corediv.c241 struct clk **clks; in mvebu_corediv_clk_init() local
256 clks = kcalloc(clk_data.clk_num, sizeof(struct clk *), in mvebu_corediv_clk_init()
258 if (WARN_ON(!clks)) in mvebu_corediv_clk_init()
282 clks[i] = clk_register(NULL, &corediv[i].hw); in mvebu_corediv_clk_init()
283 WARN_ON(IS_ERR(clks[i])); in mvebu_corediv_clk_init()
286 clk_data.clks = clks; in mvebu_corediv_clk_init()
291 kfree(clks); in mvebu_corediv_clk_init()
/linux-4.4.14/drivers/clk/meson/
Dclkc.c26 static struct clk **clks; variable
32 clks = kcalloc(nr_clks, sizeof(*clks), GFP_KERNEL); in meson_clk_init()
33 if (!clks) in meson_clk_init()
36 clk_data.clks = clks; in meson_clk_init()
40 return clks; in meson_clk_init()
45 if (clks && id) in meson_clk_add_lookup()
46 clks[id] = clk; in meson_clk_add_lookup()
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Dlsi,axm5516-clks.txt5 - compatible : shall contain "lsi,axm5516-clks"
15 clks: clock-controller@2010020000 {
16 compatible = "lsi,axm5516-clks";
25 clocks = <&clks AXXIA_CLK_PER>;
Dimx35-clock.txt101 clks: ccm@53f80000 {
112 clocks = <&clks 9>, <&clks 8>, <&clks 43>;
Dimx1-clock.txt13 clks: ccm@0021b000 {
24 clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
Dimx27-clock.txt14 clks: ccm@10027000{
24 clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
25 <&clks IMX27_CLK_PER1_GATE>;
Dimx21-clock.txt14 clks: ccm@10027000{
24 clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
25 <&clks IMX21_CLK_PER1>;
Dimx5-clock.txt15 clks: ccm@53fd4000{
26 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
Dimx6q-clock.txt17 clks: ccm@020c4000 {
28 clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
Dux500.txt5 "stericsson,u8500-clks"
6 "stericsson,u8540-clks"
7 "stericsson,u9540-clks"
36 compatible = "stericsson,u8500-clks";
Dimx31-clock.txt77 clks: ccm@53f80000{
88 clocks = <&clks 10>, <&clks 30>;
Dimx25-clock.txt148 clks: ccm@53f80000 {
158 clocks = <&clks 79>, <&clks 50>;
Dclps711x-clock.txt14 clks: clks@80000000 {
Dimx23-clock.txt59 clks: clkctrl@80040000 {
69 clocks = <&clks 32>;
Dprima2-clock.txt60 clks: clock-controller@88000000 {
72 clocks = <&clks 17>;
Dvf610-clock.txt27 clks: ccm@4006b000 {
39 clocks = <&clks VF610_CLK_UART1>;
Dimx28-clock.txt82 clks: clkctrl@80040000 {
92 clocks = <&clks 45>;
Dcsr,atlas7-car.txt44 clocks = <&clks 95>;
/linux-4.4.14/Documentation/devicetree/bindings/power/
Dfsl,imx-gpc.txt29 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
30 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
31 <&clks IMX6QDL_CLK_GPU2D_CORE>,
32 <&clks IMX6QDL_CLK_GPU2D_AXI>,
33 <&clks IMX6QDL_CLK_OPENVG_AXI>,
34 <&clks IMX6QDL_CLK_VPU_AXI>;
/linux-4.4.14/drivers/clk/rockchip/
Dclk-rockchip.c57 clk_data->clks = kzalloc(qty * sizeof(struct clk *), GFP_KERNEL); in rk2928_gate_clk_init()
58 if (!clk_data->clks) { in rk2928_gate_clk_init()
81 clk_data->clks[i] = clk_register_gate(NULL, clk_name, in rk2928_gate_clk_init()
86 WARN_ON(IS_ERR(clk_data->clks[i])); in rk2928_gate_clk_init()
/linux-4.4.14/Documentation/devicetree/bindings/timer/
Dfsl,ftm-timer.txt26 clocks = <&clks VF610_CLK_FTM2>,
27 <&clks VF610_CLK_FTM3>,
28 <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
29 <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
Dfsl,imxgpt.txt16 clocks = <&clks 46>, <&clks 61>;
Dcirrus,clps711x-timer.txt21 clocks = <&clks 5>;
28 clocks = <&clks 6>;
/linux-4.4.14/drivers/clk/berlin/
Dbg2q.c49 static struct clk *clks[MAX_CLKS]; variable
345 clks[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase, in berlin2q_clock_setup()
354 clks[CLKID_GFX2DAXI + n] = clk_register_gate(NULL, gd->name, in berlin2q_clock_setup()
360 clks[CLKID_CPU] = in berlin2q_clock_setup()
364 clks[CLKID_TWD] = in berlin2q_clock_setup()
369 if (!IS_ERR(clks[n])) in berlin2q_clock_setup()
378 clk_data.clks = clks; in berlin2q_clock_setup()
Dbg2.c95 static struct clk *clks[MAX_CLKS]; variable
651 clks[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase, in berlin2_clock_setup()
660 clks[CLKID_GETH0 + n] = clk_register_gate(NULL, gd->name, in berlin2_clock_setup()
666 clks[CLKID_TWD] = in berlin2_clock_setup()
671 if (!IS_ERR(clks[n])) in berlin2_clock_setup()
680 clk_data.clks = clks; in berlin2_clock_setup()
/linux-4.4.14/drivers/gpu/drm/msm/dsi/pll/
Ddsi_pll.c87 struct clk **clks, u32 num_clks) in msm_dsi_pll_helper_unregister_clks() argument
91 if (!num_clks || !clks) in msm_dsi_pll_helper_unregister_clks()
95 clk_unregister(clks[--num_clks]); in msm_dsi_pll_helper_unregister_clks()
96 clks[num_clks] = NULL; in msm_dsi_pll_helper_unregister_clks()
Ddsi_pll_28nm.c87 struct clk *clks[NUM_DSI_CLOCKS_MAX]; member
507 pll_28nm->clks, pll_28nm->num_clks); in dsi_pll_28nm_destroy()
513 pll_28nm->clk_data.clks = NULL; in dsi_pll_28nm_destroy()
527 struct clk **clks = pll_28nm->clks; in pll_28nm_register() local
536 clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw); in pll_28nm_register()
540 clks[num++] = clk_register_divider(dev, clk_name, in pll_28nm_register()
548 clks[num++] = clk_register_fixed_factor(dev, clk_name, in pll_28nm_register()
554 clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] = in pll_28nm_register()
563 clks[num++] = clk_register_mux(dev, clk_name, in pll_28nm_register()
571 clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] = in pll_28nm_register()
[all …]
Ddsi_pll.h81 struct clk **clks, u32 num_clks);
/linux-4.4.14/drivers/clk/ti/
Dclk.c357 int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks) in ti_clk_register_legacy_clks() argument
364 while (clks->clk) { in ti_clk_register_legacy_clks()
365 clk = ti_clk_register_clk(clks->clk); in ti_clk_register_legacy_clks()
368 list_add(&clks->link, &retry_list); in ti_clk_register_legacy_clks()
371 clks->clk->name, PTR_ERR(clk)); in ti_clk_register_legacy_clks()
375 clks->lk.clk = clk; in ti_clk_register_legacy_clks()
376 clkdev_add(&clks->lk); in ti_clk_register_legacy_clks()
378 clks++; in ti_clk_register_legacy_clks()
Dfapll.c543 fd->outputs.clks = kzalloc(sizeof(struct clk *) * in ti_fapll_setup()
546 if (!fd->outputs.clks) in ti_fapll_setup()
594 fd->outputs.clks[0] = pll_clk; in ti_fapll_setup()
638 fd->outputs.clks[output_instance] = synth_clk; in ti_fapll_setup()
659 kfree(fd->outputs.clks); in ti_fapll_setup()
/linux-4.4.14/drivers/staging/media/davinci_vpfe/
Dvpfe_mc_capture.c205 clk_disable_unprepare(vpfe_dev->clks[i]); in vpfe_disable_clock()
206 clk_put(vpfe_dev->clks[i]); in vpfe_disable_clock()
208 kzfree(vpfe_dev->clks); in vpfe_disable_clock()
229 vpfe_dev->clks = kcalloc(vpfe_cfg->num_clocks, in vpfe_enable_clock()
231 if (vpfe_dev->clks == NULL) in vpfe_enable_clock()
242 vpfe_dev->clks[i] = in vpfe_enable_clock()
244 if (IS_ERR(vpfe_dev->clks[i])) { in vpfe_enable_clock()
251 if (clk_prepare_enable(vpfe_dev->clks[i])) { in vpfe_enable_clock()
265 if (!IS_ERR(vpfe_dev->clks[i])) { in vpfe_enable_clock()
266 clk_disable_unprepare(vpfe_dev->clks[i]); in vpfe_enable_clock()
[all …]
Dvpfe_mc_capture.h60 struct clk **clks; member
/linux-4.4.14/Documentation/devicetree/bindings/mtd/
Dlpc32xx-slc.txt11 - nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
12 - nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
33 nxp,wdr-clks = <14>;
37 nxp,rdr-clks = <14>;
Dvf610-nfc.txt12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
45 clocks = <&clks VF610_CLK_NFC>;
47 assigned-clocks = <&clks VF610_CLK_NFC>;
Dfsl-quadspi.txt29 clocks = <&clks VF610_CLK_QSPI0_EN>,
30 <&clks VF610_CLK_QSPI0>;
/linux-4.4.14/drivers/gpu/drm/exynos/
Dexynos_drm_mic.c100 struct clk *clks[NUM_CLKS]; member
323 clk_disable_unprepare(mic->clks[i]); in mic_post_disable()
341 ret = clk_prepare_enable(mic->clks[i]); in mic_pre_enable()
369 clk_disable_unprepare(mic->clks[i]); in mic_pre_enable()
386 clk_disable_unprepare(mic->clks[i]); in mic_destroy()
448 mic->clks[i] = of_clk_get_by_name(dev->of_node, clk_names[i]); in exynos_mic_probe()
449 if (IS_ERR(mic->clks[i])) { in exynos_mic_probe()
452 ret = PTR_ERR(mic->clks[i]); in exynos_mic_probe()
471 clk_put(mic->clks[i]); in exynos_mic_remove()
Dexynos5433_drm_decon.c60 struct clk *clks[ARRAY_SIZE(decon_clks_name)]; member
389 ret = clk_prepare_enable(ctx->clks[i]); in decon_enable()
405 clk_disable_unprepare(ctx->clks[i]); in decon_enable()
429 clk_disable_unprepare(ctx->clks[i]); in decon_disable()
459 ret = clk_prepare_enable(ctx->clks[i]); in decon_clear_channels()
475 clk_disable_unprepare(ctx->clks[i]); in decon_clear_channels()
628 ctx->clks[i] = clk; in exynos5433_decon_probe()
Dexynos_drm_dsi.c271 struct clk **clks; member
1473 ret = clk_prepare_enable(dsi->clks[i]); in exynos_dsi_poweron()
1488 clk_disable_unprepare(dsi->clks[i]); in exynos_dsi_poweron()
1514 clk_disable_unprepare(dsi->clks[i]); in exynos_dsi_poweroff()
1906 dsi->clks = devm_kzalloc(dev, in exynos_dsi_probe()
1907 sizeof(*dsi->clks) * dsi->driver_data->num_clks, in exynos_dsi_probe()
1909 if (!dsi->clks) in exynos_dsi_probe()
1913 dsi->clks[i] = devm_clk_get(dev, clk_names[i]); in exynos_dsi_probe()
1914 if (IS_ERR(dsi->clks[i])) { in exynos_dsi_probe()
1923 return PTR_ERR(dsi->clks[i]); in exynos_dsi_probe()
/linux-4.4.14/drivers/soc/rockchip/
Dpm_domains.c52 struct clk *clks[]; member
143 clk_enable(pd->clks[i]); in rockchip_pd_power()
162 clk_disable(pd->clks[i]); in rockchip_pd_power()
255 sizeof(*pd) + clk_cnt * sizeof(pd->clks[0]), in rockchip_pm_add_one_domain()
282 pd->clks[pd->num_clks++] = clk; in rockchip_pm_add_one_domain()
309 clk_unprepare(pd->clks[i]); in rockchip_pm_add_one_domain()
310 clk_put(pd->clks[i]); in rockchip_pm_add_one_domain()
320 clk_unprepare(pd->clks[i]); in rockchip_pm_remove_one_domain()
321 clk_put(pd->clks[i]); in rockchip_pm_remove_one_domain()
/linux-4.4.14/Documentation/devicetree/bindings/pwm/
Dpwm-fsl-ftm.txt45 clocks = <&clks VF610_CLK_FTM0>,
46 <&clks VF610_CLK_FTM0_EXT_SEL>,
47 <&clks VF610_CLK_FTM0_FIX_SEL>,
48 <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
Dimx-pwm.txt23 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
24 <&clks IMX5_CLK_PWM1_HF_GATE>;
Dcirrus,clps711x-pwm.txt14 clocks = <&clks 8>;
/linux-4.4.14/Documentation/devicetree/bindings/pci/
Dfsl,imx6q-pcie.txt38 clocks = <&clks 144>, <&clks 206>, <&clks 189>;
/linux-4.4.14/Documentation/devicetree/bindings/ata/
Dimx-sata.txt32 clocks = <&clks IMX6QDL_CLK_SATA>,
33 <&clks IMX6QDL_CLK_SATA_REF_100M>,
34 <&clks IMX6QDL_CLK_AHB>;
Dimx-pata.txt15 clocks = <&clks 161>;
/linux-4.4.14/Documentation/devicetree/bindings/display/imx/
Dldb.txt83 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
84 <&clks IMX5_CLK_LDB_DI1_SEL>,
85 <&clks IMX5_CLK_IPU_DI0_SEL>,
86 <&clks IMX5_CLK_IPU_DI1_SEL>,
87 <&clks IMX5_CLK_LDB_DI0_GATE>,
88 <&clks IMX5_CLK_LDB_DI1_GATE>;
Dhdmi.txt39 clocks = <&clks 123>, <&clks 124>;
/linux-4.4.14/drivers/ata/
Dlibahci_platform.c106 for (c = 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++) { in ahci_platform_enable_clks()
107 rc = clk_prepare_enable(hpriv->clks[c]); in ahci_platform_enable_clks()
115 clk_disable_unprepare(hpriv->clks[c]); in ahci_platform_enable_clks()
132 if (hpriv->clks[c]) in ahci_platform_disable_clks()
133 clk_disable_unprepare(hpriv->clks[c]); in ahci_platform_disable_clks()
264 for (c = 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++) in ahci_platform_put_resources()
265 clk_put(hpriv->clks[c]); in ahci_platform_put_resources()
392 hpriv->clks[i] = clk; in ahci_platform_get_resources()
/linux-4.4.14/drivers/clk/st/
Dclkgen-mux.c414 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *), in st_of_clkgena_divmux_setup()
417 if (!clk_data->clks) in st_of_clkgena_divmux_setup()
440 clk_data->clks[i] = clk; in st_of_clkgena_divmux_setup()
448 kfree(clk_data->clks); in st_of_clkgena_divmux_setup()
736 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *), in st_of_clkgen_vcc_setup()
739 if (!clk_data->clks) in st_of_clkgen_vcc_setup()
810 clk_data->clks[i] = clk; in st_of_clkgen_vcc_setup()
822 if (!clk_data->clks[i]) in st_of_clkgen_vcc_setup()
825 composite = container_of(__clk_get_hw(clk_data->clks[i]), in st_of_clkgen_vcc_setup()
832 kfree(clk_data->clks); in st_of_clkgen_vcc_setup()
Dclkgen-pll.c936 clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), in clkgena_c65_pll_setup()
939 if (!clk_data->clks) in clkgena_c65_pll_setup()
949 clk_data->clks[0] = clkgen_pll_register(parent_name, in clkgena_c65_pll_setup()
953 if (IS_ERR(clk_data->clks[0])) in clkgena_c65_pll_setup()
964 clk_data->clks[1] = clkgen_c65_lsdiv_register(__clk_get_name in clkgena_c65_pll_setup()
965 (clk_data->clks[0]), in clkgena_c65_pll_setup()
968 if (IS_ERR(clk_data->clks[1])) in clkgena_c65_pll_setup()
978 clk_data->clks[2] = clkgen_pll_register(parent_name, in clkgena_c65_pll_setup()
982 if (IS_ERR(clk_data->clks[2])) in clkgena_c65_pll_setup()
989 kfree(clk_data->clks); in clkgena_c65_pll_setup()
[all …]
Dclk-flexgen.c297 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *), in st_of_flexgen_setup()
299 if (!clk_data->clks) in st_of_flexgen_setup()
329 clk_data->clks[i] = clk; in st_of_flexgen_setup()
339 kfree(clk_data->clks); in st_of_flexgen_setup()
/linux-4.4.14/drivers/clk/ingenic/
Dcgu.c527 cgu->clocks.clks[idx] = clk; in ingenic_register_clock()
565 parent = cgu->clocks.clks[clk_info->parents[i]]; in ingenic_register_clock()
576 parent = cgu->clocks.clks[clk_info->parents[0]]; in ingenic_register_clock()
638 cgu->clocks.clks[idx] = clk; in ingenic_register_clock()
680 cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *), in ingenic_cgu_register_clocks()
682 if (!cgu->clocks.clks) { in ingenic_cgu_register_clocks()
702 if (!cgu->clocks.clks[i]) in ingenic_cgu_register_clocks()
705 clk_put(cgu->clocks.clks[i]); in ingenic_cgu_register_clocks()
707 clk_unregister(cgu->clocks.clks[i]); in ingenic_cgu_register_clocks()
709 kfree(cgu->clocks.clks); in ingenic_cgu_register_clocks()
/linux-4.4.14/arch/sh/kernel/cpu/sh4a/
Dclock-shx3.c45 static struct clk *clks[] = { variable
139 for (i = 0; i < ARRAY_SIZE(clks); i++) in arch_clk_init()
140 ret |= clk_register(clks[i]); in arch_clk_init()
Dclock-sh7757.c46 static struct clk *clks[] = { variable
142 for (i = 0; i < ARRAY_SIZE(clks); i++) in arch_clk_init()
143 ret |= clk_register(clks[i]); in arch_clk_init()
Dclock-sh7785.c49 static struct clk *clks[] = { variable
165 for (i = 0; i < ARRAY_SIZE(clks); i++) in arch_clk_init()
166 ret |= clk_register(clks[i]); in arch_clk_init()
Dclock-sh7786.c51 static struct clk *clks[] = { variable
180 for (i = 0; i < ARRAY_SIZE(clks); i++) in arch_clk_init()
181 ret |= clk_register(clks[i]); in arch_clk_init()
/linux-4.4.14/Documentation/devicetree/bindings/rtc/
Drtc-mxc.txt23 clocks = <&clks IMX27_CLK_CKIL>,
24 <&clks IMX27_CLK_RTC_IPG_GATE>;
/linux-4.4.14/Documentation/devicetree/bindings/media/
Dcoda.txt27 clocks = <&clks 63>, <&clks 63>;
/linux-4.4.14/drivers/clk/samsung/
Dclk.c78 ctx->clk_data.clks = clk_table; in samsung_clk_init()
99 if (ctx->clk_data.clks && id) in samsung_clk_add_lookup()
100 ctx->clk_data.clks[id] = clk; in samsung_clk_add_lookup()
111 if (!ctx->clk_data.clks) { in samsung_clk_register_alias()
123 clk = ctx->clk_data.clks[list->id]; in samsung_clk_register_alias()
/linux-4.4.14/Documentation/devicetree/bindings/dma/
Dfsl-edma.txt53 clocks = <&clks VF610_CLK_DMAMUX0>,
54 <&clks VF610_CLK_DMAMUX1>;
71 clocks = <&clks VF610_CLK_SAI2>;
Dsirfsoc-dma.txt21 clocks = <&clks 24>;
/linux-4.4.14/Documentation/devicetree/bindings/input/touchscreen/
Dimx6ul_tsc.txt27 clocks = <&clks IMX6UL_CLK_IPG>,
28 <&clks IMX6UL_CLK_ADC2>;
/linux-4.4.14/Documentation/devicetree/bindings/display/bridge/
Ddw_hdmi.txt31 clocks = <&clks 123>, <&clks 124>;
/linux-4.4.14/drivers/misc/sgi-gru/
Dgruhandles.c42 static void update_mcs_stats(enum mcs_op op, unsigned long clks) in update_mcs_stats() argument
46 nsec = CLKS2NSEC(clks); in update_mcs_stats()
/linux-4.4.14/Documentation/devicetree/bindings/net/can/
Dm_can.txt55 clocks = <&clks IMX6SX_CLK_CANFD>,
56 <&clks IMX6SX_CLK_CANFD>;
/linux-4.4.14/Documentation/devicetree/bindings/nvmem/
Dvf610-ocotp.txt18 clocks = <&clks VF610_CLK_OCOTP>;
Dmxs-ocotp.txt23 clocks = <&clks 25>;
Dimx-ocotp.txt19 clocks = <&clks IMX6QDL_CLK_IIM>;
/linux-4.4.14/Documentation/devicetree/bindings/w1/
Dfsl-imx-owire.txt17 clocks = <&clks 159>;
/linux-4.4.14/drivers/mmc/host/
Dsdhci-s3c.c453 int ret, irq, ptr, clks; in sdhci_s3c_probe() local
507 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { in sdhci_s3c_probe()
515 clks++; in sdhci_s3c_probe()
522 if (clks == 0) { in sdhci_s3c_probe()
/linux-4.4.14/Documentation/devicetree/bindings/display/
Dmarvell,pxa2xx-lcdc.txt25 clocks = <&clks CLK_LCD>;
Dcirrus,clps711x-fb.txt23 clocks = <&clks 2>;
/linux-4.4.14/Documentation/devicetree/bindings/serial/
Dcirrus,clps711x-uart.txt26 clocks = <&clks 11>;
Dfsl-lpuart.txt26 clocks = <&clks VF610_CLK_UART0>;
Dsirf-uart.txt24 clocks = <&clks 13>;
/linux-4.4.14/Documentation/devicetree/bindings/thermal/
Dimx-thermal.txt23 clocks = <&clks 172>;
/linux-4.4.14/Documentation/devicetree/bindings/reset/
Dsirf,rstc.txt40 clocks = <&clks 35>;
/linux-4.4.14/drivers/media/platform/exynos4-is/
Dmedia-dev.c1214 clk_unregister(cp->clks[i]); in fimc_md_unregister_clk_provider()
1243 cp->clks[i] = clk_register(NULL, &camclk->hw); in fimc_md_register_clk_provider()
1244 if (IS_ERR(cp->clks[i])) { in fimc_md_register_clk_provider()
1246 init.name, PTR_ERR(cp->clks[i])); in fimc_md_register_clk_provider()
1247 ret = PTR_ERR(cp->clks[i]); in fimc_md_register_clk_provider()
1258 cp->clk_data.clks = cp->clks; in fimc_md_register_clk_provider()
/linux-4.4.14/Documentation/devicetree/bindings/spi/
Dspi-sirf.txt40 clocks = <&clks 19>;
/linux-4.4.14/Documentation/devicetree/bindings/mfd/
Dsun6i-prcm.txt4 (like clks and reset controllers).
/linux-4.4.14/Documentation/devicetree/bindings/arm/ux500/
Dboards.txt76 compatible = "stericsson,u8500-clks";

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