Lines Matching refs:clks

73 			clocks = <&clks IMX27_CLK_CPU_DIV>;
96 				clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
97 					 <&clks IMX27_CLK_DMA_AHB_GATE>;
107 				clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
114 				clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
115 					 <&clks IMX27_CLK_PER1_GATE>;
123 				clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
124 					 <&clks IMX27_CLK_PER1_GATE>;
132 				clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
133 					 <&clks IMX27_CLK_PER1_GATE>;
142 				clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
143 					 <&clks IMX27_CLK_PER1_GATE>;
151 				clocks = <&clks IMX27_CLK_CKIL>,
152 					 <&clks IMX27_CLK_RTC_IPG_GATE>;
160 				clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
167 				clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
175 				clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
176 					 <&clks IMX27_CLK_PER1_GATE>;
185 				clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
186 					 <&clks IMX27_CLK_PER1_GATE>;
195 				clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
196 					 <&clks IMX27_CLK_PER1_GATE>;
205 				clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
206 					 <&clks IMX27_CLK_PER1_GATE>;
217 				clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
218 					 <&clks IMX27_CLK_PER2_GATE>;
229 				clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
230 					 <&clks IMX27_CLK_PER2_GATE>;
240 				clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
252 				clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
265 				clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
273 				clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
274 					 <&clks IMX27_CLK_PER2_GATE>;
285 				clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
286 					 <&clks IMX27_CLK_PER2_GATE>;
303 					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
314 					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
325 					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
336 					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
347 					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
358 					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
370 				clocks = <&clks IMX27_CLK_DUMMY>;
381 				clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
382 					 <&clks IMX27_CLK_PER2_GATE>;
391 				clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
392 					 <&clks IMX27_CLK_PER1_GATE>;
400 				clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
401 					 <&clks IMX27_CLK_PER1_GATE>;
409 				clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
410 					 <&clks IMX27_CLK_PER1_GATE>;
419 				clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
420 					 <&clks IMX27_CLK_PER1_GATE>;
431 				clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
439 				clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
440 					 <&clks IMX27_CLK_PER2_GATE>;
451 				clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
452 					 <&clks IMX27_CLK_PER1_GATE>;
468 				clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
469 					 <&clks IMX27_CLK_LCDC_AHB_GATE>,
470 					 <&clks IMX27_CLK_PER3_GATE>;
479 				clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
480 					 <&clks IMX27_CLK_VPU_AHB_GATE>;
489 				clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
490 					<&clks IMX27_CLK_USB_AHB_GATE>,
491 					<&clks IMX27_CLK_USB_DIV>;
501 				clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
502 					<&clks IMX27_CLK_USB_AHB_GATE>,
503 					<&clks IMX27_CLK_USB_DIV>;
514 				clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
515 					<&clks IMX27_CLK_USB_AHB_GATE>,
516 					<&clks IMX27_CLK_USB_DIV>;
533 				clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
534 					 <&clks IMX27_CLK_SAHARA_AHB_GATE>;
538 			clks: ccm@10027000{  label
548 				clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
555 				clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
556 					 <&clks IMX27_CLK_FEC_AHB_GATE>;
568 			clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
577 			clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;