940 static struct clk **clks;  variable
952 	clks[TEGRA114_CLK_CLK_32K] = clk;  in tegra114_fixed_clk_init()
957 	clks[TEGRA114_CLK_CLK_M_DIV2] = clk;  in tegra114_fixed_clk_init()
962 	clks[TEGRA114_CLK_CLK_M_DIV4] = clk;  in tegra114_fixed_clk_init()
1057 	clks[TEGRA114_CLK_PLL_C] = clk;  in tegra114_pll_init()
1066 	clks[TEGRA114_CLK_PLL_C_OUT1] = clk;  in tegra114_pll_init()
1071 	clks[TEGRA114_CLK_PLL_C2] = clk;  in tegra114_pll_init()
1076 	clks[TEGRA114_CLK_PLL_C3] = clk;  in tegra114_pll_init()
1082 	clks[TEGRA114_CLK_PLL_M] = clk;  in tegra114_pll_init()
1091 	clks[TEGRA114_CLK_PLL_M_OUT1] = clk;  in tegra114_pll_init()
1104 	clks[TEGRA114_CLK_PLL_U] = clk;  in tegra114_pll_init()
1112 	clks[TEGRA114_CLK_PLL_U_480M] = clk;  in tegra114_pll_init()
1117 	clks[TEGRA114_CLK_PLL_U_60M] = clk;  in tegra114_pll_init()
1122 	clks[TEGRA114_CLK_PLL_U_48M] = clk;  in tegra114_pll_init()
1127 	clks[TEGRA114_CLK_PLL_U_12M] = clk;  in tegra114_pll_init()
1132 	clks[TEGRA114_CLK_PLL_D] = clk;  in tegra114_pll_init()
1137 	clks[TEGRA114_CLK_PLL_D_OUT0] = clk;  in tegra114_pll_init()
1142 	clks[TEGRA114_CLK_PLL_D2] = clk;  in tegra114_pll_init()
1147 	clks[TEGRA114_CLK_PLL_D2_OUT0] = clk;  in tegra114_pll_init()
1152 	clks[TEGRA114_CLK_PLL_RE_VCO] = clk;  in tegra114_pll_init()
1157 	clks[TEGRA114_CLK_PLL_RE_OUT] = clk;  in tegra114_pll_init()
1162 	clks[TEGRA114_CLK_PLL_E_OUT0] = clk;  in tegra114_pll_init()
1181 	clks[TEGRA114_CLK_XUSB_SS_DIV2] = clk;  in tegra114_periph_clk_init()
1188 	clks[TEGRA114_CLK_DSIA_MUX] = clk;  in tegra114_periph_clk_init()
1195 	clks[TEGRA114_CLK_DSIB_MUX] = clk;  in tegra114_periph_clk_init()
1199 	clks[TEGRA114_CLK_DSIA] = clk;  in tegra114_periph_clk_init()
1203 	clks[TEGRA114_CLK_DSIB] = clk;  in tegra114_periph_clk_init()
1214 	clks[TEGRA114_CLK_MC] = clk;  in tegra114_periph_clk_init()
1221 		clks[data->clk_id] = clk;  in tegra114_periph_clk_init()
1324 	tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);  in tegra114_clock_apply_init_table()
1475 	clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,  in tegra114_clock_init()
1477 	if (!clks)  in tegra114_clock_init()