208 static struct clk **clks;  variable
929 	clks[TEGRA30_CLK_PLL_C] = clk;  in tegra30_pll_init()
938 	clks[TEGRA30_CLK_PLL_C_OUT1] = clk;  in tegra30_pll_init()
944 	clks[TEGRA30_CLK_PLL_M] = clk;  in tegra30_pll_init()
953 	clks[TEGRA30_CLK_PLL_M_OUT1] = clk;  in tegra30_pll_init()
958 	clks[TEGRA30_CLK_PLL_X] = clk;  in tegra30_pll_init()
963 	clks[TEGRA30_CLK_PLL_X_OUT0] = clk;  in tegra30_pll_init()
968 	clks[TEGRA30_CLK_PLL_U] = clk;  in tegra30_pll_init()
975 	clks[TEGRA30_CLK_PLL_D] = clk;  in tegra30_pll_init()
980 	clks[TEGRA30_CLK_PLL_D_OUT0] = clk;  in tegra30_pll_init()
985 	clks[TEGRA30_CLK_PLL_D2] = clk;  in tegra30_pll_init()
990 	clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;  in tegra30_pll_init()
999 	clks[TEGRA30_CLK_PLL_E] = clk;  in tegra30_pll_init()
1050 	clks[TEGRA30_CLK_CCLK_G] = clk;  in tegra30_super_clk_init()
1086 	clks[TEGRA30_CLK_CCLK_LP] = clk;  in tegra30_super_clk_init()
1094 	clks[TEGRA30_CLK_SCLK] = clk;  in tegra30_super_clk_init()
1099 	clks[TEGRA30_CLK_TWD] = clk;  in tegra30_super_clk_init()
1143 	clks[TEGRA30_CLK_DSIA] = clk;  in tegra30_periph_clk_init()
1148 	clks[TEGRA30_CLK_PCIE] = clk;  in tegra30_periph_clk_init()
1153 	clks[TEGRA30_CLK_AFI] = clk;  in tegra30_periph_clk_init()
1163 	clks[TEGRA30_CLK_EMC] = clk;  in tegra30_periph_clk_init()
1167 	clks[TEGRA30_CLK_MC] = clk;  in tegra30_periph_clk_init()
1172 	clks[TEGRA30_CLK_CML0] = clk;  in tegra30_periph_clk_init()
1177 	clks[TEGRA30_CLK_CML1] = clk;  in tegra30_periph_clk_init()
1184 		clks[data->clk_id] = clk;  in tegra30_periph_clk_init()
1193 		clks[data->clk_id] = clk;  in tegra30_periph_clk_init()
1380 	tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);  in tegra30_clock_apply_init_table()
1434 	clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,  in tegra30_clock_init()
1436 	if (!clks)  in tegra30_clock_init()
1454 	tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);  in tegra30_clock_init()