1/*
2 * rcar_gen2 Core CPG Clocks
3 *
4 * Copyright (C) 2013  Ideas On Board SPRL
5 *
6 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 */
12
13#include <linux/clk-provider.h>
14#include <linux/clk/shmobile.h>
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <linux/math64.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22
23struct rcar_gen2_cpg {
24	struct clk_onecell_data data;
25	spinlock_t lock;
26	void __iomem *reg;
27};
28
29#define CPG_FRQCRB			0x00000004
30#define CPG_FRQCRB_KICK			BIT(31)
31#define CPG_SDCKCR			0x00000074
32#define CPG_PLL0CR			0x000000d8
33#define CPG_FRQCRC			0x000000e0
34#define CPG_FRQCRC_ZFC_MASK		(0x1f << 8)
35#define CPG_FRQCRC_ZFC_SHIFT		8
36#define CPG_ADSPCKCR			0x0000025c
37#define CPG_RCANCKCR			0x00000270
38
39/* -----------------------------------------------------------------------------
40 * Z Clock
41 *
42 * Traits of this clock:
43 * prepare - clk_prepare only ensures that parents are prepared
44 * enable - clk_enable only ensures that parents are enabled
45 * rate - rate is adjustable.  clk->rate = parent->rate * mult / 32
46 * parent - fixed parent.  No clk_set_parent support
47 */
48
49struct cpg_z_clk {
50	struct clk_hw hw;
51	void __iomem *reg;
52	void __iomem *kick_reg;
53};
54
55#define to_z_clk(_hw)	container_of(_hw, struct cpg_z_clk, hw)
56
57static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
58					   unsigned long parent_rate)
59{
60	struct cpg_z_clk *zclk = to_z_clk(hw);
61	unsigned int mult;
62	unsigned int val;
63
64	val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK)
65	    >> CPG_FRQCRC_ZFC_SHIFT;
66	mult = 32 - val;
67
68	return div_u64((u64)parent_rate * mult, 32);
69}
70
71static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
72				 unsigned long *parent_rate)
73{
74	unsigned long prate  = *parent_rate;
75	unsigned int mult;
76
77	if (!prate)
78		prate = 1;
79
80	mult = div_u64((u64)rate * 32, prate);
81	mult = clamp(mult, 1U, 32U);
82
83	return *parent_rate / 32 * mult;
84}
85
86static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
87			      unsigned long parent_rate)
88{
89	struct cpg_z_clk *zclk = to_z_clk(hw);
90	unsigned int mult;
91	u32 val, kick;
92	unsigned int i;
93
94	mult = div_u64((u64)rate * 32, parent_rate);
95	mult = clamp(mult, 1U, 32U);
96
97	if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
98		return -EBUSY;
99
100	val = clk_readl(zclk->reg);
101	val &= ~CPG_FRQCRC_ZFC_MASK;
102	val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
103	clk_writel(val, zclk->reg);
104
105	/*
106	 * Set KICK bit in FRQCRB to update hardware setting and wait for
107	 * clock change completion.
108	 */
109	kick = clk_readl(zclk->kick_reg);
110	kick |= CPG_FRQCRB_KICK;
111	clk_writel(kick, zclk->kick_reg);
112
113	/*
114	 * Note: There is no HW information about the worst case latency.
115	 *
116	 * Using experimental measurements, it seems that no more than
117	 * ~10 iterations are needed, independently of the CPU rate.
118	 * Since this value might be dependant of external xtal rate, pll1
119	 * rate or even the other emulation clocks rate, use 1000 as a
120	 * "super" safe value.
121	 */
122	for (i = 1000; i; i--) {
123		if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
124			return 0;
125
126		cpu_relax();
127	}
128
129	return -ETIMEDOUT;
130}
131
132static const struct clk_ops cpg_z_clk_ops = {
133	.recalc_rate = cpg_z_clk_recalc_rate,
134	.round_rate = cpg_z_clk_round_rate,
135	.set_rate = cpg_z_clk_set_rate,
136};
137
138static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg)
139{
140	static const char *parent_name = "pll0";
141	struct clk_init_data init;
142	struct cpg_z_clk *zclk;
143	struct clk *clk;
144
145	zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
146	if (!zclk)
147		return ERR_PTR(-ENOMEM);
148
149	init.name = "z";
150	init.ops = &cpg_z_clk_ops;
151	init.flags = 0;
152	init.parent_names = &parent_name;
153	init.num_parents = 1;
154
155	zclk->reg = cpg->reg + CPG_FRQCRC;
156	zclk->kick_reg = cpg->reg + CPG_FRQCRB;
157	zclk->hw.init = &init;
158
159	clk = clk_register(NULL, &zclk->hw);
160	if (IS_ERR(clk))
161		kfree(zclk);
162
163	return clk;
164}
165
166static struct clk * __init cpg_rcan_clk_register(struct rcar_gen2_cpg *cpg,
167						 struct device_node *np)
168{
169	const char *parent_name = of_clk_get_parent_name(np, 1);
170	struct clk_fixed_factor *fixed;
171	struct clk_gate *gate;
172	struct clk *clk;
173
174	fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
175	if (!fixed)
176		return ERR_PTR(-ENOMEM);
177
178	fixed->mult = 1;
179	fixed->div = 6;
180
181	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
182	if (!gate) {
183		kfree(fixed);
184		return ERR_PTR(-ENOMEM);
185	}
186
187	gate->reg = cpg->reg + CPG_RCANCKCR;
188	gate->bit_idx = 8;
189	gate->flags = CLK_GATE_SET_TO_DISABLE;
190	gate->lock = &cpg->lock;
191
192	clk = clk_register_composite(NULL, "rcan", &parent_name, 1, NULL, NULL,
193				     &fixed->hw, &clk_fixed_factor_ops,
194				     &gate->hw, &clk_gate_ops, 0);
195	if (IS_ERR(clk)) {
196		kfree(gate);
197		kfree(fixed);
198	}
199
200	return clk;
201}
202
203/* ADSP divisors */
204static const struct clk_div_table cpg_adsp_div_table[] = {
205	{  1,  3 }, {  2,  4 }, {  3,  6 }, {  4,  8 },
206	{  5, 12 }, {  6, 16 }, {  7, 18 }, {  8, 24 },
207	{ 10, 36 }, { 11, 48 }, {  0,  0 },
208};
209
210static struct clk * __init cpg_adsp_clk_register(struct rcar_gen2_cpg *cpg)
211{
212	const char *parent_name = "pll1";
213	struct clk_divider *div;
214	struct clk_gate *gate;
215	struct clk *clk;
216
217	div = kzalloc(sizeof(*div), GFP_KERNEL);
218	if (!div)
219		return ERR_PTR(-ENOMEM);
220
221	div->reg = cpg->reg + CPG_ADSPCKCR;
222	div->width = 4;
223	div->table = cpg_adsp_div_table;
224	div->lock = &cpg->lock;
225
226	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
227	if (!gate) {
228		kfree(div);
229		return ERR_PTR(-ENOMEM);
230	}
231
232	gate->reg = cpg->reg + CPG_ADSPCKCR;
233	gate->bit_idx = 8;
234	gate->flags = CLK_GATE_SET_TO_DISABLE;
235	gate->lock = &cpg->lock;
236
237	clk = clk_register_composite(NULL, "adsp", &parent_name, 1, NULL, NULL,
238				     &div->hw, &clk_divider_ops,
239				     &gate->hw, &clk_gate_ops, 0);
240	if (IS_ERR(clk)) {
241		kfree(gate);
242		kfree(div);
243	}
244
245	return clk;
246}
247
248/* -----------------------------------------------------------------------------
249 * CPG Clock Data
250 */
251
252/*
253 *   MD		EXTAL		PLL0	PLL1	PLL3
254 * 14 13 19	(MHz)		*1	*1
255 *---------------------------------------------------
256 * 0  0  0	15 x 1		x172/2	x208/2	x106
257 * 0  0  1	15 x 1		x172/2	x208/2	x88
258 * 0  1  0	20 x 1		x130/2	x156/2	x80
259 * 0  1  1	20 x 1		x130/2	x156/2	x66
260 * 1  0  0	26 / 2		x200/2	x240/2	x122
261 * 1  0  1	26 / 2		x200/2	x240/2	x102
262 * 1  1  0	30 / 2		x172/2	x208/2	x106
263 * 1  1  1	30 / 2		x172/2	x208/2	x88
264 *
265 * *1 :	Table 7.6 indicates VCO ouput (PLLx = VCO/2)
266 */
267#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
268					 (((md) & BIT(13)) >> 12) | \
269					 (((md) & BIT(19)) >> 19))
270struct cpg_pll_config {
271	unsigned int extal_div;
272	unsigned int pll1_mult;
273	unsigned int pll3_mult;
274};
275
276static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
277	{ 1, 208, 106 }, { 1, 208,  88 }, { 1, 156,  80 }, { 1, 156,  66 },
278	{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208,  88 },
279};
280
281/* SDHI divisors */
282static const struct clk_div_table cpg_sdh_div_table[] = {
283	{  0,  2 }, {  1,  3 }, {  2,  4 }, {  3,  6 },
284	{  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
285	{  8, 24 }, { 10, 36 }, { 11, 48 }, {  0,  0 },
286};
287
288static const struct clk_div_table cpg_sd01_div_table[] = {
289	{  4,  8 },
290	{  5, 12 }, {  6, 16 }, {  7, 18 }, {  8, 24 },
291	{ 10, 36 }, { 11, 48 }, { 12, 10 }, {  0,  0 },
292};
293
294/* -----------------------------------------------------------------------------
295 * Initialization
296 */
297
298static u32 cpg_mode __initdata;
299
300static struct clk * __init
301rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
302			     const struct cpg_pll_config *config,
303			     const char *name)
304{
305	const struct clk_div_table *table = NULL;
306	const char *parent_name;
307	unsigned int shift;
308	unsigned int mult = 1;
309	unsigned int div = 1;
310
311	if (!strcmp(name, "main")) {
312		parent_name = of_clk_get_parent_name(np, 0);
313		div = config->extal_div;
314	} else if (!strcmp(name, "pll0")) {
315		/* PLL0 is a configurable multiplier clock. Register it as a
316		 * fixed factor clock for now as there's no generic multiplier
317		 * clock implementation and we currently have no need to change
318		 * the multiplier value.
319		 */
320		u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
321		parent_name = "main";
322		mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
323	} else if (!strcmp(name, "pll1")) {
324		parent_name = "main";
325		mult = config->pll1_mult / 2;
326	} else if (!strcmp(name, "pll3")) {
327		parent_name = "main";
328		mult = config->pll3_mult;
329	} else if (!strcmp(name, "lb")) {
330		parent_name = "pll1";
331		div = cpg_mode & BIT(18) ? 36 : 24;
332	} else if (!strcmp(name, "qspi")) {
333		parent_name = "pll1_div2";
334		div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2)
335		    ? 8 : 10;
336	} else if (!strcmp(name, "sdh")) {
337		parent_name = "pll1";
338		table = cpg_sdh_div_table;
339		shift = 8;
340	} else if (!strcmp(name, "sd0")) {
341		parent_name = "pll1";
342		table = cpg_sd01_div_table;
343		shift = 4;
344	} else if (!strcmp(name, "sd1")) {
345		parent_name = "pll1";
346		table = cpg_sd01_div_table;
347		shift = 0;
348	} else if (!strcmp(name, "z")) {
349		return cpg_z_clk_register(cpg);
350	} else if (!strcmp(name, "rcan")) {
351		return cpg_rcan_clk_register(cpg, np);
352	} else if (!strcmp(name, "adsp")) {
353		return cpg_adsp_clk_register(cpg);
354	} else {
355		return ERR_PTR(-EINVAL);
356	}
357
358	if (!table)
359		return clk_register_fixed_factor(NULL, name, parent_name, 0,
360						 mult, div);
361	else
362		return clk_register_divider_table(NULL, name, parent_name, 0,
363						 cpg->reg + CPG_SDCKCR, shift,
364						 4, 0, table, &cpg->lock);
365}
366
367static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
368{
369	const struct cpg_pll_config *config;
370	struct rcar_gen2_cpg *cpg;
371	struct clk **clks;
372	unsigned int i;
373	int num_clks;
374
375	num_clks = of_property_count_strings(np, "clock-output-names");
376	if (num_clks < 0) {
377		pr_err("%s: failed to count clocks\n", __func__);
378		return;
379	}
380
381	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
382	clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL);
383	if (cpg == NULL || clks == NULL) {
384		/* We're leaking memory on purpose, there's no point in cleaning
385		 * up as the system won't boot anyway.
386		 */
387		pr_err("%s: failed to allocate cpg\n", __func__);
388		return;
389	}
390
391	spin_lock_init(&cpg->lock);
392
393	cpg->data.clks = clks;
394	cpg->data.clk_num = num_clks;
395
396	cpg->reg = of_iomap(np, 0);
397	if (WARN_ON(cpg->reg == NULL))
398		return;
399
400	config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
401
402	for (i = 0; i < num_clks; ++i) {
403		const char *name;
404		struct clk *clk;
405
406		of_property_read_string_index(np, "clock-output-names", i,
407					      &name);
408
409		clk = rcar_gen2_cpg_register_clock(np, cpg, config, name);
410		if (IS_ERR(clk))
411			pr_err("%s: failed to register %s %s clock (%ld)\n",
412			       __func__, np->name, name, PTR_ERR(clk));
413		else
414			cpg->data.clks[i] = clk;
415	}
416
417	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
418
419	cpg_mstp_add_clk_domain(np);
420}
421CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
422	       rcar_gen2_cpg_clocks_init);
423
424void __init rcar_gen2_clocks_init(u32 mode)
425{
426	cpg_mode = mode;
427
428	of_clk_init(NULL);
429}
430