1/*
2 * Copyright (C) 2014 Free Electrons
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
6 *
7 * Allwinner A31 APB0 clock gates driver
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17
18#define SUN6I_APB0_GATES_MAX_SIZE	32
19
20struct gates_data {
21	DECLARE_BITMAP(mask, SUN6I_APB0_GATES_MAX_SIZE);
22};
23
24static const struct gates_data sun6i_a31_apb0_gates __initconst = {
25	.mask = {0x7F},
26};
27
28static const struct gates_data sun8i_a23_apb0_gates __initconst = {
29	.mask = {0x5D},
30};
31
32static const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
33	{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates },
34	{ .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates },
35	{ /* sentinel */ }
36};
37MODULE_DEVICE_TABLE(of, sun6i_a31_apb0_gates_clk_dt_ids);
38
39static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
40{
41	struct device_node *np = pdev->dev.of_node;
42	struct clk_onecell_data *clk_data;
43	const struct of_device_id *device;
44	const struct gates_data *data;
45	const char *clk_parent;
46	const char *clk_name;
47	struct resource *r;
48	void __iomem *reg;
49	int ngates;
50	int i;
51	int j = 0;
52
53	if (!np)
54		return -ENODEV;
55
56	device = of_match_device(sun6i_a31_apb0_gates_clk_dt_ids, &pdev->dev);
57	if (!device)
58		return -ENODEV;
59	data = device->data;
60
61	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
62	reg = devm_ioremap_resource(&pdev->dev, r);
63	if (IS_ERR(reg))
64		return PTR_ERR(reg);
65
66	clk_parent = of_clk_get_parent_name(np, 0);
67	if (!clk_parent)
68		return -EINVAL;
69
70	clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data),
71				GFP_KERNEL);
72	if (!clk_data)
73		return -ENOMEM;
74
75	/* Worst-case size approximation and memory allocation */
76	ngates = find_last_bit(data->mask, SUN6I_APB0_GATES_MAX_SIZE);
77	clk_data->clks = devm_kcalloc(&pdev->dev, (ngates + 1),
78				      sizeof(struct clk *), GFP_KERNEL);
79	if (!clk_data->clks)
80		return -ENOMEM;
81
82	for_each_set_bit(i, data->mask, SUN6I_APB0_GATES_MAX_SIZE) {
83		of_property_read_string_index(np, "clock-output-names",
84					      j, &clk_name);
85
86		clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
87						      clk_parent, 0, reg, i,
88						      0, NULL);
89		WARN_ON(IS_ERR(clk_data->clks[i]));
90		clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
91
92		j++;
93	}
94
95	clk_data->clk_num = ngates + 1;
96
97	return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
98}
99
100static struct platform_driver sun6i_a31_apb0_gates_clk_driver = {
101	.driver = {
102		.name = "sun6i-a31-apb0-gates-clk",
103		.of_match_table = sun6i_a31_apb0_gates_clk_dt_ids,
104	},
105	.probe = sun6i_a31_apb0_gates_clk_probe,
106};
107module_platform_driver(sun6i_a31_apb0_gates_clk_driver);
108
109MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
110MODULE_DESCRIPTION("Allwinner A31 APB0 gate clocks driver");
111MODULE_LICENSE("GPL v2");
112