Lines Matching refs:clks

105 					clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
106 					         <&clks IMX5_CLK_DUMMY>,
107 					         <&clks IMX5_CLK_ESDHC1_PER_GATE>;
117 					clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
118 					         <&clks IMX5_CLK_DUMMY>,
119 					         <&clks IMX5_CLK_ESDHC2_PER_GATE>;
129 					clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
130 					         <&clks IMX5_CLK_UART3_PER_GATE>;
141 					clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
142 					         <&clks IMX5_CLK_ECSPI1_PER_GATE>;
154 					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
166 					clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
167 					         <&clks IMX5_CLK_DUMMY>,
168 					         <&clks IMX5_CLK_ESDHC3_PER_GATE>;
178 					clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
179 					         <&clks IMX5_CLK_DUMMY>,
180 					         <&clks IMX5_CLK_ESDHC4_PER_GATE>;
191 				clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
199 				clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
208 				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
217 				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
266 				clocks = <&clks IMX5_CLK_DUMMY>;
273 				clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
274 				         <&clks IMX5_CLK_GPT_HF_GATE>;
292 				clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
293 				         <&clks IMX5_CLK_PWM1_HF_GATE>;
302 				clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
303 				         <&clks IMX5_CLK_PWM2_HF_GATE>;
312 				clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
313 				         <&clks IMX5_CLK_UART1_PER_GATE>;
322 				clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
323 				         <&clks IMX5_CLK_UART2_PER_GATE>;
334 			clks: ccm@53fd4000{  label
367 				clocks = <&clks IMX5_CLK_I2C3_GATE>;
375 				clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
376 				         <&clks IMX5_CLK_UART4_PER_GATE>;
393 				clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
394 				         <&clks IMX5_CLK_UART5_PER_GATE>;
402 				clocks = <&clks IMX5_CLK_OWIRE_GATE>;
412 				clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
413 				         <&clks IMX5_CLK_ECSPI2_PER_GATE>;
422 				clocks = <&clks IMX5_CLK_SDMA_GATE>,
423 				         <&clks IMX5_CLK_SDMA_GATE>;
434 				clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
435 				         <&clks IMX5_CLK_CSPI_IPG_GATE>;
446 				clocks = <&clks IMX5_CLK_I2C2_GATE>;
456 				clocks = <&clks IMX5_CLK_I2C1_GATE>;
466 				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
484 				clocks = <&clks IMX5_CLK_FEC_GATE>,
485 				         <&clks IMX5_CLK_FEC_GATE>,
486 				         <&clks IMX5_CLK_FEC_GATE>;