Home
last modified time | relevance | path

Searched refs:cache (Results 1 – 200 of 960) sorted by relevance

12345

/linux-4.4.14/drivers/md/
Ddm-cache-target.c219 struct cache { struct
349 struct cache *cache; member
356 struct cache *cache; member
386 static enum cache_metadata_mode get_cache_mode(struct cache *cache);
388 static void wake_worker(struct cache *cache) in wake_worker() argument
390 queue_work(cache->wq, &cache->worker); in wake_worker()
395 static struct dm_bio_prison_cell *alloc_prison_cell(struct cache *cache) in alloc_prison_cell() argument
398 return dm_bio_prison_alloc_cell(cache->prison, GFP_NOWAIT); in alloc_prison_cell()
401 static void free_prison_cell(struct cache *cache, struct dm_bio_prison_cell *cell) in free_prison_cell() argument
403 dm_bio_prison_free_cell(cache->prison, cell); in free_prison_cell()
[all …]
DMakefile14 dm-cache-y += dm-cache-target.o dm-cache-metadata.o dm-cache-policy.o
15 dm-cache-mq-y += dm-cache-policy-mq.o
16 dm-cache-smq-y += dm-cache-policy-smq.o
17 dm-cache-cleaner-y += dm-cache-policy-cleaner.o
20 raid456-y += raid5.o raid5-cache.o
56 obj-$(CONFIG_DM_CACHE) += dm-cache.o
57 obj-$(CONFIG_DM_CACHE_MQ) += dm-cache-mq.o
58 obj-$(CONFIG_DM_CACHE_SMQ) += dm-cache-smq.o
59 obj-$(CONFIG_DM_CACHE_CLEANER) += dm-cache-cleaner.o
/linux-4.4.14/arch/powerpc/kernel/
Dcacheinfo.c43 struct cache *cache; member
117 struct cache { struct
123 struct cache *next_local; /* next cache of >= level */ argument
138 static const char *cache_type_string(const struct cache *cache) in cache_type_string() argument
140 return cache_type_info[cache->type].name; in cache_type_string()
143 static void cache_init(struct cache *cache, int type, int level, in cache_init() argument
146 cache->type = type; in cache_init()
147 cache->level = level; in cache_init()
148 cache->ofnode = of_node_get(ofnode); in cache_init()
149 INIT_LIST_HEAD(&cache->list); in cache_init()
[all …]
/linux-4.4.14/fs/btrfs/tests/
Dfree-space-tests.c28 struct btrfs_block_group_cache *cache; in init_test_block_group() local
30 cache = kzalloc(sizeof(*cache), GFP_NOFS); in init_test_block_group()
31 if (!cache) in init_test_block_group()
33 cache->free_space_ctl = kzalloc(sizeof(*cache->free_space_ctl), in init_test_block_group()
35 if (!cache->free_space_ctl) { in init_test_block_group()
36 kfree(cache); in init_test_block_group()
39 cache->fs_info = btrfs_alloc_dummy_fs_info(); in init_test_block_group()
40 if (!cache->fs_info) { in init_test_block_group()
41 kfree(cache->free_space_ctl); in init_test_block_group()
42 kfree(cache); in init_test_block_group()
[all …]
/linux-4.4.14/fs/cachefiles/
Dbind.c30 int cachefiles_daemon_bind(struct cachefiles_cache *cache, char *args) in cachefiles_daemon_bind() argument
33 cache->frun_percent, in cachefiles_daemon_bind()
34 cache->fcull_percent, in cachefiles_daemon_bind()
35 cache->fstop_percent, in cachefiles_daemon_bind()
36 cache->brun_percent, in cachefiles_daemon_bind()
37 cache->bcull_percent, in cachefiles_daemon_bind()
38 cache->bstop_percent, in cachefiles_daemon_bind()
42 ASSERT(cache->fstop_percent >= 0 && in cachefiles_daemon_bind()
43 cache->fstop_percent < cache->fcull_percent && in cachefiles_daemon_bind()
44 cache->fcull_percent < cache->frun_percent && in cachefiles_daemon_bind()
[all …]
Ddaemon.c63 int (*handler)(struct cachefiles_cache *cache, char *args);
89 struct cachefiles_cache *cache; in cachefiles_daemon_open() local
102 cache = kzalloc(sizeof(struct cachefiles_cache), GFP_KERNEL); in cachefiles_daemon_open()
103 if (!cache) { in cachefiles_daemon_open()
108 mutex_init(&cache->daemon_mutex); in cachefiles_daemon_open()
109 cache->active_nodes = RB_ROOT; in cachefiles_daemon_open()
110 rwlock_init(&cache->active_lock); in cachefiles_daemon_open()
111 init_waitqueue_head(&cache->daemon_pollwq); in cachefiles_daemon_open()
118 cache->frun_percent = 7; in cachefiles_daemon_open()
119 cache->fcull_percent = 5; in cachefiles_daemon_open()
[all …]
Dinterface.c32 struct cachefiles_cache *cache; in cachefiles_alloc_object() local
38 cache = container_of(_cache, struct cachefiles_cache, cache); in cachefiles_alloc_object()
40 _enter("{%s},%p,", cache->cache.identifier, cookie); in cachefiles_alloc_object()
56 fscache_object_init(&object->fscache, cookie, &cache->cache); in cachefiles_alloc_object()
105 fscache_object_destroyed(&cache->cache); in cachefiles_alloc_object()
121 struct cachefiles_cache *cache; in cachefiles_lookup_object() local
127 cache = container_of(_object->cache, struct cachefiles_cache, cache); in cachefiles_lookup_object()
136 cachefiles_begin_secure(cache, &saved_cred); in cachefiles_lookup_object()
140 cachefiles_end_secure(cache, saved_cred); in cachefiles_lookup_object()
202 struct cachefiles_cache *cache; in cachefiles_update_object() local
[all …]
Dnamei.c99 static void cachefiles_mark_object_buried(struct cachefiles_cache *cache, in cachefiles_mark_object_buried() argument
108 write_lock(&cache->active_lock); in cachefiles_mark_object_buried()
110 p = cache->active_nodes.rb_node; in cachefiles_mark_object_buried()
121 write_unlock(&cache->active_lock); in cachefiles_mark_object_buried()
141 write_unlock(&cache->active_lock); in cachefiles_mark_object_buried()
148 static int cachefiles_mark_object_active(struct cachefiles_cache *cache, in cachefiles_mark_object_active() argument
158 write_lock(&cache->active_lock); in cachefiles_mark_object_active()
167 _p = &cache->active_nodes.rb_node; in cachefiles_mark_object_active()
184 rb_insert_color(&object->active_node, &cache->active_nodes); in cachefiles_mark_object_active()
186 write_unlock(&cache->active_lock); in cachefiles_mark_object_active()
[all …]
Dsecurity.c20 int cachefiles_get_security_ID(struct cachefiles_cache *cache) in cachefiles_get_security_ID() argument
25 _enter("{%s}", cache->secctx); in cachefiles_get_security_ID()
33 if (cache->secctx) { in cachefiles_get_security_ID()
34 ret = set_security_override_from_ctx(new, cache->secctx); in cachefiles_get_security_ID()
43 cache->cache_cred = new; in cachefiles_get_security_ID()
53 static int cachefiles_check_cache_dir(struct cachefiles_cache *cache, in cachefiles_check_cache_dir() argument
79 int cachefiles_determine_cache_security(struct cachefiles_cache *cache, in cachefiles_determine_cache_security() argument
94 cachefiles_end_secure(cache, *_saved_cred); in cachefiles_determine_cache_security()
101 cachefiles_begin_secure(cache, _saved_cred); in cachefiles_determine_cache_security()
106 put_cred(cache->cache_cred); in cachefiles_determine_cache_security()
[all …]
Dinternal.h59 struct fscache_cache cache; /* FS-Cache record */ member
127 static inline void cachefiles_state_changed(struct cachefiles_cache *cache) in cachefiles_state_changed() argument
129 set_bit(CACHEFILES_STATE_CHANGED, &cache->flags); in cachefiles_state_changed()
130 wake_up_all(&cache->daemon_pollwq); in cachefiles_state_changed()
136 extern int cachefiles_daemon_bind(struct cachefiles_cache *cache, char *args);
137 extern void cachefiles_daemon_unbind(struct cachefiles_cache *cache);
144 extern int cachefiles_has_space(struct cachefiles_cache *cache,
160 extern int cachefiles_delete_object(struct cachefiles_cache *cache,
166 extern struct dentry *cachefiles_get_directory(struct cachefiles_cache *cache,
170 extern int cachefiles_cull(struct cachefiles_cache *cache, struct dentry *dir,
[all …]
Drdwr.c395 struct cachefiles_cache *cache; in cachefiles_read_or_alloc_page() local
403 cache = container_of(object->fscache.cache, in cachefiles_read_or_alloc_page()
404 struct cachefiles_cache, cache); in cachefiles_read_or_alloc_page()
441 } else if (cachefiles_has_space(cache, 0, 1) == 0) { in cachefiles_read_or_alloc_page()
681 struct cachefiles_cache *cache; in cachefiles_read_or_alloc_pages() local
691 cache = container_of(object->fscache.cache, in cachefiles_read_or_alloc_pages()
692 struct cachefiles_cache, cache); in cachefiles_read_or_alloc_pages()
702 if (cachefiles_has_space(cache, 0, *nr_pages) < 0) in cachefiles_read_or_alloc_pages()
795 struct cachefiles_cache *cache; in cachefiles_allocate_page() local
800 cache = container_of(object->fscache.cache, in cachefiles_allocate_page()
[all …]
/linux-4.4.14/drivers/acpi/acpica/
Dutcache.c70 struct acpi_memory_list *cache; in acpi_os_create_cache() local
80 cache = acpi_os_allocate(sizeof(struct acpi_memory_list)); in acpi_os_create_cache()
81 if (!cache) { in acpi_os_create_cache()
87 memset(cache, 0, sizeof(struct acpi_memory_list)); in acpi_os_create_cache()
88 cache->list_name = cache_name; in acpi_os_create_cache()
89 cache->object_size = object_size; in acpi_os_create_cache()
90 cache->max_depth = max_depth; in acpi_os_create_cache()
92 *return_cache = cache; in acpi_os_create_cache()
108 acpi_status acpi_os_purge_cache(struct acpi_memory_list * cache) in acpi_os_purge_cache() argument
115 if (!cache) { in acpi_os_purge_cache()
[all …]
Duttrack.c96 struct acpi_memory_list *cache; in acpi_ut_create_list() local
98 cache = acpi_os_allocate(sizeof(struct acpi_memory_list)); in acpi_ut_create_list()
99 if (!cache) { in acpi_ut_create_list()
103 memset(cache, 0, sizeof(struct acpi_memory_list)); in acpi_ut_create_list()
105 cache->list_name = list_name; in acpi_ut_create_list()
106 cache->object_size = object_size; in acpi_ut_create_list()
108 *return_cache = cache; in acpi_ut_create_list()
/linux-4.4.14/fs/fscache/
Dcache.c99 struct fscache_cache *cache; in fscache_select_cache_for_object() local
117 cache = object->cache; in fscache_select_cache_for_object()
119 test_bit(FSCACHE_IOERROR, &cache->flags)) in fscache_select_cache_for_object()
120 cache = NULL; in fscache_select_cache_for_object()
123 _leave(" = %p [parent]", cache); in fscache_select_cache_for_object()
124 return cache; in fscache_select_cache_for_object()
151 if (!tag->cache) { in fscache_select_cache_for_object()
156 if (test_bit(FSCACHE_IOERROR, &tag->cache->flags)) in fscache_select_cache_for_object()
159 _leave(" = %p [specific]", tag->cache); in fscache_select_cache_for_object()
160 return tag->cache; in fscache_select_cache_for_object()
[all …]
Dcookie.c25 static int fscache_alloc_object(struct fscache_cache *cache,
194 struct fscache_cache *cache; in fscache_acquire_non_index_cookie() local
213 cache = fscache_select_cache_for_object(cookie->parent); in fscache_acquire_non_index_cookie()
214 if (!cache) { in fscache_acquire_non_index_cookie()
221 _debug("cache %s", cache->tag->name); in fscache_acquire_non_index_cookie()
227 ret = fscache_alloc_object(cache, cookie); in fscache_acquire_non_index_cookie()
278 static int fscache_alloc_object(struct fscache_cache *cache, in fscache_alloc_object() argument
284 _enter("%p,%p{%s}", cache, cookie, cookie->def->name); in fscache_alloc_object()
289 if (object->cache == cache) in fscache_alloc_object()
297 object = cache->ops->alloc_object(cache, cookie); in fscache_alloc_object()
[all …]
Dobject.c293 struct fscache_cache *cache) in fscache_object_init() argument
297 atomic_inc(&cache->object_count); in fscache_object_init()
314 object->cache = cache; in fscache_object_init()
395 object->cache->ops->grab_object(object)) { in fscache_initialise_object()
459 test_bit(FSCACHE_IOERROR, &object->cache->flags) || in fscache_look_up_object()
466 cookie->def->name, object->cache->tag->name); in fscache_look_up_object()
470 ret = object->cache->ops->lookup_object(object); in fscache_look_up_object()
585 object->cache->ops->lookup_complete(object); in fscache_object_available()
621 object->cache->ops->lookup_complete(object); in fscache_lookup_failure()
687 struct fscache_cache *cache = object->cache; in fscache_drop_object() local
[all …]
Doperation.c481 struct fscache_cache *cache; in fscache_put_operation() local
518 cache = object->cache; in fscache_put_operation()
519 spin_lock(&cache->op_gc_list_lock); in fscache_put_operation()
520 list_add_tail(&op->pend_link, &cache->op_gc_list); in fscache_put_operation()
521 spin_unlock(&cache->op_gc_list_lock); in fscache_put_operation()
522 schedule_work(&cache->op_gc); in fscache_put_operation()
547 struct fscache_cache *cache = in fscache_operation_gc() local
554 spin_lock(&cache->op_gc_list_lock); in fscache_operation_gc()
555 if (list_empty(&cache->op_gc_list)) { in fscache_operation_gc()
556 spin_unlock(&cache->op_gc_list_lock); in fscache_operation_gc()
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/arm/uniphier/
Dcache-uniphier.txt1 UniPhier outer cache controller
3 UniPhier SoCs are integrated with a full-custom outer cache controller system.
4 All of them have a level 2 cache controller, and some have a level 3 cache
8 - compatible: should be "socionext,uniphier-system-cache"
12 - cache-unified: specifies the cache is a unified cache.
13 - cache-size: specifies the size in bytes of the cache
14 - cache-sets: specifies the number of associativity sets of the cache
15 - cache-line-size: specifies the line size in bytes
16 - cache-level: specifies the level in the cache hierarchy. The value should
17 be 2 for L2 cache, 3 for L3 cache, etc.
[all …]
/linux-4.4.14/drivers/staging/lustre/lustre/fld/
Dfld_cache.c66 struct fld_cache *cache; in fld_cache_init() local
71 cache = kzalloc(sizeof(*cache), GFP_NOFS); in fld_cache_init()
72 if (!cache) in fld_cache_init()
75 INIT_LIST_HEAD(&cache->fci_entries_head); in fld_cache_init()
76 INIT_LIST_HEAD(&cache->fci_lru); in fld_cache_init()
78 cache->fci_cache_count = 0; in fld_cache_init()
79 rwlock_init(&cache->fci_lock); in fld_cache_init()
81 strlcpy(cache->fci_name, name, in fld_cache_init()
82 sizeof(cache->fci_name)); in fld_cache_init()
84 cache->fci_cache_size = cache_size; in fld_cache_init()
[all …]
Dfld_internal.h149 void fld_cache_fini(struct fld_cache *cache);
151 void fld_cache_flush(struct fld_cache *cache);
153 int fld_cache_insert(struct fld_cache *cache,
159 int fld_cache_insert_nolock(struct fld_cache *cache,
161 void fld_cache_delete(struct fld_cache *cache,
163 void fld_cache_delete_nolock(struct fld_cache *cache,
165 int fld_cache_lookup(struct fld_cache *cache,
169 fld_cache_entry_lookup(struct fld_cache *cache, struct lu_seq_range *range);
170 void fld_cache_entry_delete(struct fld_cache *cache,
172 void fld_dump_cache_entries(struct fld_cache *cache);
[all …]
/linux-4.4.14/fs/squashfs/
Dcache.c66 struct squashfs_cache *cache, u64 block, int length) in squashfs_cache_get() argument
71 spin_lock(&cache->lock); in squashfs_cache_get()
74 for (i = cache->curr_blk, n = 0; n < cache->entries; n++) { in squashfs_cache_get()
75 if (cache->entry[i].block == block) { in squashfs_cache_get()
76 cache->curr_blk = i; in squashfs_cache_get()
79 i = (i + 1) % cache->entries; in squashfs_cache_get()
82 if (n == cache->entries) { in squashfs_cache_get()
87 if (cache->unused == 0) { in squashfs_cache_get()
88 cache->num_waiters++; in squashfs_cache_get()
89 spin_unlock(&cache->lock); in squashfs_cache_get()
[all …]
/linux-4.4.14/arch/mn10300/mm/
DMakefile5 cache-smp-wback-$(CONFIG_MN10300_CACHE_WBACK) := cache-smp-flush.o
7 cacheflush-y := cache.o
8 cacheflush-$(CONFIG_SMP) += cache-smp.o cache-smp-inv.o $(cache-smp-wback-y)
9 cacheflush-$(CONFIG_MN10300_CACHE_INV_ICACHE) += cache-inv-icache.o
10 cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_ICACHE) += cache-flush-icache.o
11 cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_TAG) += cache-inv-by-tag.o
12 cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_REG) += cache-inv-by-reg.o
13 cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_TAG) += cache-flush-by-tag.o
14 cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_REG) += cache-flush-by-reg.o
17 cache-dbg-flush-by-tag.o cache-dbg-inv-by-tag.o
[all …]
DKconfig.cache2 # MN10300 CPU cache options
12 the affected cacheline to be read into the cache first before being
13 operated upon. Memory is not then updated by a write until the cache
14 is filled and a cacheline needs to be displaced from the cache to
19 cacheline is also in cache, it will be updated too.
35 cache. This means that the written data is immediately available for
38 This is not available for use with an SMP kernel if cache flushing
53 prompt "CPU cache flush/invalidate method"
58 This determines the method by which CPU cache flushing and
62 bool "Use the cache tag registers directly"
[all …]
Dcache.inc15 # Invalidate the instruction cache.
27 # don't want an interrupt routine seeing a disabled cache
49 # wait for the cache to finish
76 # Invalidate the data cache.
88 # don't want an interrupt routine seeing a disabled cache
110 # wait for the cache to finish
Dcache-dbg-flush-by-tag.S26 # Flush the entire data cache back to RAM and invalidate the icache
43 # read the addresses tagged in the cache's tag RAM and attempt to flush
103 # retain valid entries in the cache
Dcache-flush-by-tag.S45 # Flush the entire data cache back to RAM
56 # read the addresses tagged in the cache's tag RAM and attempt to flush
/linux-4.4.14/drivers/base/regmap/
Dregcache-flat.c22 unsigned int *cache; in regcache_flat_init() local
24 map->cache = kzalloc(sizeof(unsigned int) * (map->max_register + 1), in regcache_flat_init()
26 if (!map->cache) in regcache_flat_init()
29 cache = map->cache; in regcache_flat_init()
32 cache[map->reg_defaults[i].reg] = map->reg_defaults[i].def; in regcache_flat_init()
39 kfree(map->cache); in regcache_flat_exit()
40 map->cache = NULL; in regcache_flat_exit()
48 unsigned int *cache = map->cache; in regcache_flat_read() local
50 *value = cache[reg]; in regcache_flat_read()
58 unsigned int *cache = map->cache; in regcache_flat_write() local
[all …]
Dregcache.c128 map->cache = NULL; in regcache_init()
537 u8 *cache = base; in regcache_set_val() local
538 cache[idx] = val; in regcache_set_val()
542 u16 *cache = base; in regcache_set_val() local
543 cache[idx] = val; in regcache_set_val()
547 u32 *cache = base; in regcache_set_val() local
548 cache[idx] = val; in regcache_set_val()
570 const u8 *cache = base; in regcache_get_val() local
571 return cache[idx]; in regcache_get_val()
574 const u16 *cache = base; in regcache_get_val() local
[all …]
Dregcache-lzo.c142 map->cache = kzalloc(blkcount * sizeof *lzo_blocks, in regcache_lzo_init()
144 if (!map->cache) in regcache_lzo_init()
146 lzo_blocks = map->cache; in regcache_lzo_init()
209 lzo_blocks = map->cache; in regcache_lzo_exit()
230 map->cache = NULL; in regcache_lzo_exit()
248 lzo_blocks = map->cache; in regcache_lzo_read()
287 lzo_blocks = map->cache; in regcache_lzo_write()
342 lzo_blocks = map->cache; in regcache_lzo_sync()
Dregcache-rbtree.c69 struct regcache_rbtree_ctx *rbtree_ctx = map->cache; in regcache_rbtree_lookup()
140 struct regcache_rbtree_ctx *rbtree_ctx = map->cache; in rbtree_show()
205 map->cache = kmalloc(sizeof *rbtree_ctx, GFP_KERNEL); in regcache_rbtree_init()
206 if (!map->cache) in regcache_rbtree_init()
209 rbtree_ctx = map->cache; in regcache_rbtree_init()
235 rbtree_ctx = map->cache; in regcache_rbtree_exit()
251 kfree(map->cache); in regcache_rbtree_exit()
252 map->cache = NULL; in regcache_rbtree_exit()
392 rbtree_ctx = map->cache; in regcache_rbtree_write()
466 rbtree_ctx = map->cache; in regcache_rbtree_sync()
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/arm/
Dl2cc.txt3 ARM cores often have a separate level 2 cache controller. There are various
4 implementations of the L2 cache controller with compatible programming models.
5 Some of the properties that are just prefixed "cache-*" are taken from section
9 The ARM L2 cache representation in the device tree should be done as follows:
14 "arm,pl310-cache"
15 "arm,l220-cache"
16 "arm,l210-cache"
17 "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
18 "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
20 cache controller
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/powerpc/fsl/
Dl2cache.txt3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are ePAPR compliant
8 - compatible : Should include "fsl,chip-l2-cache-controller" and "cache"
10 - reg : Address and size of L2 cache controller registers
11 - cache-size : Size of the entire L2 cache
13 - cache-line-size : Size of L2 cache lines
17 L2: l2-cache-controller@20000 {
18 compatible = "fsl,bsc9132-l2-cache-controller", "cache";
20 cache-line-size = <32>; // 32 bytes
21 cache-size = <0x40000>; // L2,256K
Dcache_sram.txt4 option of configuring a part of (or full) cache memory
5 as SRAM. This cache SRAM representation in the device
10 - compatible : should be "fsl,p2020-cache-sram"
11 - fsl,cache-sram-ctlr-handle : points to the L2 controller
12 - reg : offset and length of the cache-sram.
16 cache-sram@fff00000 {
17 fsl,cache-sram-ctlr-handle = <&L2>;
19 compatible = "fsl,p2020-cache-sram";
Dpamu.txt59 - fsl,primary-cache-geometry
62 cache. The first is the number of cache lines, and the
65 - fsl,secondary-cache-geometry
68 cache. The first is the number of cache lines, and the
83 best LIODN values to minimize PAMU cache thrashing.
109 fsl,primary-cache-geometry = <32 1>;
110 fsl,secondary-cache-geometry = <128 2>;
115 fsl,primary-cache-geometry = <32 1>;
116 fsl,secondary-cache-geometry = <128 2>;
121 fsl,primary-cache-geometry = <32 1>;
[all …]
/linux-4.4.14/fs/
Dmbcache.c193 struct mb_cache *cache = ce->e_cache; in __mb_cache_entry_forget() local
196 kmem_cache_free(cache->c_entry_cache, ce); in __mb_cache_entry_forget()
197 atomic_dec(&cache->c_entry_count); in __mb_cache_entry_forget()
293 struct mb_cache *cache; in mb_cache_shrink_count() local
297 list_for_each_entry(cache, &mb_cache_list, c_cache_list) { in mb_cache_shrink_count()
298 mb_debug("cache %s (%d)", cache->c_name, in mb_cache_shrink_count()
299 atomic_read(&cache->c_entry_count)); in mb_cache_shrink_count()
300 count += atomic_read(&cache->c_entry_count); in mb_cache_shrink_count()
328 struct mb_cache *cache = NULL; in mb_cache_create() local
338 cache = kmalloc(sizeof(struct mb_cache), GFP_KERNEL); in mb_cache_create()
[all …]
/linux-4.4.14/drivers/video/fbdev/
Dsh_mobile_meram.c133 struct sh_mobile_meram_icb *cache; member
227 plane->cache = &priv->icbs[idx]; in meram_plane_alloc()
239 __set_bit(plane->cache->index, &priv->used_icb); in meram_plane_alloc()
255 __clear_bit(plane->cache->index, &priv->used_icb); in meram_plane_free()
269 struct sh_mobile_meram_fb_cache *cache, in meram_set_next_addr() argument
273 struct sh_mobile_meram_icb *icb = cache->planes[0].marker; in meram_set_next_addr()
280 meram_write_icb(priv->base, cache->planes[0].cache->index, target, in meram_set_next_addr()
282 meram_write_icb(priv->base, cache->planes[0].marker->index, target, in meram_set_next_addr()
283 base_addr_y + cache->planes[0].marker->cache_unit); in meram_set_next_addr()
285 if (cache->nplanes == 2) { in meram_set_next_addr()
[all …]
/linux-4.4.14/drivers/staging/rdma/hfi1/
Dqsfp.c304 u8 *cache = &cp->cache[0]; in refresh_qsfp_cache() local
307 memset(cache, 0, (QSFP_MAX_NUM_PAGES*128)); in refresh_qsfp_cache()
314 ret = qsfp_read(ppd, target, 0, cache, 256); in refresh_qsfp_cache()
322 if (cache[0] != 0x0C && cache[0] != 0x0D) in refresh_qsfp_cache()
326 if (!(cache[2] & 4)) { in refresh_qsfp_cache()
329 if ((cache[195] & 0xC0) == 0xC0) { in refresh_qsfp_cache()
331 ret = qsfp_read(ppd, target, 384, cache + 256, 128); in refresh_qsfp_cache()
336 ret = qsfp_read(ppd, target, 640, cache + 384, 128); in refresh_qsfp_cache()
341 ret = qsfp_read(ppd, target, 896, cache + 512, 128); in refresh_qsfp_cache()
346 } else if ((cache[195] & 0x80) == 0x80) { in refresh_qsfp_cache()
[all …]
/linux-4.4.14/Documentation/device-mapper/
Dcache.txt4 dm-cache is a device mapper target written by Joe Thornber, Heinz
33 may be out of date or kept in sync with the copy on the cache device
47 2. A cache device - the small, fast one.
49 3. A small metadata device - records which blocks are in the cache,
51 This information could be put on the cache device, but having it
54 be used by a single cache device.
60 is configurable when you first create the cache. Typically we've been
66 getting hit a lot, yet the whole block will be promoted to the cache.
67 So large block sizes are bad because they waste cache space. And small
74 The cache has three operating modes: writeback, writethrough and
[all …]
Dcache-policies.txt25 Overview of supplied cache replacement policies
34 waiting for the cache and another two for those in the cache (a set for
38 the cache is based on variable thresholds and queue selection is based
39 on hit count on entry. The policy aims to take different cache miss
51 considered sequential it will bypass the cache. The random threshold
61 promote sequential blocks to the cache (e.g. fast application startup).
63 disabled and sequential I/O will no longer implicitly bypass the cache.
68 count of a block not in the cache goes above this threshold it gets
69 promoted to the cache. The read, write and discard promote adjustment
72 If you're trying to quickly warm a new cache device you may wish to
[all …]
Dera.txt11 partially invalidating the contents of a cache to restore cache
64 The scenario of invalidating a cache when rolling back a vendor
78 - Cache enters passthrough mode (see: dm-cache's docs in cache.txt)
/linux-4.4.14/fs/overlayfs/
Dreaddir.c51 struct ovl_dir_cache *cache; member
175 struct ovl_dir_cache *cache = od->cache; in ovl_cache_put() local
177 WARN_ON(cache->refcount <= 0); in ovl_cache_put()
178 cache->refcount--; in ovl_cache_put()
179 if (!cache->refcount) { in ovl_cache_put()
180 if (ovl_dir_cache(dentry) == cache) in ovl_cache_put()
183 ovl_cache_free(&cache->entries); in ovl_cache_put()
184 kfree(cache); in ovl_cache_put()
270 struct ovl_dir_cache *cache = od->cache; in ovl_dir_reset() local
274 if (cache && ovl_dentry_version_get(dentry) != cache->version) { in ovl_dir_reset()
[all …]
/linux-4.4.14/tools/perf/Documentation/
Dperf-buildid-cache.txt1 perf-buildid-cache(1)
6 perf-buildid-cache - Manage build-id cache.
11 'perf buildid-cache <options>'
15 This command manages the build-id cache. It can add, remove, update and purge
16 files to/from the cache. In the future it should as well set upper limits for
17 the space used by the cache, etc.
23 Add specified file to the cache.
26 Add specified kcore file to the cache. For the current host that is
28 running 'perf buildid-cache' as root may update root's build-id cache
34 kcore in the cache (with the same build-id) that has the same modules at
[all …]
/linux-4.4.14/arch/powerpc/boot/dts/fsl/
Dp4080si-pre.dtsi98 next-level-cache = <&L2_0>;
100 L2_0: l2-cache {
101 next-level-cache = <&cpc>;
108 next-level-cache = <&L2_1>;
110 L2_1: l2-cache {
111 next-level-cache = <&cpc>;
118 next-level-cache = <&L2_2>;
120 L2_2: l2-cache {
121 next-level-cache = <&cpc>;
128 next-level-cache = <&L2_3>;
[all …]
Dt104xsi-pre.dtsi78 next-level-cache = <&L2_1>;
79 L2_1: l2-cache {
80 next-level-cache = <&cpc>;
87 next-level-cache = <&L2_2>;
88 L2_2: l2-cache {
89 next-level-cache = <&cpc>;
96 next-level-cache = <&L2_3>;
97 L2_3: l2-cache {
98 next-level-cache = <&cpc>;
105 next-level-cache = <&L2_4>;
[all …]
Dp2041si-pre.dtsi93 next-level-cache = <&L2_0>;
95 L2_0: l2-cache {
96 next-level-cache = <&cpc>;
103 next-level-cache = <&L2_1>;
105 L2_1: l2-cache {
106 next-level-cache = <&cpc>;
113 next-level-cache = <&L2_2>;
115 L2_2: l2-cache {
116 next-level-cache = <&cpc>;
123 next-level-cache = <&L2_3>;
[all …]
Dp3041si-pre.dtsi94 next-level-cache = <&L2_0>;
96 L2_0: l2-cache {
97 next-level-cache = <&cpc>;
104 next-level-cache = <&L2_1>;
106 L2_1: l2-cache {
107 next-level-cache = <&cpc>;
114 next-level-cache = <&L2_2>;
116 L2_2: l2-cache {
117 next-level-cache = <&cpc>;
124 next-level-cache = <&L2_3>;
[all …]
Dp5040si-pre.dtsi100 next-level-cache = <&L2_0>;
102 L2_0: l2-cache {
103 next-level-cache = <&cpc>;
110 next-level-cache = <&L2_1>;
112 L2_1: l2-cache {
113 next-level-cache = <&cpc>;
120 next-level-cache = <&L2_2>;
122 L2_2: l2-cache {
123 next-level-cache = <&cpc>;
130 next-level-cache = <&L2_3>;
[all …]
Dt4240si-pre.dtsi92 next-level-cache = <&L2_1>;
99 next-level-cache = <&L2_1>;
106 next-level-cache = <&L2_1>;
113 next-level-cache = <&L2_1>;
120 next-level-cache = <&L2_2>;
127 next-level-cache = <&L2_2>;
134 next-level-cache = <&L2_2>;
141 next-level-cache = <&L2_2>;
148 next-level-cache = <&L2_3>;
155 next-level-cache = <&L2_3>;
[all …]
Dt102xsi-pre.dtsi78 next-level-cache = <&L2_1>;
79 L2_1: l2-cache {
80 next-level-cache = <&cpc>;
87 next-level-cache = <&L2_2>;
88 L2_2: l2-cache {
89 next-level-cache = <&cpc>;
Dp5020si-pre.dtsi100 next-level-cache = <&L2_0>;
102 L2_0: l2-cache {
103 next-level-cache = <&cpc>;
110 next-level-cache = <&L2_1>;
112 L2_1: l2-cache {
113 next-level-cache = <&cpc>;
Db4420si-post.dtsi75 cpc: l3-cache-controller@10000 {
76 compatible = "fsl,b4420-l3-cache-controller", "cache";
92 L2_1: l2-cache-controller@c20000 {
93 compatible = "fsl,b4420-l2-cache-controller";
95 next-level-cache = <&cpc>;
Dp5040si-post.dtsi246 cpc: l3-cache-controller@10000 {
247 compatible = "fsl,p5040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
274 fsl,primary-cache-geometry = <32 1>;
275 fsl,secondary-cache-geometry = <128 2>;
280 fsl,primary-cache-geometry = <32 1>;
281 fsl,secondary-cache-geometry = <128 2>;
286 fsl,primary-cache-geometry = <32 1>;
287 fsl,secondary-cache-geometry = <128 2>;
292 fsl,primary-cache-geometry = <32 1>;
293 fsl,secondary-cache-geometry = <128 2>;
[all …]
Dp5020si-post.dtsi291 cpc: l3-cache-controller@10000 {
292 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
320 fsl,primary-cache-geometry = <32 1>;
321 fsl,secondary-cache-geometry = <128 2>;
326 fsl,primary-cache-geometry = <32 1>;
327 fsl,secondary-cache-geometry = <128 2>;
332 fsl,primary-cache-geometry = <32 1>;
333 fsl,secondary-cache-geometry = <128 2>;
338 fsl,primary-cache-geometry = <32 1>;
339 fsl,secondary-cache-geometry = <128 2>;
Dp2041si-post.dtsi261 cpc: l3-cache-controller@10000 {
262 compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
288 fsl,primary-cache-geometry = <32 1>;
289 fsl,secondary-cache-geometry = <128 2>;
294 fsl,primary-cache-geometry = <32 1>;
295 fsl,secondary-cache-geometry = <128 2>;
300 fsl,primary-cache-geometry = <32 1>;
301 fsl,secondary-cache-geometry = <128 2>;
306 fsl,primary-cache-geometry = <32 1>;
307 fsl,secondary-cache-geometry = <128 2>;
Dp3041si-post.dtsi288 cpc: l3-cache-controller@10000 {
289 compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
315 fsl,primary-cache-geometry = <32 1>;
316 fsl,secondary-cache-geometry = <128 2>;
321 fsl,primary-cache-geometry = <32 1>;
322 fsl,secondary-cache-geometry = <128 2>;
327 fsl,primary-cache-geometry = <32 1>;
328 fsl,secondary-cache-geometry = <128 2>;
333 fsl,primary-cache-geometry = <32 1>;
334 fsl,secondary-cache-geometry = <128 2>;
Dmpc8572ds_camp_core0.dts4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
44 l2-cache-controller@20000 {
45 cache-size = <0x80000>; // L2, 512K
/linux-4.4.14/fs/fat/
Dcache.c40 struct fat_cache *cache = (struct fat_cache *)foo; in init_once() local
42 INIT_LIST_HEAD(&cache->cache_list); in init_once()
66 static inline void fat_cache_free(struct fat_cache *cache) in fat_cache_free() argument
68 BUG_ON(!list_empty(&cache->cache_list)); in fat_cache_free()
69 kmem_cache_free(fat_cache_cachep, cache); in fat_cache_free()
73 struct fat_cache *cache) in fat_cache_update_lru() argument
75 if (MSDOS_I(inode)->cache_lru.next != &cache->cache_list) in fat_cache_update_lru()
76 list_move(&cache->cache_list, &MSDOS_I(inode)->cache_lru); in fat_cache_update_lru()
135 struct fat_cache *cache, *tmp; in fat_cache_add() local
145 cache = fat_cache_merge(inode, new); in fat_cache_add()
[all …]
/linux-4.4.14/Documentation/ABI/testing/
Dsysfs-block-bcache5 A write to this file causes the backing device or cache to be
6 unregistered. If a backing device had dirty data in the cache,
17 What: /sys/block/<disk>/bcache/cache
21 For a backing device that has cache, a symlink to
22 the bcache/ dir of that cache.
28 For backing devices: integer number of full cache hits,
29 counted per bio. A partial cache hit counts as a miss.
35 For backing devices: integer number of cache misses.
41 For backing devices: cache hits as a percentage.
48 skip the cache. Read and written as bytes in human readable
[all …]
Dsysfs-kernel-slab8 internal state of the SLUB allocator for each cache. Certain
9 files may be modified to change the behavior of the cache (and
10 any cache it aliases, if any).
13 What: /sys/kernel/slab/cache/aliases
20 have merged into this cache.
22 What: /sys/kernel/slab/cache/align
28 The align file is read-only and specifies the cache's object
31 What: /sys/kernel/slab/cache/alloc_calls
38 locations from which allocations for this cache were performed.
40 enabled for that cache (see Documentation/vm/slub.txt).
[all …]
Dsysfs-devices-system-cpu162 What: /sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1}
166 Description: Disable L3 cache indices
168 These files exist in every CPU's cache/index3 directory. Each
170 can be used to disable a cache index. Reading from these files
174 index to one of these files will cause the specificed cache
228 What: /sys/devices/system/cpu/cpu*/cache/index*/<set_of_attributes_mentioned_below>
232 Description: Parameters for the CPU cache attributes
235 - WriteAllocate: allocate a memory location to a cache line
236 on a cache miss because of a write
237 - ReadAllocate: allocate a memory location to a cache line
[all …]
Dsysfs-class-bdi36 total write-back cache that relates to its current average
40 percentage of the write-back cache to a particular device.
46 given percentage of the write-back cache. This is useful in
48 most of the write-back cache. For example in case of an NFS
/linux-4.4.14/drivers/power/
Dbq27xxx_battery.c132 struct bq27xxx_reg_cache cache; member
715 struct bq27xxx_reg_cache cache = {0, }; in bq27xxx_battery_update() local
719 cache.flags = bq27xxx_read(di, BQ27XXX_REG_FLAGS, has_singe_flag); in bq27xxx_battery_update()
720 if ((cache.flags & 0xff) == 0xff) in bq27xxx_battery_update()
721 cache.flags = -1; /* read error */ in bq27xxx_battery_update()
722 if (cache.flags >= 0) { in bq27xxx_battery_update()
723 cache.temperature = bq27xxx_battery_read_temperature(di); in bq27xxx_battery_update()
724 if (has_ci_flag && (cache.flags & BQ27000_FLAG_CI)) { in bq27xxx_battery_update()
726 cache.capacity = -ENODATA; in bq27xxx_battery_update()
727 cache.energy = -ENODATA; in bq27xxx_battery_update()
[all …]
/linux-4.4.14/Documentation/
Dbcache.txt2 nice if you could use them as cache... Hence bcache.
21 Writeback caching can use most of the cache for buffering writes - writing
30 thus entirely bypass the cache.
33 from disk or invalidating cache entries. For unrecoverable errors (meta data
35 in the cache it first disables writeback caching and waits for all dirty data
39 You'll need make-bcache from the bcache-tools repository. Both the cache device
45 you format your backing devices and cache device at the same time, you won't
57 device, it'll be running in passthrough mode until you attach it to a cache.
78 cache set shows up as /sys/fs/bcache/<UUID>
82 After your cache device and backing device are registered, the backing device
[all …]
Dcachetlb.txt6 This document describes the cache/tlb flushing interfaces called
16 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 "TLB" is abstracted under Linux as something the cpu uses to cache
26 possible for stale translations to exist in this "TLB" cache.
113 Next, we have the cache flushing interfaces. In general, when Linux
129 The cache level flush will always be first, because this allows
132 when that virtual address is flushed from the cache. The HyperSparc
135 The cache flushing routines below need only deal with cache flushing
149 the caches. That is, after running, there will be no cache
158 the caches. That is, after running, there will be no cache
[all …]
/linux-4.4.14/drivers/block/
Dps3vram.c83 struct ps3vram_cache cache; member
317 struct ps3vram_cache *cache = &priv->cache; in ps3vram_cache_evict() local
319 if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY)) in ps3vram_cache_evict()
323 cache->tags[entry].address); in ps3vram_cache_evict()
324 if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size, in ps3vram_cache_evict()
325 cache->tags[entry].address, DMA_PAGE_SIZE, in ps3vram_cache_evict()
326 cache->page_size / DMA_PAGE_SIZE) < 0) { in ps3vram_cache_evict()
329 entry * cache->page_size, cache->tags[entry].address, in ps3vram_cache_evict()
330 cache->page_size); in ps3vram_cache_evict()
332 cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY; in ps3vram_cache_evict()
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/arm/mrvl/
Dferoceon.txt4 - compatible : Should be either "marvell,feroceon-cache" or
5 "marvell,kirkwood-cache".
8 - reg : Address of the L2 cache control register. Mandatory for
9 "marvell,kirkwood-cache", not used by "marvell,feroceon-cache"
13 l2: l2-cache@20128 {
14 compatible = "marvell,kirkwood-cache";
Dtauros2.txt4 - compatible : Should be "marvell,tauros2-cache".
5 - marvell,tauros2-cache-features : Specify the features supported for the
6 tauros2 cache.
11 arch/arm/include/asm/hardware/cache-tauros2.h
14 L2: l2-cache {
15 compatible = "marvell,tauros2-cache";
16 marvell,tauros2-cache-features = <0x3>;
/linux-4.4.14/drivers/infiniband/core/
Dcache.c250 struct ib_gid_table **ports_table = ib_dev->cache.gid_cache; in ib_cache_gid_add()
301 struct ib_gid_table **ports_table = ib_dev->cache.gid_cache; in ib_cache_gid_del()
326 struct ib_gid_table **ports_table = ib_dev->cache.gid_cache; in ib_cache_gid_del_all_netdev_gids()
345 struct ib_gid_table **ports_table = ib_dev->cache.gid_cache; in __ib_cache_gid_get()
377 struct ib_gid_table **ports_table = ib_dev->cache.gid_cache; in _ib_cache_gid_table_find()
418 struct ib_gid_table **ports_table = ib_dev->cache.gid_cache; in ib_find_cached_gid_by_port()
472 struct ib_gid_table **ports_table = ib_dev->cache.gid_cache; in ib_cache_gid_find_by_filter()
573 struct ib_gid_table **ports_table = ib_dev->cache.gid_cache; in ib_cache_gid_set_default_gid()
664 ib_dev->cache.gid_cache = table; in _gid_table_setup_one()
680 struct ib_gid_table **table = ib_dev->cache.gid_cache; in gid_table_release_one()
[all …]
/linux-4.4.14/fs/btrfs/
Dextent-tree.c106 static int btrfs_update_reserved_bytes(struct btrfs_block_group_cache *cache,
115 block_group_cache_done(struct btrfs_block_group_cache *cache) in block_group_cache_done() argument
118 return cache->cached == BTRFS_CACHE_FINISHED || in block_group_cache_done()
119 cache->cached == BTRFS_CACHE_ERROR; in block_group_cache_done()
122 static int block_group_bits(struct btrfs_block_group_cache *cache, u64 bits) in block_group_bits() argument
124 return (cache->flags & bits) == bits; in block_group_bits()
127 void btrfs_get_block_group(struct btrfs_block_group_cache *cache) in btrfs_get_block_group() argument
129 atomic_inc(&cache->count); in btrfs_get_block_group()
132 void btrfs_put_block_group(struct btrfs_block_group_cache *cache) in btrfs_put_block_group() argument
134 if (atomic_dec_and_test(&cache->count)) { in btrfs_put_block_group()
[all …]
Drelocation.c196 static void remove_backref_node(struct backref_cache *cache,
207 static void backref_cache_init(struct backref_cache *cache) in backref_cache_init() argument
210 cache->rb_root = RB_ROOT; in backref_cache_init()
212 INIT_LIST_HEAD(&cache->pending[i]); in backref_cache_init()
213 INIT_LIST_HEAD(&cache->changed); in backref_cache_init()
214 INIT_LIST_HEAD(&cache->detached); in backref_cache_init()
215 INIT_LIST_HEAD(&cache->leaves); in backref_cache_init()
218 static void backref_cache_cleanup(struct backref_cache *cache) in backref_cache_cleanup() argument
223 while (!list_empty(&cache->detached)) { in backref_cache_cleanup()
224 node = list_entry(cache->detached.next, in backref_cache_cleanup()
[all …]
/linux-4.4.14/arch/powerpc/boot/dts/
Diss4xx-mpic.dts40 i-cache-line-size = <32>;
41 d-cache-line-size = <32>;
42 i-cache-size = <32768>;
43 d-cache-size = <32768>;
54 i-cache-line-size = <32>;
55 d-cache-line-size = <32>;
56 i-cache-size = <32768>;
57 d-cache-size = <32768>;
70 i-cache-line-size = <32>;
71 d-cache-line-size = <32>;
[all …]
Dsbc8548-pre.dtsi36 d-cache-line-size = <0x20>; // 32 bytes
37 i-cache-line-size = <0x20>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
43 next-level-cache = <&L2>;
Dstx_gp3_8560.dts34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>;
37 i-cache-size = <32768>;
41 next-level-cache = <&L2>;
78 L2: l2-cache-controller@20000 {
79 compatible = "fsl,mpc8540-l2-cache-controller";
81 cache-line-size = <32>;
82 cache-size = <0x40000>; // L2, 256K
Dtqm8541.dts35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
42 next-level-cache = <&L2>;
79 L2: l2-cache-controller@20000 {
80 compatible = "fsl,mpc8540-l2-cache-controller";
82 cache-line-size = <32>;
83 cache-size = <0x40000>; // L2, 256K
Dtqm8555.dts35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
42 next-level-cache = <&L2>;
79 L2: l2-cache-controller@20000 {
80 compatible = "fsl,mpc8540-l2-cache-controller";
82 cache-line-size = <32>;
83 cache-size = <0x40000>; // L2, 256K
Dtqm8540.dts36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <32768>;
39 i-cache-size = <32768>;
43 next-level-cache = <&L2>;
80 L2: l2-cache-controller@20000 {
81 compatible = "fsl,mpc8540-l2-cache-controller";
83 cache-line-size = <32>;
84 cache-size = <0x40000>; // L2, 256K
Dsocrates.dts36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
43 next-level-cache = <&L2>;
81 L2: l2-cache-controller@20000 {
82 compatible = "fsl,mpc8544-l2-cache-controller";
84 cache-line-size = <32>;
85 cache-size = <0x40000>; // L2, 256K
Dgamecube.dts42 i-cache-line-size = <32>;
43 d-cache-line-size = <32>;
44 i-cache-size = <32768>;
45 d-cache-size = <32768>;
Dksi8560.dts36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <0x8000>; /* L1, 32K */
39 i-cache-size = <0x8000>; /* L1, 32K */
43 next-level-cache = <&L2>;
79 L2: l2-cache-controller@20000 {
80 compatible = "fsl,mpc8540-l2-cache-controller";
82 cache-line-size = <0x20>; /* 32 bytes */
83 cache-size = <0x40000>; /* L2, 256K */
Dps3.dts64 i-cache-size = <32768>;
65 d-cache-size = <32768>;
66 i-cache-line-size = <128>;
67 d-cache-line-size = <128>;
Dxpedite5301.dts37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
44 next-level-cache = <&L2>;
50 d-cache-line-size = <32>; // 32 bytes
51 i-cache-line-size = <32>; // 32 bytes
52 d-cache-size = <0x8000>; // L1, 32K
53 i-cache-size = <0x8000>; // L1, 32K
57 next-level-cache = <&L2>;
[all …]
Dxpedite5370.dts35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
42 next-level-cache = <&L2>;
48 d-cache-line-size = <32>; // 32 bytes
49 i-cache-line-size = <32>; // 32 bytes
50 d-cache-size = <0x8000>; // L1, 32K
51 i-cache-size = <0x8000>; // L1, 32K
55 next-level-cache = <&L2>;
[all …]
Dholly.dts27 d-cache-line-size = <32>;
28 i-cache-line-size = <32>;
29 d-cache-size = <32768>;
30 i-cache-size = <32768>;
31 d-cache-sets = <128>;
32 i-cache-sets = <128>;
Dtqm8560.dts37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
40 i-cache-size = <32768>;
44 next-level-cache = <&L2>;
81 L2: l2-cache-controller@20000 {
82 compatible = "fsl,mpc8540-l2-cache-controller";
84 cache-line-size = <32>;
85 cache-size = <0x40000>; // L2, 256K
Darches.dts57 i-cache-line-size = <32>;
58 d-cache-line-size = <32>;
59 i-cache-size = <32768>;
60 d-cache-size = <32768>;
63 next-level-cache = <&L2C0>;
129 compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
131 0x030 0x008>; /* L2 cache DCR's */
132 cache-line-size = <32>; /* 32 bytes */
133 cache-size = <262144>; /* L2, 256K */
Dstorcenter.dts38 i-cache-line-size = <32>;
39 d-cache-line-size = <32>;
40 i-cache-size = <16384>;
41 d-cache-size = <16384>;
Dxpedite5330.dts73 d-cache-line-size = <32>; // 32 bytes
74 i-cache-line-size = <32>; // 32 bytes
75 d-cache-size = <0x8000>; // L1, 32K
76 i-cache-size = <0x8000>; // L1, 32K
80 next-level-cache = <&L2>;
86 d-cache-line-size = <32>; // 32 bytes
87 i-cache-line-size = <32>; // 32 bytes
88 d-cache-size = <0x8000>; // L1, 32K
89 i-cache-size = <0x8000>; // L1, 32K
93 next-level-cache = <&L2>;
[all …]
Dxcalibur1501.dts36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
43 next-level-cache = <&L2>;
49 d-cache-line-size = <32>; // 32 bytes
50 i-cache-line-size = <32>; // 32 bytes
51 d-cache-size = <0x8000>; // L1, 32K
52 i-cache-size = <0x8000>; // L1, 32K
56 next-level-cache = <&L2>;
[all …]
Diss4xx.dts38 i-cache-line-size = <32>; // may need fixup in sim
39 d-cache-line-size = <32>; // may need fixup in sim
40 i-cache-size = <32768>; /* may need fixup in sim */
41 d-cache-size = <32768>; /* may need fixup in sim */
/linux-4.4.14/arch/sh/mm/
Dcache-debugfs.c28 struct cache_info *cache; in cache_seq_show() local
49 cache = &current_cpu_data.dcache; in cache_seq_show()
52 cache = &current_cpu_data.icache; in cache_seq_show()
55 waysize = cache->sets; in cache_seq_show()
64 waysize <<= cache->entry_shift; in cache_seq_show()
66 for (way = 0; way < cache->ways; way++) { in cache_seq_show()
76 addr += cache->linesz, line++) { in cache_seq_show()
89 addrstart += cache->way_incr; in cache_seq_show()
DMakefile5 obj-y := alignment.o cache.o init.o consistent.o mmap.o
7 cacheops-$(CONFIG_CPU_SH2) := cache-sh2.o
8 cacheops-$(CONFIG_CPU_SH2A) := cache-sh2a.o
9 cacheops-$(CONFIG_CPU_SH3) := cache-sh3.o
10 cacheops-$(CONFIG_CPU_SH4) := cache-sh4.o flush-sh4.o
11 cacheops-$(CONFIG_CPU_SH5) := cache-sh5.o flush-sh4.o
12 cacheops-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o
13 cacheops-$(CONFIG_CPU_SHX3) += cache-shx3.o
25 debugfs-$(CONFIG_CPU_SH4) += cache-debugfs.o
/linux-4.4.14/arch/m68k/kernel/
Dsys_m68k.c67 cache_flush_040 (unsigned long addr, int scope, int cache, unsigned long len) in cache_flush_040() argument
74 switch (cache) in cache_flush_040()
127 switch (cache) in cache_flush_040()
184 switch (cache) in cache_flush_040()
227 cache_flush_060 (unsigned long addr, int scope, int cache, unsigned long len) in cache_flush_060() argument
240 switch (cache) in cache_flush_060()
288 switch (cache) in cache_flush_060()
347 switch (cache) in cache_flush_060()
377 sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len) in sys_cacheflush() argument
382 cache & ~FLUSH_CACHE_BOTH) in sys_cacheflush()
[all …]
/linux-4.4.14/Documentation/filesystems/caching/
Dbackend-api.txt9 This API is declared in <linux/fscache-cache.h>.
16 To start off, a cache definition must be initialised and registered for each
17 cache the backend wants to make available. For instance, CacheFS does this in
20 The cache definition (struct fscache_cache) should be initialised by calling:
22 void fscache_init_cache(struct fscache_cache *cache,
29 (*) "cache" is a pointer to the cache definition;
32 this cache; and
35 for the cache.
38 The cache should then be registered with FS-Cache by passing a pointer to the
39 previously initialised cache definition to:
[all …]
Dcachefiles.txt13 (*) Starting the cache.
34 CacheFiles is a caching backend that's meant to use as a cache a directory on
37 CacheFiles uses a userspace daemon to do some of the cache management - such as
41 The filesystem and data integrity of the cache are only as good as those of the
48 and whilst it is open, a cache is at least partially in existence. The daemon
49 opens this and sends commands down it to control the cache.
51 CacheFiles is currently limited to a single cache.
54 the filesystem, shrinking the cache by culling the objects it contains to make
66 available in the system and in the cache filesystem:
79 filesystems being used as a cache.
[all …]
Dnetfs-api.txt67 entire in-cache hierarchy for this netfs will be scrapped and begun
106 cache. Any such objects created within an index will be created in the
107 first cache only. The cache in which an index is created can be
108 controlled by cache tags (see below).
179 (3) A function to select the cache in which to store an index [optional].
181 This function is invoked when an index needs to be instantiated in a cache
189 cache in the parent's list will be chosen, or failing that, the first
190 cache in the master list.
203 this is a data file. The size may be used to govern how much cache must
204 be reserved for this file in the cache.
[all …]
Dfscache.txt9 This facility is a general purpose cache for network filesystems, though it
12 FS-Cache mediates between cache backends (such as CacheFS) and network
29 | ISOFS |--+ | /var/cache |
34 facility to a network filesystem such that the cache is transparent to the
54 +---------+ | /var/cache | | /dev/sda6 |
71 opened in its entirety into a cache before permitting it to be accessed and
72 then serving the pages out of that cache rather than the netfs inode because:
74 (1) It must be practical to operate without a cache.
77 cache.
80 must not be limited to the size of the cache.
[all …]
Dobject.txt30 a cache backend is currently actively caching. Such objects are represented by
31 the fscache_object struct. The cache backends allocate these upon request, and
36 represented by multiple objects - an index may exist in more than one cache -
108 (2) Initialisation: states that perform lookups in the cache and validate
149 to disconnecting the netfs's representation of a cache object (fscache_cookie)
150 from the cache backend's representation (fscache_object) - which may be
165 the cache, it is expected that it will not be possible to look an object
175 FS-Cache expects the cache backend to probe the cache to see whether this
179 The cache should call fscache_object_lookup_negative() to indicate lookup
187 to be read out of the cache for that file that isn't currently also held
[all …]
/linux-4.4.14/Documentation/filesystems/nfs/
Drpc-cache.txt24 - general cache lookup with correct locking
26 - allowing an EXPIRED time on cache items, and removing
28 - making requests to user-space to fill in cache entries
29 - allowing user-space to directly set entries in the cache
31 cache entries, and replaying those requests when the cache entry
38 1/ A cache needs a datum to store. This is in the form of a
43 Each cache element is reference counted and contains
44 expiry and update times for use in cache management.
45 2/ A cache needs a "cache_detail" structure that
46 describes the cache. This stores the hash table, some
[all …]
/linux-4.4.14/drivers/gpu/drm/amd/amdkfd/
Dkfd_topology.c220 static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache) in kfd_parse_subtype_cache() argument
226 BUG_ON(!cache); in kfd_parse_subtype_cache()
228 id = cache->processor_id_low; in kfd_parse_subtype_cache()
239 props->cache_level = cache->cache_level; in kfd_parse_subtype_cache()
240 props->cache_size = cache->cache_size; in kfd_parse_subtype_cache()
241 props->cacheline_size = cache->cache_line_size; in kfd_parse_subtype_cache()
242 props->cachelines_per_tag = cache->lines_per_tag; in kfd_parse_subtype_cache()
243 props->cache_assoc = cache->associativity; in kfd_parse_subtype_cache()
244 props->cache_latency = cache->cache_latency; in kfd_parse_subtype_cache()
246 if (cache->flags & CRAT_CACHE_FLAGS_DATA_CACHE) in kfd_parse_subtype_cache()
[all …]
/linux-4.4.14/drivers/infiniband/hw/mlx5/
Dmr.c72 struct mlx5_mr_cache *cache = &dev->cache; in order2idx() local
74 if (order < cache->ent[0].order) in order2idx()
77 return order - cache->ent[0].order; in order2idx()
84 struct mlx5_mr_cache *cache = &dev->cache; in reg_mr_callback() local
86 struct mlx5_cache_ent *ent = &cache->ent[c]; in reg_mr_callback()
118 cache->last_add = jiffies; in reg_mr_callback()
136 struct mlx5_mr_cache *cache = &dev->cache; in add_keys() local
137 struct mlx5_cache_ent *ent = &cache->ent[c]; in add_keys()
190 struct mlx5_mr_cache *cache = &dev->cache; in remove_keys() local
191 struct mlx5_cache_ent *ent = &cache->ent[c]; in remove_keys()
[all …]
/linux-4.4.14/include/net/
Dnetlabel.h209 struct netlbl_lsm_cache *cache; member
234 struct netlbl_lsm_cache *cache; in netlbl_secattr_cache_alloc() local
236 cache = kzalloc(sizeof(*cache), flags); in netlbl_secattr_cache_alloc()
237 if (cache) in netlbl_secattr_cache_alloc()
238 atomic_set(&cache->refcount, 1); in netlbl_secattr_cache_alloc()
239 return cache; in netlbl_secattr_cache_alloc()
250 static inline void netlbl_secattr_cache_free(struct netlbl_lsm_cache *cache) in netlbl_secattr_cache_free() argument
252 if (!atomic_dec_and_test(&cache->refcount)) in netlbl_secattr_cache_free()
255 if (cache->free) in netlbl_secattr_cache_free()
256 cache->free(cache->data); in netlbl_secattr_cache_free()
[all …]
/linux-4.4.14/tools/perf/util/
Ddso.c557 struct rb_root *root = &dso->data.cache; in dso_cache__free()
562 struct dso_cache *cache; in dso_cache__free() local
564 cache = rb_entry(next, struct dso_cache, rb_node); in dso_cache__free()
565 next = rb_next(&cache->rb_node); in dso_cache__free()
566 rb_erase(&cache->rb_node, root); in dso_cache__free()
567 free(cache); in dso_cache__free()
574 const struct rb_root *root = &dso->data.cache; in dso_cache__find()
577 struct dso_cache *cache; in dso_cache__find() local
583 cache = rb_entry(parent, struct dso_cache, rb_node); in dso_cache__find()
584 end = cache->offset + DSO__DATA_CACHE_SIZE; in dso_cache__find()
[all …]
Dordered-events.c92 struct list_head *cache = &oe->cache; in alloc_event() local
100 if (!list_empty(cache)) { in alloc_event()
101 new = list_entry(cache->next, struct ordered_event, list); in alloc_event()
150 list_move(&event->list, &oe->cache); in ordered_events__delete()
293 INIT_LIST_HEAD(&oe->cache); in ordered_events__init()
/linux-4.4.14/fs/nilfs2/
Dalloc.c273 struct nilfs_palloc_cache *cache = NILFS_MDT(inode)->mi_palloc_cache; in nilfs_palloc_get_desc_block() local
278 bhp, &cache->prev_desc, &cache->lock); in nilfs_palloc_get_desc_block()
292 struct nilfs_palloc_cache *cache = NILFS_MDT(inode)->mi_palloc_cache; in nilfs_palloc_get_bitmap_block() local
297 &cache->prev_bitmap, &cache->lock); in nilfs_palloc_get_bitmap_block()
308 struct nilfs_palloc_cache *cache = NILFS_MDT(inode)->mi_palloc_cache; in nilfs_palloc_delete_bitmap_block() local
313 &cache->prev_bitmap, &cache->lock); in nilfs_palloc_delete_bitmap_block()
326 struct nilfs_palloc_cache *cache = NILFS_MDT(inode)->mi_palloc_cache; in nilfs_palloc_get_entry_block() local
331 &cache->prev_entry, &cache->lock); in nilfs_palloc_get_entry_block()
341 struct nilfs_palloc_cache *cache = NILFS_MDT(inode)->mi_palloc_cache; in nilfs_palloc_delete_entry_block() local
345 &cache->prev_entry, &cache->lock); in nilfs_palloc_delete_entry_block()
[all …]
/linux-4.4.14/net/rds/
Dib_recv.c87 static void rds_ib_cache_xfer_to_ready(struct rds_ib_refill_cache *cache) in rds_ib_cache_xfer_to_ready() argument
91 tmp = xchg(&cache->xfer, NULL); in rds_ib_cache_xfer_to_ready()
93 if (cache->ready) in rds_ib_cache_xfer_to_ready()
94 list_splice_entire_tail(tmp, cache->ready); in rds_ib_cache_xfer_to_ready()
96 cache->ready = tmp; in rds_ib_cache_xfer_to_ready()
100 static int rds_ib_recv_alloc_cache(struct rds_ib_refill_cache *cache) in rds_ib_recv_alloc_cache() argument
105 cache->percpu = alloc_percpu(struct rds_ib_cache_head); in rds_ib_recv_alloc_cache()
106 if (!cache->percpu) in rds_ib_recv_alloc_cache()
110 head = per_cpu_ptr(cache->percpu, cpu); in rds_ib_recv_alloc_cache()
114 cache->xfer = NULL; in rds_ib_recv_alloc_cache()
[all …]
/linux-4.4.14/arch/arm/mm/
DMakefile39 obj-$(CONFIG_CPU_CACHE_V4) += cache-v4.o
40 obj-$(CONFIG_CPU_CACHE_V4WT) += cache-v4wt.o
41 obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o
42 obj-$(CONFIG_CPU_CACHE_V6) += cache-v6.o
43 obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o
44 obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o
45 obj-$(CONFIG_CPU_CACHE_NOP) += cache-nop.o
102 obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
103 obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o l2c-l2x0-resume.o
104 obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o
[all …]
Dcache-v7.S77 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
78 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
104 beq start_flush_levels @ start flushing cache levels
125 mov r10, #0 @ start clean at cache level 0
127 add r2, r10, r10, lsr #1 @ work out 3x current cache level
128 mov r1, r0, lsr r2 @ extract cache type bits from clidr
129 and r1, r1, #7 @ mask of the bits for current cache only
130 cmp r1, #2 @ see what cache we have at this level
131 blt skip @ skip if no cache, or just i-cache
135 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
[all …]
Dproc-arm940.S41 bic r0, r0, #0x00001000 @ i-cache
42 bic r0, r0, #0x00000004 @ d-cache
54 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
55 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
59 bic ip, ip, #0x00001000 @ i-cache
80 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
112 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
123 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
171 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
279 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
DKconfig17 which has no memory control unit and cache.
50 A 32-bit RISC processor with 8KB cache or 4KB variants,
67 which has no memory control unit and cache.
140 instruction sequences for cache and TLB operations. Curiously,
159 Branch Target Buffer, Unified TLB and cache line size 16.
242 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
490 # The cache model
539 ARM Architecture Version 4 TLB with writethrough cache.
544 ARM Architecture Version 4 TLB with writeback cache.
549 ARM Architecture Version 4 TLB with writeback cache and invalidate
[all …]
Dproc-arm946.S48 bic r0, r0, #0x00001000 @ i-cache
49 bic r0, r0, #0x00000004 @ d-cache
61 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
62 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
66 bic ip, ip, #0x00001000 @ i-cache
87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
107 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
118 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
213 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
332 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
Dproc-xscale.S94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
155 @ *** cache line aligned ***
193 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
217 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
239 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
240 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
241 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
[all …]
Dcache-v6.S43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
146 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
Dcache-v4wb.S30 # error Unknown cache size
61 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
80 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
114 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
117 bhs __flush_whole_cache @ flush whole D cache
172 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
Dcache-v4.S43 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
62 mcr p15, 0, ip, c7, c7, 0 @ flush ID cache
118 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
Dcache-v4wt.S51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
73 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
74 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
143 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
Dproc-feroceon.S60 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
64 mov r0, r0, lsr #18 @ get cache size order
68 mov r2, r2, lsl r0 @ actual cache size
136 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
170 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
255 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
269 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
488 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
589 .macro feroceon_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache:req
612 .long \cache
[all …]
Dproc-mohawk.S105 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
127 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
129 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
215 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
330 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
331 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
333 orr r0, r0, #0x18 @ cache the page table in L2
378 orr r1, r1, #0x18 @ cache the page table in L2
392 orr r4, r4, #0x18 @ cache the page table in L2
Dcache-fa.S48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
69 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
71 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
91 bhs __flush_whole_cache @ flush whole D cache
157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
/linux-4.4.14/drivers/net/wireless/cw1200/
Dtxrx.c216 static int tx_policy_find(struct tx_policy_cache *cache, in tx_policy_find() argument
225 list_for_each_entry(it, &cache->used, link) { in tx_policy_find()
227 return it - cache->cache; in tx_policy_find()
230 list_for_each_entry(it, &cache->free, link) { in tx_policy_find()
232 return it - cache->cache; in tx_policy_find()
237 static inline void tx_policy_use(struct tx_policy_cache *cache, in tx_policy_use() argument
241 list_move(&entry->link, &cache->used); in tx_policy_use()
244 static inline int tx_policy_release(struct tx_policy_cache *cache, in tx_policy_release() argument
249 list_move(&entry->link, &cache->free); in tx_policy_release()
256 struct tx_policy_cache *cache = &priv->tx_policy_cache; in tx_policy_clean() local
[all …]
/linux-4.4.14/arch/arm/boot/dts/
Dvf610.dtsi13 next-level-cache = <&L2>;
17 L2: l2-cache@40006000 {
18 compatible = "arm,pl310-cache";
20 cache-unified;
21 cache-level = <2>;
Duniphier-ph1-pro5.dtsi59 next-level-cache = <&l2>;
66 next-level-cache = <&l2>;
103 l2: l2-cache@500c0000 {
104 compatible = "socionext,uniphier-system-cache";
108 cache-unified;
109 cache-size = <(2 * 1024 * 1024)>;
110 cache-sets = <512>;
111 cache-line-size = <128>;
112 cache-level = <2>;
113 next-level-cache = <&l3>;
[all …]
Dbcm63138.dtsi27 next-level-cache = <&L2>;
35 next-level-cache = <&L2>;
67 L2: cache-controller@1d000 {
68 compatible = "arm,pl310-cache";
70 cache-unified;
71 cache-level = <2>;
72 cache-size = <524288>;
73 cache-sets = <1024>;
74 cache-line-size = <32>;
Dhighbank.dts37 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
65 next-level-cache = <&L2>;
74 next-level-cache = <&L2>;
119 L2: l2-cache {
120 compatible = "arm,pl310-cache";
123 cache-unified;
124 cache-level = <2>;
Dzx296702.dtsi15 next-level-cache = <&l2cc>;
22 next-level-cache = <&l2cc>;
58 l2cc: l2-cache-controller@0x00c00000 {
59 compatible = "arm,pl310-cache";
61 cache-unified;
62 cache-level = <2>;
Dvexpress-v2p-ca9.dts40 next-level-cache = <&L2>;
47 next-level-cache = <&L2>;
54 next-level-cache = <&L2>;
61 next-level-cache = <&L2>;
169 L2: cache-controller@1e00a000 {
170 compatible = "arm,pl310-cache";
173 cache-unified;
174 cache-level = <2>;
230 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
275 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
[all …]
Duniphier-proxstream2.dtsi59 next-level-cache = <&l2>;
66 next-level-cache = <&l2>;
73 next-level-cache = <&l2>;
80 next-level-cache = <&l2>;
117 l2: l2-cache@500c0000 {
118 compatible = "socionext,uniphier-system-cache";
122 cache-unified;
123 cache-size = <(1280 * 1024)>;
124 cache-sets = <512>;
125 cache-line-size = <128>;
[all …]
Dmeson8b.dtsi61 next-level-cache = <&L2>;
68 next-level-cache = <&L2>;
75 next-level-cache = <&L2>;
82 next-level-cache = <&L2>;
93 L2: l2-cache-controller@c4200000 {
94 compatible = "arm,pl310-cache";
96 cache-unified;
97 cache-level = <2>;
Duniphier-ph1-sld3.dtsi59 next-level-cache = <&l2>;
66 next-level-cache = <&l2>;
125 l2: l2-cache@500c0000 {
126 compatible = "socionext,uniphier-system-cache";
130 cache-unified;
131 cache-size = <(512 * 1024)>;
132 cache-sets = <256>;
133 cache-line-size = <128>;
134 cache-level = <2>;
Duniphier-ph1-pro4.dtsi59 next-level-cache = <&l2>;
66 next-level-cache = <&l2>;
103 l2: l2-cache@500c0000 {
104 compatible = "socionext,uniphier-system-cache";
108 cache-unified;
109 cache-size = <(768 * 1024)>;
110 cache-sets = <256>;
111 cache-line-size = <128>;
112 cache-level = <2>;
Dqcom-apq8084.dtsi22 next-level-cache = <&L2>;
33 next-level-cache = <&L2>;
44 next-level-cache = <&L2>;
55 next-level-cache = <&L2>;
61 L2: l2-cache {
62 compatible = "qcom,arch-cache";
63 cache-level = <2>;
Dbcm-nsp.dtsi56 next-level-cache = <&L2>;
61 L2: l2-cache {
62 compatible = "arm,pl310-cache";
64 cache-unified;
65 cache-level = <2>;
Duniphier-ph1-sld8.dtsi58 next-level-cache = <&l2>;
95 l2: l2-cache@500c0000 {
96 compatible = "socionext,uniphier-system-cache";
100 cache-unified;
101 cache-size = <(256 * 1024)>;
102 cache-sets = <256>;
103 cache-line-size = <128>;
104 cache-level = <2>;
Duniphier-ph1-ld4.dtsi58 next-level-cache = <&l2>;
95 l2: l2-cache@500c0000 {
96 compatible = "socionext,uniphier-system-cache";
100 cache-unified;
101 cache-size = <(512 * 1024)>;
102 cache-sets = <256>;
103 cache-line-size = <128>;
104 cache-level = <2>;
Dqcom-msm8660.dtsi23 next-level-cache = <&L2>;
31 next-level-cache = <&L2>;
34 L2: l2-cache {
35 compatible = "cache";
36 cache-level = <2>;
Dvexpress-v2p-ca5s.dts40 next-level-cache = <&L2>;
47 next-level-cache = <&L2>;
114 L2: cache-controller@2c0f0000 {
115 compatible = "arm,pl310-cache";
118 cache-level = <2>;
Dbcm4708.dtsi22 next-level-cache = <&L2>;
29 next-level-cache = <&L2>;
/linux-4.4.14/drivers/gpio/
Dgpio-mcp23s08.c70 u16 cache[11]; member
197 if ((n + reg) > sizeof(mcp->cache)) in mcp23s08_read_regs()
239 if ((n + reg) > sizeof(mcp->cache)) in mcp23s17_read_regs()
276 mcp->cache[MCP_IODIR] |= (1 << offset); in mcp23s08_direction_input()
277 status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]); in mcp23s08_direction_input()
294 mcp->cache[MCP_GPIO] = status; in mcp23s08_get()
303 unsigned olat = mcp->cache[MCP_OLAT]; in __mcp23s08_set()
309 mcp->cache[MCP_OLAT] = olat; in __mcp23s08_set()
333 mcp->cache[MCP_IODIR] &= ~mask; in mcp23s08_direction_output()
334 status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]); in mcp23s08_direction_output()
[all …]
/linux-4.4.14/arch/arm64/boot/dts/arm/
Djuno.dts68 next-level-cache = <&A57_L2>;
77 next-level-cache = <&A57_L2>;
86 next-level-cache = <&A53_L2>;
95 next-level-cache = <&A53_L2>;
104 next-level-cache = <&A53_L2>;
113 next-level-cache = <&A53_L2>;
118 compatible = "cache";
122 compatible = "cache";
Djuno-r1.dts68 next-level-cache = <&A57_L2>;
77 next-level-cache = <&A57_L2>;
86 next-level-cache = <&A53_L2>;
95 next-level-cache = <&A53_L2>;
104 next-level-cache = <&A53_L2>;
113 next-level-cache = <&A53_L2>;
118 compatible = "cache";
122 compatible = "cache";
Drtsm_ve-aemv8a.dts40 next-level-cache = <&L2_0>;
48 next-level-cache = <&L2_0>;
56 next-level-cache = <&L2_0>;
64 next-level-cache = <&L2_0>;
68 compatible = "cache";
Dfoundation-v8.dts37 next-level-cache = <&L2_0>;
45 next-level-cache = <&L2_0>;
53 next-level-cache = <&L2_0>;
61 next-level-cache = <&L2_0>;
65 compatible = "cache";
/linux-4.4.14/include/linux/
Dfscache-cache.h37 struct fscache_cache *cache; /* cache referred to by this tag */ member
222 struct fscache_object *(*alloc_object)(struct fscache_cache *cache,
260 void (*sync_cache)(struct fscache_cache *cache);
296 void (*dissociate_pages)(struct fscache_cache *cache);
366 struct fscache_cache *cache; /* cache that supplied this object */ member
404 return test_bit(FSCACHE_IOERROR, &object->cache->flags); in fscache_cache_is_broken()
420 static inline void fscache_object_destroyed(struct fscache_cache *cache) in fscache_object_destroyed() argument
422 if (atomic_dec_and_test(&cache->object_count)) in fscache_object_destroyed()
519 void fscache_init_cache(struct fscache_cache *cache,
523 extern int fscache_add_cache(struct fscache_cache *cache,
[all …]
Dkasan.h50 void kasan_unpoison_object_data(struct kmem_cache *cache, void *object);
51 void kasan_poison_object_data(struct kmem_cache *cache, void *object);
76 static inline void kasan_unpoison_object_data(struct kmem_cache *cache, in kasan_unpoison_object_data() argument
78 static inline void kasan_poison_object_data(struct kmem_cache *cache, in kasan_poison_object_data() argument
/linux-4.4.14/scripts/
Ddecode_stacktrace.sh13 declare -A cache
33 local base_addr=${cache[$name]}
36 cache["$name"]="$base_addr"
53 local code=${cache[$address]}
56 cache[$address]=$code
/linux-4.4.14/arch/s390/kernel/
Dcache.c70 struct cacheinfo *cache; in show_cacheinfo() local
78 cache = this_cpu_ci->info_list + idx; in show_cacheinfo()
80 seq_printf(m, "level=%d ", cache->level); in show_cacheinfo()
81 seq_printf(m, "type=%s ", cache_type_string[cache->type]); in show_cacheinfo()
83 cache->disable_sysfs ? "Shared" : "Private"); in show_cacheinfo()
84 seq_printf(m, "size=%dK ", cache->size >> 10); in show_cacheinfo()
85 seq_printf(m, "line_size=%u ", cache->coherency_line_size); in show_cacheinfo()
86 seq_printf(m, "associativity=%d", cache->ways_of_associativity); in show_cacheinfo()
/linux-4.4.14/drivers/acpi/apei/
Dghes.c528 struct ghes_estatus_cache *cache; in ghes_estatus_cached() local
534 cache = rcu_dereference(ghes_estatus_caches[i]); in ghes_estatus_cached()
535 if (cache == NULL) in ghes_estatus_cached()
537 if (len != cache->estatus_len) in ghes_estatus_cached()
539 cache_estatus = GHES_ESTATUS_FROM_CACHE(cache); in ghes_estatus_cached()
542 atomic_inc(&cache->count); in ghes_estatus_cached()
544 if (now - cache->time_in < GHES_ESTATUS_IN_CACHE_MAX_NSEC) in ghes_estatus_cached()
558 struct ghes_estatus_cache *cache; in ghes_estatus_cache_alloc() local
568 cache = (void *)gen_pool_alloc(ghes_estatus_pool, cache_len); in ghes_estatus_cache_alloc()
569 if (!cache) { in ghes_estatus_cache_alloc()
[all …]
/linux-4.4.14/arch/unicore32/mm/
DKconfig15 Say Y here to disable the processor instruction cache. Unless
21 Say Y here to disable the processor data cache. Unless
25 bool "Force write through D-cache"
27 Say Y here to use the data cache in writethrough mode. Unless you
31 bool "Disable D-cache line ops"
34 Say Y here to disable the data cache line operations.
/linux-4.4.14/drivers/md/bcache/
Dbcache.h380 struct cache { struct
484 struct cache *cache[MAX_CACHES_PER_SET]; member
485 struct cache *cache_by_alloc[MAX_CACHES_PER_SET];
715 static inline struct cache *PTR_CACHE(struct cache_set *c, in PTR_CACHE()
719 return c->cache[PTR_DEV(k, ptr)]; in PTR_CACHE()
800 for (iter = 0; ca = cs->cache[iter], iter < (cs)->sb.nr_in_set; iter++)
843 struct cache *ca; in wake_up_allocators()
852 void bch_count_io_errors(struct cache *, int, const char *);
862 uint8_t bch_inc_gen(struct cache *, struct bucket *);
865 bool bch_can_invalidate_bucket(struct cache *, struct bucket *);
[all …]
Dalloc.c74 uint8_t bch_inc_gen(struct cache *ca, struct bucket *b) in bch_inc_gen()
86 struct cache *ca; in bch_rescale_priorities()
129 bool bch_can_invalidate_bucket(struct cache *ca, struct bucket *b) in bch_can_invalidate_bucket()
139 void __bch_invalidate_one_bucket(struct cache *ca, struct bucket *b) in __bch_invalidate_one_bucket()
152 static void bch_invalidate_one_bucket(struct cache *ca, struct bucket *b) in bch_invalidate_one_bucket()
178 static void invalidate_buckets_lru(struct cache *ca) in invalidate_buckets_lru()
215 static void invalidate_buckets_fifo(struct cache *ca) in invalidate_buckets_fifo()
238 static void invalidate_buckets_random(struct cache *ca) in invalidate_buckets_random()
263 static void invalidate_buckets(struct cache *ca) in invalidate_buckets()
298 static int bch_allocator_push(struct cache *ca, long bucket) in bch_allocator_push()
[all …]
/linux-4.4.14/arch/metag/kernel/
Dcachepart.c58 static int get_thread_cache_size(unsigned int cache, int thread_id) in get_thread_cache_size() argument
64 isEnabled = (cache == DCACHE ? metag_in32(MMCU_DCACHE_CTRL_ADDR) & 0x1 : in get_thread_cache_size()
70 cache_size = (cache == DCACHE ? get_global_dcache_size() : in get_thread_cache_size()
74 cache_size = (cache == DCACHE ? get_dcache_size() : in get_thread_cache_size()
77 t_cache_part = (cache == DCACHE ? in get_thread_cache_size()
/linux-4.4.14/arch/mips/alchemy/common/
Dsleeper.S99 cache 0x14, 0(t0)
100 cache 0x14, 32(t0)
101 cache 0x14, 64(t0)
102 cache 0x14, 96(t0)
125 cache 0x14, 0(t0)
126 cache 0x14, 32(t0)
127 cache 0x14, 64(t0)
128 cache 0x14, 96(t0)
168 1: cache 0x14, 0(t0)
/linux-4.4.14/net/ipv6/
Dip6mr.c112 struct sk_buff *skb, struct mfc6_cache *cache);
346 struct list_head *cache; member
359 it->cache = &mrt->mfc6_cache_array[it->ct]; in ipmr_mfc_seq_idx()
360 list_for_each_entry(mfc, it->cache, list) in ipmr_mfc_seq_idx()
367 it->cache = &mrt->mfc6_unres_queue; in ipmr_mfc_seq_idx()
368 list_for_each_entry(mfc, it->cache, list) in ipmr_mfc_seq_idx()
373 it->cache = NULL; in ipmr_mfc_seq_idx()
514 if (mfc->list.next != it->cache) in ipmr_mfc_seq_next()
517 if (it->cache == &mrt->mfc6_unres_queue) in ipmr_mfc_seq_next()
520 BUG_ON(it->cache != &mrt->mfc6_cache_array[it->ct]); in ipmr_mfc_seq_next()
[all …]
/linux-4.4.14/arch/arm/boot/compressed/
Dhead.S622 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
623 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
651 mcr p15, 0, r0, c2, c0, 0 @ cache on
658 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
671 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
745 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
768 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
796 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
800 orr r0, r0, #0x1000 @ I-cache enable
815 .align 5 @ cache line aligned
[all …]
Dhead-xscale.S16 @ Data cache might be active.
17 @ Be sure to flush kernel binary out of the cache,
20 @ memory to be sure we hit the same cache.
/linux-4.4.14/mm/kasan/
Dkasan.c324 void kasan_unpoison_object_data(struct kmem_cache *cache, void *object) in kasan_unpoison_object_data() argument
326 kasan_unpoison_shadow(object, cache->object_size); in kasan_unpoison_object_data()
329 void kasan_poison_object_data(struct kmem_cache *cache, void *object) in kasan_poison_object_data() argument
332 round_up(cache->object_size, KASAN_SHADOW_SCALE_SIZE), in kasan_poison_object_data()
336 void kasan_slab_alloc(struct kmem_cache *cache, void *object) in kasan_slab_alloc() argument
338 kasan_kmalloc(cache, object, cache->object_size); in kasan_slab_alloc()
341 void kasan_slab_free(struct kmem_cache *cache, void *object) in kasan_slab_free() argument
343 unsigned long size = cache->object_size; in kasan_slab_free()
347 if (unlikely(cache->flags & SLAB_DESTROY_BY_RCU)) in kasan_slab_free()
353 void kasan_kmalloc(struct kmem_cache *cache, const void *object, size_t size) in kasan_kmalloc() argument
[all …]
/linux-4.4.14/arch/m32r/boot/
Dsetup.S67 ldi r1, #0x0101 ; cache on (with invalidation)
68 ; ldi r1, #0x00 ; cache off
73 ldi r1, #0x73 ; cache on (with invalidation)
74 ; ldi r1, #0x00 ; cache off
78 ldi r1, #0x101 ; cache on (with invalidation)
79 ; ldi r1, #0x00 ; cache off
93 ldi r1, #0x703 ; cache on (with invalidation)
/linux-4.4.14/net/ipv4/
Dipmr.c129 struct sk_buff *skb, struct mfc_cache *cache,
691 static void ipmr_update_thresholds(struct mr_table *mrt, struct mfc_cache *cache, in ipmr_update_thresholds() argument
696 cache->mfc_un.res.minvif = MAXVIFS; in ipmr_update_thresholds()
697 cache->mfc_un.res.maxvif = 0; in ipmr_update_thresholds()
698 memset(cache->mfc_un.res.ttls, 255, MAXVIFS); in ipmr_update_thresholds()
703 cache->mfc_un.res.ttls[vifi] = ttls[vifi]; in ipmr_update_thresholds()
704 if (cache->mfc_un.res.minvif > vifi) in ipmr_update_thresholds()
705 cache->mfc_un.res.minvif = vifi; in ipmr_update_thresholds()
706 if (cache->mfc_un.res.maxvif <= vifi) in ipmr_update_thresholds()
707 cache->mfc_un.res.maxvif = vifi + 1; in ipmr_update_thresholds()
[all …]
/linux-4.4.14/net/sunrpc/
Dauth.c399 rpcauth_clear_credcache(struct rpc_cred_cache *cache) in rpcauth_clear_credcache() argument
404 unsigned int hashsize = 1U << cache->hashbits; in rpcauth_clear_credcache()
408 spin_lock(&cache->lock); in rpcauth_clear_credcache()
410 head = &cache->hashtable[i]; in rpcauth_clear_credcache()
422 spin_unlock(&cache->lock); in rpcauth_clear_credcache()
433 struct rpc_cred_cache *cache = auth->au_credcache; in rpcauth_destroy_credcache() local
435 if (cache) { in rpcauth_destroy_credcache()
437 rpcauth_clear_credcache(cache); in rpcauth_destroy_credcache()
438 kfree(cache->hashtable); in rpcauth_destroy_credcache()
439 kfree(cache); in rpcauth_destroy_credcache()
[all …]
/linux-4.4.14/fs/ecryptfs/
Dmain.c663 struct kmem_cache **cache; member
669 .cache = &ecryptfs_auth_tok_list_item_cache,
674 .cache = &ecryptfs_file_info_cache,
679 .cache = &ecryptfs_dentry_info_cache,
684 .cache = &ecryptfs_inode_info_cache,
690 .cache = &ecryptfs_sb_info_cache,
695 .cache = &ecryptfs_header_cache,
700 .cache = &ecryptfs_xattr_cache,
705 .cache = &ecryptfs_key_record_cache,
710 .cache = &ecryptfs_key_sig_cache,
[all …]
/linux-4.4.14/net/irda/
Dirlmp_frame.c394 lap->cache.valid = FALSE; in irlmp_update_cache()
396 lap->cache.dlsap_sel = lsap->dlsap_sel; in irlmp_update_cache()
397 lap->cache.slsap_sel = lsap->slsap_sel; in irlmp_update_cache()
398 lap->cache.lsap = lsap; in irlmp_update_cache()
399 lap->cache.valid = TRUE; in irlmp_update_cache()
433 if ((self->cache.valid) && in irlmp_find_lsap()
434 (self->cache.slsap_sel == slsap_sel) && in irlmp_find_lsap()
435 (self->cache.dlsap_sel == dlsap_sel)) in irlmp_find_lsap()
437 return self->cache.lsap; in irlmp_find_lsap()
/linux-4.4.14/arch/mips/mm/
Dcex-sb1.S121 cache Index_Invalidate_I,(0<<13)(k0)
122 cache Index_Invalidate_I,(1<<13)(k0)
123 cache Index_Invalidate_I,(2<<13)(k0)
124 cache Index_Invalidate_I,(3<<13)(k0)
/linux-4.4.14/arch/powerpc/platforms/ps3/
Dspu.c125 struct priv1_cache cache; member
368 spu_pdata(spu)->cache.sr1 = 0x33; in ps3_create_spu()
498 spu_pdata(spu)->cache.masks[class] = mask; in int_mask_set()
500 spu_pdata(spu)->cache.masks[class]); in int_mask_set()
505 return spu_pdata(spu)->cache.masks[class]; in int_mask_get()
556 BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed)); in mfc_sr1_set()
558 spu_pdata(spu)->cache.sr1 = sr1; in mfc_sr1_set()
562 spu_pdata(spu)->cache.sr1); in mfc_sr1_set()
567 return spu_pdata(spu)->cache.sr1; in mfc_sr1_get()
572 spu_pdata(spu)->cache.tclass_id = tclass_id; in mfc_tclass_id_set()
[all …]
/linux-4.4.14/sound/soc/codecs/
Dwm_hubs.c156 struct wm_hubs_dcs_cache *cache; in wm_hubs_dcs_cache_get() local
165 list_for_each_entry(cache, &hubs->dcs_cache, list) { in wm_hubs_dcs_cache_get()
166 if (cache->left != left || cache->right != right) in wm_hubs_dcs_cache_get()
169 *entry = cache; in wm_hubs_dcs_cache_get()
179 struct wm_hubs_dcs_cache *cache; in wm_hubs_dcs_cache_set() local
184 cache = devm_kzalloc(codec->dev, sizeof(*cache), GFP_KERNEL); in wm_hubs_dcs_cache_set()
185 if (!cache) in wm_hubs_dcs_cache_set()
188 cache->left = snd_soc_read(codec, WM8993_LEFT_OUTPUT_VOLUME); in wm_hubs_dcs_cache_set()
189 cache->left &= WM8993_HPOUT1L_VOL_MASK; in wm_hubs_dcs_cache_set()
191 cache->right = snd_soc_read(codec, WM8993_RIGHT_OUTPUT_VOLUME); in wm_hubs_dcs_cache_set()
[all …]
Dwm9705.c210 u16 *cache = codec->reg_cache; in ac97_read() local
223 return cache[reg]; in ac97_read()
231 u16 *cache = codec->reg_cache; in ac97_write() local
236 cache[reg] = val; in ac97_write()
313 u16 *cache = codec->reg_cache; in wm9705_soc_resume() local
321 soc_ac97_ops->write(ac97, i, cache[i>>1]); in wm9705_soc_resume()
/linux-4.4.14/fs/afs/
Dfile.c144 ret = fscache_read_or_alloc_page(vnode->cache, in afs_page_filler()
182 fscache_uncache_page(vnode->cache, page); in afs_page_filler()
193 fscache_write_page(vnode->cache, page, GFP_KERNEL) != 0) { in afs_page_filler()
194 fscache_uncache_page(vnode->cache, page); in afs_page_filler()
260 ret = fscache_read_or_alloc_pages(vnode->cache, in afs_readpages()
326 fscache_wait_on_page_write(vnode->cache, page); in afs_invalidatepage()
327 fscache_uncache_page(vnode->cache, page); in afs_invalidatepage()
361 if (!fscache_maybe_release_page(vnode->cache, page, gfp_flags)) { in afs_releasepage()
DMakefile5 afs-cache-$(CONFIG_AFS_FSCACHE) := cache.o
8 $(afs-cache-y) \
/linux-4.4.14/arch/tile/kernel/
Dtlb.c57 int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0; in flush_tlb_page_mm() local
58 flush_remote(0, cache, mm_cpumask(mm), in flush_tlb_page_mm()
73 int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0; in flush_tlb_range() local
74 flush_remote(0, cache, mm_cpumask(mm), start, end - start, size, in flush_tlb_range()
/linux-4.4.14/arch/mips/include/asm/
Dr4kcache.h559 static inline void extra##blast_##pfx##cache##lsize(void) \
572 cache##lsize##_unroll32(addr|ws, indexop); \
577 static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \
585 cache##lsize##_unroll32(start, hitop); \
592 static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
606 cache##lsize##_unroll32(addr|ws, indexop); \
633 static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
641 cache##lsize##_unroll32_user(start, hitop); \
660 static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
687 static inline void protected_blast_##pfx##cache##_range(unsigned long start,\
/linux-4.4.14/fs/nfs/
Ddir.c2091 struct nfs_access_entry *cache; in nfs_access_free_list() local
2094 cache = list_entry(head->next, struct nfs_access_entry, lru); in nfs_access_free_list()
2095 list_del(&cache->lru); in nfs_access_free_list()
2096 nfs_access_free_entry(cache); in nfs_access_free_list()
2105 struct nfs_access_entry *cache; in nfs_do_access_cache_scan() local
2118 cache = list_entry(nfsi->access_cache_entry_lru.next, in nfs_do_access_cache_scan()
2120 list_move(&cache->lru, &head); in nfs_do_access_cache_scan()
2121 rb_erase(&cache->rb_node, &nfsi->access_cache); in nfs_do_access_cache_scan()
2229 struct nfs_access_entry *cache; in nfs_access_get_cached() local
2235 cache = nfs_access_search_rbtree(inode, cred); in nfs_access_get_cached()
[all …]
/linux-4.4.14/drivers/staging/lustre/lustre/llite/
Dxattr_cache.c76 static int ll_xattr_cache_find(struct list_head *cache, in ll_xattr_cache_find() argument
82 list_for_each_entry(entry, cache, xe_list) { in ll_xattr_cache_find()
106 static int ll_xattr_cache_add(struct list_head *cache, in ll_xattr_cache_add() argument
113 if (ll_xattr_cache_find(cache, xattr_name, &xattr) == 0) { in ll_xattr_cache_add()
135 list_add(&xattr->xe_list, cache); in ll_xattr_cache_add()
157 static int ll_xattr_cache_del(struct list_head *cache, in ll_xattr_cache_del() argument
164 if (ll_xattr_cache_find(cache, xattr_name, &xattr) == 0) { in ll_xattr_cache_del()
186 static int ll_xattr_cache_list(struct list_head *cache, in ll_xattr_cache_list() argument
193 list_for_each_entry_safe(xattr, tmp, cache, xe_list) { in ll_xattr_cache_list()
/linux-4.4.14/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-dt.txt34 next-level-cache = <&L2>;
50 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
62 next-level-cache = <&L2>;
Darm_big_little_dt.txt31 next-level-cache = <&L2>;
44 next-level-cache = <&L2>;
50 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
/linux-4.4.14/Documentation/block/
Dwriteback_cache_control.txt2 Explicit volatile write back cache control
17 a forced cache flush, and the Force Unit Access (FUA) flag for requests.
20 Explicit cache flushes
24 the filesystem and will make sure the volatile cache of the storage device
28 set on an otherwise empty bio structure, which causes only an explicit cache
30 the blkdev_issue_flush() helper for a pure cache flush.
45 worry if the underlying devices need any explicit cache flushing and how
57 drivers that do not have a volatile cache the REQ_FLUSH and REQ_FUA bits
/linux-4.4.14/lib/
Dtest_kasan.c281 struct kmem_cache *cache = kmem_cache_create("test_cache", in kmem_cache_oob() local
284 if (!cache) { in kmem_cache_oob()
289 p = kmem_cache_alloc(cache, GFP_KERNEL); in kmem_cache_oob()
292 kmem_cache_destroy(cache); in kmem_cache_oob()
297 kmem_cache_free(cache, p); in kmem_cache_oob()
298 kmem_cache_destroy(cache); in kmem_cache_oob()
/linux-4.4.14/drivers/staging/lustre/lustre/osc/
Dosc_page.c596 struct cl_client_cache *cache = cli->cl_cache; in osc_cache_too_much() local
606 if (atomic_read(cli->cl_lru_left) < cache->ccc_lru_max >> 4) { in osc_cache_too_much()
609 tmp = cache->ccc_lru_max / atomic_read(&cache->ccc_users); in osc_cache_too_much()
818 struct cl_client_cache *cache = cli->cl_cache; in osc_lru_reclaim() local
822 LASSERT(cache != NULL); in osc_lru_reclaim()
838 spin_lock(&cache->ccc_lru_lock); in osc_lru_reclaim()
839 LASSERT(!list_empty(&cache->ccc_lru)); in osc_lru_reclaim()
841 cache->ccc_lru_shrinkers++; in osc_lru_reclaim()
842 list_move_tail(&cli->cl_lru_osc, &cache->ccc_lru); in osc_lru_reclaim()
844 max_scans = atomic_read(&cache->ccc_users); in osc_lru_reclaim()
[all …]
/linux-4.4.14/drivers/hwmon/
Dapplesmc.c142 struct applesmc_entry *cache; /* cached key entries */ member
342 struct applesmc_entry *cache = &smcreg.cache[index]; in applesmc_get_entry_by_index() local
347 if (cache->valid) in applesmc_get_entry_by_index()
348 return cache; in applesmc_get_entry_by_index()
352 if (cache->valid) in applesmc_get_entry_by_index()
362 memcpy(cache->key, key, 4); in applesmc_get_entry_by_index()
363 cache->len = info[0]; in applesmc_get_entry_by_index()
364 memcpy(cache->type, &info[1], 4); in applesmc_get_entry_by_index()
365 cache->flags = info[5]; in applesmc_get_entry_by_index()
366 cache->valid = 1; in applesmc_get_entry_by_index()
[all …]
/linux-4.4.14/drivers/net/wireless/prism54/
Doid_mgt.c424 void *cache, *_data = data; in mgt_set_request() local
435 cache = priv->mib[n]; in mgt_set_request()
436 cache += (cache ? extra * dlen : 0); in mgt_set_request()
441 _data = cache; in mgt_set_request()
450 if (cache) in mgt_set_request()
462 } else if (!cache) in mgt_set_request()
465 if (cache) { in mgt_set_request()
467 memcpy(cache, _data, dlen); in mgt_set_request()
524 void *cache, *_res = NULL; in mgt_get_request() local
537 cache = priv->mib[n]; in mgt_get_request()
[all …]
/linux-4.4.14/drivers/macintosh/
Dwindfarm_smu_sat.c41 u8 cache[16]; member
131 err = i2c_smbus_read_i2c_block_data(sat->i2c, 0x3f, 16, sat->cache); in wf_sat_read_cache()
140 DBG(" %.2x", sat->cache[i]); in wf_sat_read_cache()
165 val = ((sat->cache[i] << 8) + sat->cache[i+1]) << sens->shift; in wf_sat_sensor_get()
169 val = (val * ((sat->cache[i] << 8) + sat->cache[i+1])) >> 4; in wf_sat_sensor_get()
/linux-4.4.14/Documentation/filesystems/
D9p.txt71 cache=mode specifies a caching policy. By default, no caches are used.
72 none = default no cache policy, metadata and data
77 cache backend.
78 mmap = minimal cache that is only used for read-write
79 mmap. Northing else is cached, like cache=none
132 cachetag cache tag to use the specified persistent cache.
133 cache tags for existing cache sessions can be listed at
134 /sys/fs/9p/caches. (applies only to cache=fscache)
/linux-4.4.14/Documentation/cris/
DREADME30 The ETRAX 100LX is a 100 MIPS processor with 8kB cache, MMU, and a very broad
61 I-cache and 16kB D-cache and with a wide range of device interfaces
93 Dentry-cache hash table entries: 2048 (order: 1, 16384 bytes)
94 Buffer-cache hash table entries: 2048 (order: 0, 8192 bytes)
95 Page-cache hash table entries: 2048 (order: 0, 8192 bytes)
98 Inode-cache hash table entries: 1024 (order: 0, 8192 bytes)
104 kmem_create: Forcing size word alignment - file lock cache
127 IP: routing cache hash table of 1024 buckets, 8Kbytes
151 cache size : 8 kB
/linux-4.4.14/drivers/gpu/drm/shmobile/
Dshmob_drm_crtc.c273 if (scrtc->cache) { in shmob_drm_crtc_stop()
274 sh_mobile_meram_cache_free(sdev->meram, scrtc->cache); in shmob_drm_crtc_stop()
275 scrtc->cache = NULL; in shmob_drm_crtc_stop()
325 if (scrtc->cache) in shmob_drm_crtc_compute_base()
326 sh_mobile_meram_cache_update(sdev->meram, scrtc->cache, in shmob_drm_crtc_compute_base()
384 void *cache; in shmob_drm_crtc_mode_set() local
400 if (scrtc->cache) { in shmob_drm_crtc_mode_set()
401 sh_mobile_meram_cache_free(sdev->meram, scrtc->cache); in shmob_drm_crtc_mode_set()
402 scrtc->cache = NULL; in shmob_drm_crtc_mode_set()
405 cache = sh_mobile_meram_cache_alloc(sdev->meram, mdata, in shmob_drm_crtc_mode_set()
[all …]
/linux-4.4.14/Documentation/xtensa/
Datomctl.txt11 The Core comes up with a default value of for the three types of cache ops:
21 For systems without an coherent cache controller, non-MX, we always
31 with the cache being bypassed; for example studying cache alias problems.
/linux-4.4.14/arch/m32r/boot/compressed/
Dhead.S77 ; Touch memory for the no-write-allocating cache.
138 ldi r1, 0xd0 ; invalidate i-cache, copy back d-cache
148 ldi r1, 0x0700 ; invalidate i-cache, copy back d-cache
/linux-4.4.14/fs/9p/
Dvfs_inode_dotl.c332 if ((v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) && in v9fs_vfs_atomic_open_dotl()
356 if (v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) in v9fs_vfs_atomic_open_dotl()
436 if (v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) { in v9fs_vfs_mkdir_dotl()
482 if (v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) { in v9fs_vfs_getattr_dotl()
712 if (v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) { in v9fs_vfs_symlink_dotl()
790 if (v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) { in v9fs_vfs_link_dotl()
868 if (v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) { in v9fs_vfs_mknod_dotl()
947 if (v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) in v9fs_refresh_inode_dotl()
Dvfs_super.c89 if (v9ses->cache) in v9fs_fill_super()
93 if (!v9ses->cache) in v9fs_fill_super()
143 if (v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) in v9fs_mount()
281 if (v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) in v9fs_drop_inode()
/linux-4.4.14/arch/arm/kvm/
Dtrace.h286 TP_PROTO(unsigned long vcpu_pc, bool cache),
287 TP_ARGS(vcpu_pc, cache),
291 __field( bool, cache )
296 __entry->cache = cache;
300 __entry->vcpu_pc, __entry->cache ? "on" : "off")
Dmmu.c125 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, in mmu_topup_memory_cache() argument
131 if (cache->nobjs >= min) in mmu_topup_memory_cache()
133 while (cache->nobjs < max) { in mmu_topup_memory_cache()
137 cache->objects[cache->nobjs++] = page; in mmu_topup_memory_cache()
833 static pud_t *stage2_get_pud(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, in stage2_get_pud() argument
841 if (!cache) in stage2_get_pud()
843 pud = mmu_memory_cache_alloc(cache); in stage2_get_pud()
851 static pmd_t *stage2_get_pmd(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, in stage2_get_pmd() argument
857 pud = stage2_get_pud(kvm, cache, addr); in stage2_get_pmd()
859 if (!cache) in stage2_get_pmd()
[all …]
/linux-4.4.14/arch/mn10300/include/asm/
Dmmu_context.h87 unsigned long mc = MMU_NO_CONTEXT, cache; in get_mmu_context() local
90 cache = mmu_context_cache[smp_processor_id()]; in get_mmu_context()
94 if ((mc ^ cache) & MMU_CONTEXT_VERSION_MASK) in get_mmu_context()
/linux-4.4.14/arch/x86/mm/
Dpat.c158 enum page_cache_mode cache; in pat_get_cache_mode() local
162 case PAT_UC: cache = CM(UC); cache_mode = "UC "; break; in pat_get_cache_mode()
163 case PAT_WC: cache = CM(WC); cache_mode = "WC "; break; in pat_get_cache_mode()
164 case PAT_WT: cache = CM(WT); cache_mode = "WT "; break; in pat_get_cache_mode()
165 case PAT_WP: cache = CM(WP); cache_mode = "WP "; break; in pat_get_cache_mode()
166 case PAT_WB: cache = CM(WB); cache_mode = "WB "; break; in pat_get_cache_mode()
167 case PAT_UC_MINUS: cache = CM(UC_MINUS); cache_mode = "UC- "; break; in pat_get_cache_mode()
168 default: cache = CM(WB); cache_mode = "WB "; break; in pat_get_cache_mode()
173 return cache; in pat_get_cache_mode()
185 enum page_cache_mode cache; in pat_init_cache_modes() local
[all …]
/linux-4.4.14/arch/mips/cavium-octeon/
DKconfig14 int "Number of L1 cache lines reserved for CVMSEG memory"
19 local memory; the larger CVMSEG is, the smaller the cache is.
20 This selects the size of CVMSEG LM, which is in cache blocks. The
21 legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
41 Enable locking parts of the kernel into the L2 cache.
/linux-4.4.14/arch/m32r/mm/
DMakefile6 obj-y := init.o fault.o mmu.o extable.o ioremap.o cache.o page.o
8 obj-y := init.o fault-nommu.o mmu.o extable.o ioremap-nommu.o cache.o page.o
/linux-4.4.14/drivers/crypto/marvell/
Dhash.c53 creq->cache = dma_pool_alloc(cesa_dev->dma->cache_pool, flags, in mv_cesa_ahash_dma_alloc_cache()
55 if (!creq->cache) in mv_cesa_ahash_dma_alloc_cache()
64 creq->cache = kzalloc(CESA_MAX_HASH_BLOCK_SIZE, flags); in mv_cesa_ahash_std_alloc_cache()
65 if (!creq->cache) in mv_cesa_ahash_std_alloc_cache()
78 if (creq->cache) in mv_cesa_ahash_alloc_cache()
91 dma_pool_free(cesa_dev->dma->cache_pool, creq->cache, in mv_cesa_ahash_dma_free_cache()
97 kfree(creq->cache); in mv_cesa_ahash_std_free_cache()
102 if (!creq->cache) in mv_cesa_ahash_free_cache()
110 creq->cache = NULL; in mv_cesa_ahash_free_cache()
213 creq->cache, creq->cache_ptr); in mv_cesa_ahash_std_step()
[all …]
/linux-4.4.14/arch/blackfin/mach-common/
DMakefile6 cache.o cache-c.o entry.o head.o \
/linux-4.4.14/arch/nios2/platform/
DKconfig.platform12 or cache bits set.
99 bool "Custom cache settings"
101 This option allows you to tweak the cache settings used during early
113 Maximum possible data cache size.
120 Minimum possible data cache line size.
127 Maximum possible instruction cache size.
/linux-4.4.14/tools/perf/tests/attr/
Dtest-record-group-sampling3 args = -e '{cycles,cache-misses}:S' kill >/dev/null 2>&1
16 # cache-misses
/linux-4.4.14/arch/powerpc/perf/
Dpower8-pmu.c287 unsigned int unit, pmc, cache, ebb; in power8_get_constraint() local
297 cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK; in power8_get_constraint()
337 if (cache & 0x7) in power8_get_constraint()
342 value |= CNST_L1_QUAL_VAL(cache); in power8_get_constraint()
405 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val; in power8_compute_mmcr() local
445 cache = event[i] >> EVENT_CACHE_SEL_SHIFT; in power8_compute_mmcr()
446 mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT; in power8_compute_mmcr()
447 cache >>= 1; in power8_compute_mmcr()
448 mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT; in power8_compute_mmcr()
/linux-4.4.14/Documentation/devicetree/bindings/opp/
Dopp.txt29 next-level-cache = <&L2>;
138 next-level-cache = <&L2>;
148 next-level-cache = <&L2>;
193 next-level-cache = <&L2>;
203 next-level-cache = <&L2>;
213 next-level-cache = <&L2>;
223 next-level-cache = <&L2>;
273 next-level-cache = <&L2>;
283 next-level-cache = <&L2>;
293 next-level-cache = <&L2>;
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/arc/
Darchs-pct.txt4 CPU and cache events like cache misses and hits. Like conventional PCT there
/linux-4.4.14/arch/mips/sgi-ip22/
DPlatform28 ifeq ($(call cc-option-yn,-mr10k-cache-barrier=store), n)
29 $(error gcc doesn't support needed option -mr10k-cache-barrier=store)
33 cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=store -I$(srctree)/arch/mips/include/asm/mach-ip28
/linux-4.4.14/drivers/usb/core/
Dquirks.c247 struct usb_interface_cache *cache; in usb_match_any_interface() local
250 cache = cfg->intf_cache[j]; in usb_match_any_interface()
251 if (cache->num_altsetting == 0) in usb_match_any_interface()
254 intf = &cache->altsetting[0]; in usb_match_any_interface()

12345