Lines Matching refs:cache
17 which has no memory control unit and cache.
50 A 32-bit RISC processor with 8KB cache or 4KB variants,
67 which has no memory control unit and cache.
140 instruction sequences for cache and TLB operations. Curiously,
159 Branch Target Buffer, Unified TLB and cache line size 16.
242 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
490 # The cache model
539 ARM Architecture Version 4 TLB with writethrough cache.
544 ARM Architecture Version 4 TLB with writeback cache.
549 ARM Architecture Version 4 TLB with writeback cache and invalidate
550 instruction cache entry.
560 Faraday ARM FA526 architecture, unified TLB with writeback cache
561 and invalidate instruction cache entry. Branch target buffer is
578 tag TLB and possibly cache entries.
752 Say Y here to disable the processor instruction cache. Unless
759 Say Y here to disable the processor data cache. Unless
768 Some cores are synthesizable to have various sized cache. For
770 To support such cache operations, it is efficient to know the size
776 bool "Force write through D-cache"
780 Say Y here to use the data cache in writethrough mode. Unless you
784 bool "Round robin I and D cache replacement algorithm"
787 Say Y here to use the predictable round-robin cache replacement
851 bool "Enable read/write for ownership DMA cache maintenance"
856 cache maintenance operations and the dma_{map,unmap}_area()
857 functions may leave stale cache entries on other CPUs. By
859 DMA cache maintenance functions is performed. These LDR/STR
860 instructions change the cache line state to shared or modified
861 so that the cache operation has the desired effect.
864 not perform speculative loads into the D-cache. For such
865 processors, if cache maintenance operations are not broadcast
866 in hardware, other workarounds are needed (e.g. cache
876 The outer cache has a outer_cache_fns.sync function pointer
877 that can be used to drain the write buffer of the outer cache.
880 bool "Enable the Feroceon L2 cache controller"
885 This option enables the Feroceon L2 cache controller.
888 bool "Force Feroceon L2 cache write through"
891 Say Y here to use the Feroceon L2 cache in writethrough mode.
898 or PL310 cache controller, but where its use is optional.
903 Boards or SoCs which always require the cache controller
909 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
921 The PL310 L2 cache controller implements three types of Clean &
933 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
942 bool "PL310 errata: cache sync operation may be faulty"
946 Under some condition the effect of cache sync operation on
950 is to replace the normal offset of cache sync operation (0x730)
952 This has the same effect as the cache sync operation: store buffer
963 on systems with an outer cache, the store buffer is drained
969 bool "Enable the Tauros2 L2 cache controller"
974 This option enables the Tauros2 L2 cache controller (as
978 bool "Enable the UniPhier outer cache controller"
984 This option enables the UniPhier outer cache (system cache)
988 bool "Enable the L2 cache on XScale3"
993 This option enables the L2 cache on XScale3.
999 Setting ARM L1 cache line size to 64 Bytes.