Lines Matching refs:cache
622 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
623 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
651 mcr p15, 0, r0, c2, c0, 0 @ cache on
658 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
671 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
745 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
768 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
796 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
800 orr r0, r0, #0x1000 @ I-cache enable
815 .align 5 @ cache line aligned
857 ARM( addeq pc, r12, r3 ) @ call cache function
859 THUMB( moveq pc, r12 ) @ call cache function
1048 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1058 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1060 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1067 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1069 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1081 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1111 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1121 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1129 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1130 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1147 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1159 mov r10, #0 @ start clean at cache level 0
1161 add r2, r10, r10, lsr #1 @ work out 3x current cache level
1162 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1163 and r1, r1, #7 @ mask of the bits for current cache only
1164 cmp r1, #2 @ see what cache we have at this level
1165 blt skip @ skip if no cache, or just i-cache
1166 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1169 and r2, r1, #7 @ extract the length of the cache lines
1179 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
1182 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
1191 add r10, r10, #2 @ increment cache number
1196 mov r10, #0 @ swith back to cache level 0
1197 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1208 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1210 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1219 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1220 teq r3, r9 @ cache ID register present?
1231 mov r11, r11, lsl r3 @ cache line size in bytes
1234 bic r1, r1, #63 @ align to longest cache line
1237 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1238 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1243 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1244 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1253 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3