Lines Matching refs:cache

2 # MN10300 CPU cache options
12 	  the affected cacheline to be read into the cache first before being
13 	  operated upon. Memory is not then updated by a write until the cache
14 	  is filled and a cacheline needs to be displaced from the cache to
19 	  cacheline is also in cache, it will be updated too.
35 	  cache.  This means that the written data is immediately available for
38 	  This is not available for use with an SMP kernel if cache flushing
53 	prompt "CPU cache flush/invalidate method"
58 	  This determines the method by which CPU cache flushing and
62 	bool "Use the cache tag registers directly"
104 # The kernel debugger gets its own separate cache flushing functions
113 	  icache using the cache tag registers to make breakpoints work.
130 	  Set if the debugger needs to invalidate the icache using the cache