Lines Matching refs:cache

3 ARM cores often have a separate level 2 cache controller. There are various
4 implementations of the L2 cache controller with compatible programming models.
5 Some of the properties that are just prefixed "cache-*" are taken from section
9 The ARM L2 cache representation in the device tree should be done as follows:
14   "arm,pl310-cache"
15   "arm,l220-cache"
16   "arm,l210-cache"
17   "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
18   "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
20      cache controller
21   "marvell,aurora-system-cache": Marvell Controller designed to be
22      compatible with the ARM one, with system cache mode (meaning
25   "marvell,aurora-outer-cache": Marvell Controller designed to be
26      compatible with the ARM one with outer cache mode.
27   "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
28      with arm,pl310-cache controller.
29 - cache-unified : Specifies the cache is a unified cache.
30 - cache-level : Should be set to 2 for a level 2 cache.
31 - reg : Physical base address and size of cache controller's memory mapped
48   I/O coherent mode. Valid only when the arm,pl310-cache compatible
51 - cache-size : specifies the size in bytes of the cache
52 - cache-sets : specifies the number of associativity sets of the cache
53 - cache-block-size : specifies the size in bytes of a cache block
54 - cache-line-size : specifies the size in bytes of a line in the cache,
56   cache block size
57 - cache-id-part: cache id part number to be used if it is not present
70 - arm,shared-override : The default behavior of the pl310 cache controller with
84 L2: cache-controller {
85         compatible = "arm,pl310-cache";
90         cache-unified;
91         cache-level = <2>;