Lines Matching refs:cache
6 This document describes the cache/tlb flushing interfaces called
16 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 "TLB" is abstracted under Linux as something the cpu uses to cache
26 possible for stale translations to exist in this "TLB" cache.
113 Next, we have the cache flushing interfaces. In general, when Linux
129 The cache level flush will always be first, because this allows
132 when that virtual address is flushed from the cache. The HyperSparc
135 The cache flushing routines below need only deal with cache flushing
149 the caches. That is, after running, there will be no cache
158 the caches. That is, after running, there will be no cache
171 addresses from the cache. After running, there will be no
172 entries in the cache for 'vma->vm_mm' for virtual addresses in
180 sized regions from the cache, instead of having the kernel
187 from the cache. The 'vma' is the backing structure used by
191 executable (and thus could be in the 'instruction cache' in
192 "Harvard" type cache layouts).
197 the cache.
199 After running, there will be no entries in the cache for
211 After running, there will be no entries in the cache for
221 of (kernel) virtual addresses from the cache. After running,
222 there will be no entries in the cache for the kernel address
229 There exists another whole class of cpu cache issues which currently
231 The biggest problem is that of virtual aliasing in the data cache
234 Is your port susceptible to virtual aliasing in its D-cache?
235 Well, if your D-cache is virtually indexed, is larger in size than
236 PAGE_SIZE, and does not prevent multiple cache lines for the same
239 If your D-cache has this problem, first define asm/shmparam.h SHMLBA
241 addressed D-cache (or if the size is variable, the largest possible
249 Next, you have to solve the D-cache aliasing issue for all
254 physical page into its address space, by implication the D-cache
262 pages. It allows a port to efficiently avoid D-cache alias
276 If D-cache aliasing is not an issue, these two routines may
281 Any time the kernel writes to a page cache page, _OR_
282 the kernel is about to read from a page cache page and
286 NOTE: This routine need only be called for page cache pages
289 handling vfs symlinks in the page cache need not call
292 The phrase "kernel writes to a page cache page" means,
296 D-cache aliasing, to make sure these kernel stores are
304 If D-cache aliasing is not an issue, this routine may
341 Any necessary cache flushing or other coherency operations
343 instruction cache does not snoop cpu stores, it is very
344 likely that you will need to flush the instruction cache
355 the cache of the page at vmaddr.
366 the kernel cache for page (using page_address(page)).
391 flushes the kernel cache for a given virtual address range in
399 the cache for a given virtual address range in the vmap area
400 which prevents the processor from making the cache stale by