Searched refs:SS (Results 1 - 142 of 142) sorted by relevance

/linux-4.4.14/drivers/net/wireless/brcm80211/brcmsmac/
H A Drate.c45 /* MCS 0: SS 1, MOD: BPSK, CR 1/2 */
48 /* MCS 1: SS 1, MOD: QPSK, CR 1/2 */
51 /* MCS 2: SS 1, MOD: QPSK, CR 3/4 */
54 /* MCS 3: SS 1, MOD: 16QAM, CR 1/2 */
57 /* MCS 4: SS 1, MOD: 16QAM, CR 3/4 */
60 /* MCS 5: SS 1, MOD: 64QAM, CR 2/3 */
63 /* MCS 6: SS 1, MOD: 64QAM, CR 3/4 */
66 /* MCS 7: SS 1, MOD: 64QAM, CR 5/6 */
69 /* MCS 8: SS 2, MOD: BPSK, CR 1/2 */
72 /* MCS 9: SS 2, MOD: QPSK, CR 1/2 */
75 /* MCS 10: SS 2, MOD: QPSK, CR 3/4 */
78 /* MCS 11: SS 2, MOD: 16QAM, CR 1/2 */
81 /* MCS 12: SS 2, MOD: 16QAM, CR 3/4 */
84 /* MCS 13: SS 2, MOD: 64QAM, CR 2/3 */
87 /* MCS 14: SS 2, MOD: 64QAM, CR 3/4 */
90 /* MCS 15: SS 2, MOD: 64QAM, CR 5/6 */
93 /* MCS 16: SS 3, MOD: BPSK, CR 1/2 */
96 /* MCS 17: SS 3, MOD: QPSK, CR 1/2 */
99 /* MCS 18: SS 3, MOD: QPSK, CR 3/4 */
102 /* MCS 19: SS 3, MOD: 16QAM, CR 1/2 */
105 /* MCS 20: SS 3, MOD: 16QAM, CR 3/4 */
108 /* MCS 21: SS 3, MOD: 64QAM, CR 2/3 */
111 /* MCS 22: SS 3, MOD: 64QAM, CR 3/4 */
114 /* MCS 23: SS 3, MOD: 64QAM, CR 5/6 */
117 /* MCS 24: SS 4, MOD: BPSK, CR 1/2 */
120 /* MCS 25: SS 4, MOD: QPSK, CR 1/2 */
123 /* MCS 26: SS 4, MOD: QPSK, CR 3/4 */
126 /* MCS 27: SS 4, MOD: 16QAM, CR 1/2 */
129 /* MCS 28: SS 4, MOD: 16QAM, CR 3/4 */
132 /* MCS 29: SS 4, MOD: 64QAM, CR 2/3 */
135 /* MCS 30: SS 4, MOD: 64QAM, CR 3/4 */
138 /* MCS 31: SS 4, MOD: 64QAM, CR 5/6 */
141 /* MCS 32: SS 1, MOD: BPSK, CR 1/2 */
/linux-4.4.14/tools/testing/selftests/x86/
H A Dsysret_ss_attrs.c2 * sysret_ss_attrs.c - test that syscalls return valid hidden SS attributes
14 * On AMD CPUs, SYSRET can return with a valid SS descriptor with with
35 * re-enter with SS = 0. threadproc()
81 printf("[RUN]\tSyscalls followed by SS validation\n"); main()
87 * SYSRET doesn't fix up the cached SS descriptor, so the main()
90 * can be a confusing failure because the SS *selector* main()
98 * to cause a crash if our cached SS descriptor is invalid. main()
H A Dsigreturn.c17 * For now, this focuses on the effects of unusual CS and SS values,
312 * SIGUSR1 handler. Sets CS and SS as requested and points IP to the
421 printf("[SKIP]\tCode segment unavailable for %d-bit CS, %d-bit SS\n", test_valid_sigreturn()
431 printf("[SKIP]\tData segment unavailable for %d-bit CS, 16-bit SS\n", test_valid_sigreturn()
443 printf("[RUN]\tValid sigreturn: %d-bit CS (%hx), %d-bit SS (%hx%s)\n", test_valid_sigreturn()
513 * nasty IRET case of returning to a 16-bit SS, test_valid_sigreturn()
539 printf("[RUN]\t%d-bit CS (%hx), bogus SS (%hx)\n", test_bad_iret()
568 strcpy(trapname, "SS"); test_bad_iret()
603 /* Easy cases: return to a 32-bit SS in each possible CS bitness. */ main()
609 * Test easy espfix cases: return to a 16-bit LDT SS in each possible main()
610 * CS bitness. NB: with a long mode CS, the SS bitness is irrelevant. main()
621 * For performance reasons, Linux skips espfix if SS points main()
622 * to the GDT. If we were able to allocate a 16-bit SS in main()
648 /* Easy failures: invalid SS, resulting in #GP(0) */ main()
653 /* These fail because SS isn't a data segment, resulting in #GP(SS) */ main()
658 /* Try to return to a not-present code segment, triggering #NP(SS). */ main()
663 * This will cause IRET to fail with #SS on the espfix stack. This main()
/linux-4.4.14/tools/perf/arch/x86/util/
H A Dperf_regs.c16 SMPL_REG(SS, PERF_REG_X86_SS),
/linux-4.4.14/tools/perf/arch/x86/tests/
H A Dregs_load.S14 #define SS 11 * 8 define
47 movq $0, SS(%rdi)
84 movl $0, SS(%edi)
/linux-4.4.14/arch/x86/include/uapi/asm/
H A Dptrace-abi.h22 #define SS 16 macro
58 #define SS 160 macro
/linux-4.4.14/arch/x86/um/os-Linux/
H A Dmcontext.c17 COPY(EIP); COPY_SEG_CPL3(CS); COPY(EFL); COPY_SEG_CPL3(SS); get_regs_from_mc()
/linux-4.4.14/arch/s390/include/uapi/asm/
H A Dhypfs.h42 char time[8]; /* HH:MM:SS in EBCDIC */
/linux-4.4.14/arch/x86/um/
H A Duser-offsets.c48 DEFINE(HOST_SS, SS); foo()
73 DEFINE_LONGS(HOST_SS, SS); foo()
H A Dptrace_32.c70 [SS] = HOST_SS,
101 case SS: putreg()
152 case SS: getreg()
H A Dptrace_64.c42 [SS >> 3] = HOST_SS,
88 case SS: putreg()
167 case SS: getreg()
H A Dsignal.c198 GETREG(SS, ss); copy_sc_from_user()
290 PUTREG(SS, ss); copy_sc_to_user()
/linux-4.4.14/drivers/crypto/sunxi-ss/
H A Dsun4i-ss.h69 /* SS operation mode - bits 12-13 */
88 /* SS Method - bits 4-6 */
102 /* SS Enable bit - bit 0 */
H A Dsun4i-ss-core.c6 * Core file which registers crypto algorithms supported by the SS.
246 dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err); sun4i_ss_probe()
254 dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err); sun4i_ss_probe()
326 * Since the A80 seems to have an other version of SS sun4i_ss_probe()
H A Dsun4i-ss-hash.c136 * Write data by step of 32bits and put then in the SS.
142 * So the first work is to get the number of bytes to write to SS modulo 64
335 * Then ask the SS for finalizing the hashing operation
426 /* Tell the SS to stop the hashing */ sun4i_hash_final()
430 * Wait for SS to finish the hash. sun4i_hash_final()
H A Dsun4i-ss-cipher.c27 /* when activating SS, the default FIFO space is SS_RX_DEFAULT(32) */ sun4i_ss_opti_poll()
137 /* when activating SS, the default FIFO space is SS_RX_DEFAULT(32) */ sun4i_ss_cipher_poll()
170 * we can use the SS optimized function sun4i_ss_cipher_poll()
/linux-4.4.14/drivers/staging/rtl8723au/include/
H A Dieee80211.h86 RATR_INX_WIRELESS_NGB = 0, /* BGN 40 Mhz 2SS 1SS */
88 RATR_INX_WIRELESS_NB = 2, /* BGN 20 Mhz 2SS 1SS or BN */
/linux-4.4.14/drivers/usb/atm/
H A Dcxacru.c115 * layout: PP PP VV VV MM MM MM MM MM MM ?? ?? SS SS SS SS SS SS SS SS
116 * SS SS SS SS SS SS SS SS 00 00 00 00 00 00 00 00 00 00 00 00
/linux-4.4.14/tools/perf/arch/x86/include/
H A Dperf_regs.h52 return "SS"; perf_reg_name()
/linux-4.4.14/arch/x86/kernel/
H A Dprocess_64.c322 * Note that we don't need to do anything for CS and SS, as __switch_to()
428 * AMD CPUs have a misfeature: SYSRET sets the SS selector but __switch_to()
430 * do SYSRET while SS is NULL, we'll end up in user mode with __switch_to()
431 * SS apparently equal to __USER_DS but actually unusable. __switch_to()
435 * fast paths. Instead, we ensure that SS is never NULL in __switch_to()
436 * system call context. We do this by replacing NULL SS __switch_to()
438 * SS, so the only way to get NULL is to re-enter the kernel __switch_to()
444 * We read SS first because SS reads are much faster than __switch_to()
445 * writes. Out of caution, we force SS to __KERNEL_DS even if __switch_to()
H A Dmcount_64.S39 #define MCOUNT_REG_SIZE (SS+8 + MCOUNT_FRAME_SIZE)
212 movq %rcx, SS(%rsp)
225 /* Copy flags back to SS, to restore them */
H A Ddumpstack.c291 printk(" SS:ESP %04x:%08lx\n", ss, sp); __die()
H A Despfix_64.c23 * is mapped 2^16 times 64K apart. When we detect that the return SS is
H A Dprocess_32.c95 printk(KERN_DEFAULT " DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n", __show_regs()
H A Dvm86_32.c607 case 0x36: /* SS */ break; handle_vm86_fault()
H A Dapm_32.c521 * are interrupts disabled, but all the segment registers (except SS)
/linux-4.4.14/drivers/usb/gadget/udc/
H A Dnet2280.h228 * - Tip: Upon the first SS Control Read the FSM never
233 /* Non-SS Control Read:
236 * - Tip: Upon the first SS Control Read the FSM never
241 /* SS Control Read:
243 * first SS Control Read.
H A Dfusb300_udc.h190 * * SS Controller Register 0 (offset = 308H)
197 * * SS Controller Register 1 (offset = 30CH)
210 * *SS Controller Register 2 (offset = 310H)
219 * *SS Device Notification Control (DEV_NOTF, offset = 314H)
H A Dnet2280.c1957 ep_warn(dev, "It will operate on cold-reboot and SS connect"); defect7374_enable_data_eps_zero()
2236 * - On SS connections, setting Recovery Idle to Recover Fmw improves usb_reinit_338x()
2713 * Connection is NOT SS: defect7374_workaround()
2723 /* Connection is SS: */ defect7374_workaround()
2749 "to detect SS host's data phase ACK."); defect7374_workaround()
2884 * Workaround for SS SeqNum not cleared via handle_stat0_irqs_superspeed()
H A Ddummy_hcd.c504 * For SS devices the wMaxPacketSize is limited by 1024. dummy_enable()
/linux-4.4.14/drivers/usb/dwc3/
H A Ddebug.h103 return "SS.Disabled"; dwc3_gadget_link_string()
107 return "SS.Inactive"; dwc3_gadget_link_string()
H A Ddebugfs.c538 seq_printf(s, "SS.Disabled\n"); dwc3_link_state_show()
544 seq_printf(s, "SS.Inactive\n"); dwc3_link_state_show()
591 if (!strncmp(buf, "SS.Disabled", 11)) dwc3_link_state_write()
595 else if (!strncmp(buf, "SS.Inactive", 11)) dwc3_link_state_write()
H A Dgadget.c2304 * We change the clock only at SS but I dunno why I would want to do dwc3_update_ram_clk_sel()
2348 * STAR#9000483510: RTL: SS : USB3 reset event may dwc3_gadget_conndone_interrupt()
2464 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation dwc3_gadget_linksts_change_interrupt()
2493 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us dwc3_gadget_linksts_change_interrupt()
H A Dcore.h716 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
H A Dep0.c423 * 9.4.1 says only only for SS, in AddressState only for dwc3_ep0_handle_feature()
/linux-4.4.14/drivers/mfd/
H A Dmc13xxx-spi.c113 * "The CSPI negates SS when the FIFO becomes empty with
117 * result, the SS will negate before all of the data has been
/linux-4.4.14/arch/x86/include/asm/xen/
H A Dinterface_64.h69 * Discard R11, RCX, CS, SS.
71 * Restore RAX, R11, RCX, CS:RIP, RFLAGS, SS:RSP.
/linux-4.4.14/arch/x86/boot/compressed/
H A Defi_stub_32.S29 * set to 0x0010, DS and SS have been set to 0x0018. In EFI, I found
/linux-4.4.14/arch/arm/mach-omap2/
H A Domap24xx.h62 /* DSP SS */
H A Dopp.c75 * the MPU-SS. omap_init_opp_table()
H A Dpm.c148 * source, so CPU0 is used to represent the MPU-SS. omap2_set_init_voltage()
H A Domap_hwmod.c3257 * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up
/linux-4.4.14/arch/arm64/kvm/
H A Ddebug.c132 * the guest's MDSCR_EL1.SS and PSTATE.SS. Once the kvm_arm_setup_debug()
140 * do so by masking MDSCR_EL.SS. kvm_arm_setup_debug()
/linux-4.4.14/arch/x86/entry/
H A Dentry_64.S13 * - iret frame: Architecture defined interrupt frame from SS to RIP
222 * avoid SYSRET with SS == NULL, which could happen if we schedule,
224 * interrupt entries on x86_64 set SS to NULL.) We prevent that
225 * from happening by reloading SS in __switch_to. (Actually
340 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
606 * 64-bit mode SS:RSP on the exception stack is always valid.
609 testb $4, (SS-RIP)(%rsp)
617 * handled by fixup_bad_iret. These include #SS, #GP, and #NP.
636 movq (6*8)(%rsp), %rax /* SS */
1258 * | original SS |
1268 * | iret SS } Copied from "outermost" frame |
1274 * | outermost SS } initialized in first_nmi; |
1397 pushq $0 /* SS */
H A Dcalling.h87 #define SS 20*8 macro
H A Dentry_64_compat.S228 * SS = __USER_DS
H A Dentry_32.S362 movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS
372 je ldt_ss # returning to user-space with LDT SS
778 * i386 does not save SS and ESP when coming from kernel.
/linux-4.4.14/drivers/power/
H A Dbq24190_charger.c342 /* On i386 ptrace-abi.h defines SS that breaks the macro calls below. */
343 #undef SS macro
374 BQ24190_SYSFS_FIELD_RO(vbus_stat, SS, VBUS_STAT),
375 BQ24190_SYSFS_FIELD_RO(chrg_stat, SS, CHRG_STAT),
376 BQ24190_SYSFS_FIELD_RO(dpm_stat, SS, DPM_STAT),
377 BQ24190_SYSFS_FIELD_RO(pg_stat, SS, PG_STAT),
378 BQ24190_SYSFS_FIELD_RO(therm_stat, SS, THERM_STAT),
379 BQ24190_SYSFS_FIELD_RO(vsys_stat, SS, VSYS_STAT),
1208 dev_err(bdi->dev, "Can't read SS reg: %d\n", ret); bq24190_irq_handler_thread()
/linux-4.4.14/arch/x86/platform/efi/
H A Defi_stub_32.S27 * set to 0x0010, DS and SS have been set to 0x0018. In EFI, I found
/linux-4.4.14/arch/m68k/sun3/prom/
H A Dconsole.c159 /* This works on SS-2 (an early OpenFirmware) still. */
/linux-4.4.14/drivers/bus/
H A Domap_l3_smx.h149 /* IVA2.2 SS has 3 IDs*/
153 /* IVA 2.2 SS DMA has 6 IDS */
/linux-4.4.14/drivers/usb/gadget/udc/bdc/
H A Dbdc_udc.c93 /* Enable U1T in SS mode */ bdc_uspc_connected()
275 * In SS we might not have PRC bit set before connection, but in 2.0 bdc_sr_uspc()
277 * of bus reset to handle both SS/2.0 speeds. bdc_sr_uspc()
H A Dbdc.h45 /* Start with SS as default */
H A Dbdc_ep.c1067 * Setup packet received, just store the packet and process on next DS or SS
/linux-4.4.14/drivers/memory/
H A Dti-aemif.c42 #define SS(x) ((x) << SS_SHIFT) macro
64 #define SS_VAL(x) (((x) & SS(SS_MAX)) >> SS_SHIFT)
82 EW(EW_MAX) | SS(SS_MAX) | \
/linux-4.4.14/drivers/usb/misc/
H A Dlvstest.c375 /* valid only for SS root hub */ lvs_rh_probe()
377 dev_err(&intf->dev, "Bind LVS driver with SS root Hub only\n"); lvs_rh_probe()
/linux-4.4.14/arch/x86/include/asm/
H A Dthread_info.h26 * we can read the saved SS value, but that value will be above sp0.
270 * return path, which is able to restore modified SS, CS and certain
H A Dsegment.h82 * 26 - ESPFIX small SS
H A Dkvm_emulate.h291 /* interruptibility state, as a result of execution of STI or MOV SS */
H A Dcpufeature.h275 #define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */
H A Dprocessor.h719 * is accessible even if the CPU haven't stored the SS/ESP registers
/linux-4.4.14/drivers/ata/
H A Data_piix.c359 /* PM PS SM SS MAP */
375 /* PM PS SM SS MAP */
392 /* PM PS SM SS MAP */
404 /* PM PS SM SS MAP */
416 /* PM PS SM SS MAP */
428 /* PM PS SM SS MAP */
440 /* PM PS SM SS MAP */
/linux-4.4.14/drivers/staging/rtl8188eu/hal/
H A DHal8188ERateAdaptive.c50 {4, 4, 4, 5, 4, 4, 5, 7, 7, 7, 8, 0x0a, /* SS>TH */
54 0x0a, 0x0b, 0x0c, 0x0d, 0x10, 0x13, 0x14, /* SS<TH */
61 0x0f, 0x0f, 0x10, 0x12, 0x13, 0x14, /* SS>TH */
H A Dusb_halinit.c833 /* Move by Neo for USB SS to below setp */ rtl8188eu_hal_init()
/linux-4.4.14/drivers/phy/
H A Dphy-exynos5-usbdrd.c159 * reference clocks' for SS and HS operations
382 /* This bit must be set for both HS and SS operations */ exynos5_usbdrd_phy_init()
395 /* Enable ref clock for SS function */ exynos5_usbdrd_phy_init()
/linux-4.4.14/drivers/net/wireless/iwlwifi/mvm/
H A Dfw-api-rs.h258 /* Bit 17-18: (0) SS, (1) SS*2 */
H A Drs.c1961 * supports STBC of at least 1*SS rs_stbc_allow()
/linux-4.4.14/drivers/staging/rtl8188eu/include/
H A Dieee80211.h150 RATR_INX_WIRELESS_NGB = 0, /* BGN 40 Mhz 2SS 1SS */
152 RATR_INX_WIRELESS_NB = 2, /* BGN 20 Mhz 2SS 1SS or BN */
/linux-4.4.14/drivers/rtc/
H A Drtc-sysfs.c137 * exact YYYY-MM-DD HH:MM[:SS] date *must* disable their RTC wakealarm_show()
H A Drtc-sun6i.c304 * After writing the RTC HH-MM-SS register, the sun6i_rtc_settime()
H A Drtc-sunxi.c382 * After writing the RTC HH-MM-SS register, the sunxi_rtc_settime()
/linux-4.4.14/drivers/staging/fbtft/
H A Dfb_ili9320.c65 /* set SS and SM bit */ init_display()
H A Dfb_ili9325.c115 write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ init_display()
/linux-4.4.14/drivers/input/serio/
H A Dps2mult.c266 dev_dbg(&serio->dev, "SS\n"); ps2mult_interrupt()
/linux-4.4.14/arch/x86/math-emu/
H A Dget_address.c204 SS INDEX BASE
/linux-4.4.14/arch/x86/tools/
H A Dgen-insn-attr-x86.awk94 prefix_num["SEG=SS"] = "INAT_PFX_SS"
/linux-4.4.14/sound/isa/ad1816a/
H A Dad1816a.c171 sprintf(card->longname, "%s, SS at 0x%lx, irq %d, dma %d&%d", snd_card_ad1816a_probe()
/linux-4.4.14/tools/perf/util/intel-pt-decoder/
H A Dgen-insn-attr-x86.awk94 prefix_num["SEG=SS"] = "INAT_PFX_SS"
/linux-4.4.14/drivers/gpu/drm/amd/include/
H A Datombios.h1940 /****************************LVDS SS Command Table Definitions**********************/
1966 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
2435 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
2438 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
2514 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
2515 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
3765 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD
3774 #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.
3775 #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.
3776 #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz
3777 #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz
5852 // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
5853 //Memory SS Info Table
5854 //Define Memory Clock SS chip ID
5858 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
5866 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
5870 UCHAR ucSSChipID; //SS chip being used
5871 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
5894 UCHAR ucClockIndication; //Indicate which clock source needs SS
5899 //Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type.
5900 //SS is not required or enabled if a match is not found.
5920 UCHAR ucClockIndication; //Indicate which clock source needs SS
5921 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
5951 UCHAR ucClockIndication; //Indicate which clock source needs SS
5952 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
7833 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
7834 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
7845 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
7846 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Datombios.h1897 /****************************LVDS SS Command Table Definitions**********************/
1923 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
2367 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
2370 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
2443 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
2444 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
3643 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD
3652 #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.
3653 #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.
3654 #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz
3655 #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz
5433 // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
5434 //Memory SS Info Table
5435 //Define Memory Clock SS chip ID
5439 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
5447 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
5451 UCHAR ucSSChipID; //SS chip being used
5452 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
5475 UCHAR ucClockIndication; //Indicate which clock source needs SS
5480 //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type.
5481 //SS is not required or enabled if a match is not found.
5501 UCHAR ucClockIndication; //Indicate which clock source needs SS
5502 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
5532 UCHAR ucClockIndication; //Indicate which clock source needs SS
5533 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
7313 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
7314 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
H A Datombios_crtc.c449 /* Don't mess with SS if percentage is 0 or external ss. atombios_crtc_program_ss()
450 * SS is already disabled previously, and disabling it atombios_crtc_program_ss()
/linux-4.4.14/drivers/usb/gadget/function/
H A Df_uvc.c501 * uvc_ss_control_comp (for SS only) uvc_copy_descriptors()
597 /* Fill in the FS/HS/SS Video Streaming specific descriptors from the uvc_function_bind()
H A Df_sourcesink.c429 * Fill in the SS isoc descriptors from the module parameters. sourcesink_bind()
H A Df_fs.c1808 pr_vdebug("EP SS companion descriptor\n"); ffs_do_single_desc()
/linux-4.4.14/drivers/gpu/drm/bridge/
H A Dparade-ps8622.c117 /* RCO SS setting: [5:4] = b01 0.5%, b10 1%, b11 1.5% */ ps8622_send_config()
122 /* [7] RCO SS enable */ ps8622_send_config()
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A Datombios_crtc.c251 /* Don't mess with SS if percentage is 0 or external ss. amdgpu_atombios_crtc_program_ss()
252 * SS is already disabled previously, and disabling it amdgpu_atombios_crtc_program_ss()
/linux-4.4.14/arch/arm64/kernel/
H A Ddebug-monitors.c388 * If single step is active for this thread, then set SPSR.SS user_rewind_single_step()
H A Dentry.S91 get_thread_info tsk // Ensure MDSCR_EL1.SS is clear,
/linux-4.4.14/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-dev.c677 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x3) xgbe_set_gmii_speed()
680 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3); xgbe_set_gmii_speed()
687 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x2) xgbe_set_gmii_2500_speed()
690 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2); xgbe_set_gmii_2500_speed()
697 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0) xgbe_set_xgmii_speed()
700 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0); xgbe_set_xgmii_speed()
/linux-4.4.14/drivers/staging/rtl8723au/hal/
H A Drtl8723a_hal_init.c1254 for SS mode. */ _DisableRFAFEAndResetBB8192C()
1293 /* 2010/08/12 MH For USB SS, we can not stop 8051 when we _ResetDigitalProcedure1_92C()
1297 /* If we want to SS mode, we can not reset 8051. */ _ResetDigitalProcedure1_92C()
H A Dusb_halinit.c681 /* Move by Neo for USB SS from above setp */ rtl8723au_hal_init()
821 RT_TRACE(_module_hal_init_c_, _drv_err_, "SS LVL1\n"); phy_SsPwrSwitch92CU()
/linux-4.4.14/drivers/iommu/
H A Dmsm_iommu_hw-8xxx.h482 #define SET_SS(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SS, v)
670 #define GET_SS(b, c) GET_CONTEXT_FIELD(b, c, FSR, SS)
1039 #define SS (SS_MASK << SS_SHIFT) macro
H A Dmsm_iommu.c623 (fsr & 0x40000000) ? "SS " : "", print_ctx_regs()
/linux-4.4.14/drivers/spi/
H A Dspi-mpc512x-psc.c438 0x00000800; /* UseEOF = 1 -- SS low until EOF */ mpc512x_psc_spi_port_config()
H A Dspi-mpc52xx.c400 out_8(regs + SPI_PORTDATA, 0x8); /* Deassert /SS signal */ mpc52xx_spi_probe()
H A Dspi-cadence.c54 #define CDNS_SPI_CR_SSFORCE_MASK 0x00004000 /* Manual SS Enable Mask */
/linux-4.4.14/drivers/net/wireless/iwlwifi/
H A Diwl-config.h183 * @stbc: support Tx STBC and 1*SS Rx STBC
/linux-4.4.14/drivers/acpi/acpica/
H A Dutids.c433 * SS = Sub-class code
/linux-4.4.14/tools/usb/
H A Dffs-test.c225 * Find the end of FS and HS USB descriptors. SS descriptors descs_to_legacy()
/linux-4.4.14/drivers/usb/storage/
H A Drealtek_cr.c780 usb_stor_dbg(us, "Ready to enter SS state\n"); rts51x_suspend_timer_fn()
860 usb_stor_dbg(us, "NOT working scsi, not SS\n"); rts51x_invoke_transport()
/linux-4.4.14/drivers/media/common/
H A Dcx2341x.c1044 2, /* MPEG-1 SS */ cx2341x_update()
1344 2, /* MPEG-1 SS */ cx2341x_s_ctrl()
/linux-4.4.14/arch/sparc/kernel/
H A Dhead_32.S38 /* Tested on SS-5, SS-10 */
H A Dioport.c89 #define XNRES 10 /* SS-10 uses 8 */
/linux-4.4.14/drivers/net/ethernet/ti/
H A Dnetcp_ethss.c39 /* 1G Ethernet SS defines */
58 /* 1G Ethernet NU SS defines */
82 /* 10G Ethernet SS defines */
393 * are for SS version NU and some are for 2U.
2079 /* Enable correct MII mode at SS level */ gbe_port_config()
/linux-4.4.14/drivers/regulator/
H A Dqcom_rpm-regulator.c48 struct request_member hpm; /* switch: control OCP and SS */
/linux-4.4.14/drivers/net/caif/
H A Dcaif_spi.c461 printk(KERN_WARNING "CFSPI: Spurious SS interrupt.\n"); cfspi_ss_cb()
/linux-4.4.14/drivers/net/fddi/skfp/h/
H A Dcmtdef.h149 #define POLICY_SS (1<<10) /* reject SS */
/linux-4.4.14/arch/x86/kernel/cpu/
H A Damd.c762 /* AMD CPUs don't reset SS attributes on SYSRET */ init_amd()
H A Dperf_event.c2346 * X86_64 - CS,DS,SS,ES are all zero based.
/linux-4.4.14/arch/x86/kvm/
H A Dtrace.h270 EXS(DF), EXS(TS), EXS(NP), EXS(SS), EXS(GP), EXS(PF), \
H A Dvmx.c947 VMX_SEGMENT_FIELD(SS),
3419 * CS and SS RPL should be equal during guest entry according fix_pmode_seg()
5174 * Cause the #SS fault with 0 error code in VM86 mode. handle_rmode_exception()
6580 /* Checks for #GP/#SS exceptions. */ get_vmx_mem_address()
6586 * - usability check (#GP(0)/#SS(0)) get_vmx_mem_address()
6587 * - limit check (#GP(0)/#SS(0)) get_vmx_mem_address()
6605 /* Long mode: #GP(0)/#SS(0) if the memory address is in a get_vmx_mem_address()
6610 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable. get_vmx_mem_address()
6613 /* Protected mode: #GP(0)/#SS(0) if the memory get_vmx_mem_address()
7969 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); dump_vmcs()
7999 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", dump_vmcs()
8562 /* When single-stepping over STI and MOV SS, we must clear the vmx_vcpu_run()
H A Dsvm.c226 VMCB_SEG, /* CS, DS, SS, ES, CPL */
1271 * Any change of EFLAGS.VM is accompained by a reload of SS svm_set_rflags()
1548 * with SS.DPL != 3. Intel does not have this quirk, and always svm_set_segment()
1549 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it svm_set_segment()
H A Demulate.c58 #define OpSS 22ull /* SS */
1572 /* NULL selector is not valid for TR, CS and SS (except for long mode) */ __load_segment_descriptor()
4838 case 0x36: /* SS override */ x86_decode_insn()
/linux-4.4.14/arch/x86/xen/
H A Dsmp.c447 * bit set. This means before DS/SS is touched, NX in cpu_initialize_context()
/linux-4.4.14/drivers/block/
H A Dswim.c568 { 720, 9, 1, 80, 0, 0x2A, 0x02, 0xDF, 0x50, NULL }, /* 360KB SS 3.5"*/
H A Dfloppy.c452 { 720, 9,1,80,0,0x2A,0x02,0xDF,0x50,"D360" }, /* 3 360KB SS 3.5" */
/linux-4.4.14/sound/pci/cs46xx/
H A Dcs46xx_dsp_scb_types.h49 |S| SBT |D| DBT |wb|wb| | | LS | SS |Opt|Do|SSG|DSG| | | | | | | Dword |
/linux-4.4.14/sound/pci/echoaudio/
H A Dechoaudio_dsp.h403 * data. "SS" means stereo->stereo.
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dhw.c1040 /* ARFB table 9 for 11ac 5G 2SS */ _rtl8821ae_hw_configure()
1042 /* ARFB table 10 for 11ac 5G 1SS */ _rtl8821ae_hw_configure()
1044 /* ARFB table 11 for 11ac 24G 1SS */ _rtl8821ae_hw_configure()
1047 /* ARFB table 12 for 11ac 24G 1SS */ _rtl8821ae_hw_configure()
3576 if (ratr_bitmap & 0xfff00000) /* Mix , 2SS */ _rtl8821ae_get_vht_eni()
3578 else /* Mix, 1SS */ _rtl8821ae_get_vht_eni()
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbtc8192e2ant.c1357 "[BTCoex], REAL set SS Type = %d\n", sstype); halbtc8192e2ant_set_switch_sstype()
1390 "[BTCoex], %s Switch SS Type = %d\n", halbtc8192e2ant_switch_sstype()
3433 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x ", "SS Type", ex_halbtc8192e2ant_display_coex_info()
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dhw.c940 /* ARFB table 9 for 11ac 5G 2SS */ _rtl92ee_hw_configure()
944 /* ARFB table 10 for 11ac 5G 1SS */ _rtl92ee_hw_configure()
H A Ddm.c1159 } else { /* MCS13~MCS15, 1SS, G-mode */ rtl92ee_dm_dynamic_arfb_select()
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dhw.c1985 /* 1T2R but 1SS (1x1 receive combining) */ _rtl92se_read_adapter_info()
1992 "RF_TYPE=1T2R but only 1SS\n"); _rtl92se_read_adapter_info()
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Dhw.c961 /* ARFB table 9 for 11ac 5G 2SS */ _rtl8723be_hw_configure()
964 /* ARFB table 10 for 11ac 5G 1SS */ _rtl8723be_hw_configure()
/linux-4.4.14/drivers/nfc/
H A Dtrf7970a.c33 * parallel mode, SPI with Slave Select (SS) mode, and SPI without
34 * SS mode. The driver only supports the two SPI modes.
/linux-4.4.14/drivers/staging/rts5208/
H A Drtsx_chip.h717 /* Flag to indicate that this card is just resumed from SS state,
/linux-4.4.14/drivers/staging/media/lirc/
H A Dlirc_imon.c139 /* SoundGraph iMON SS (IR & VFD) -- iMON_SS.inf */
/linux-4.4.14/drivers/gpu/drm/panel/
H A Dpanel-samsung-s6e8aa0.c208 /* SS */ s6e8aa0_panel_cond_set_v142()
/linux-4.4.14/drivers/usb/core/
H A Dhub.c2819 * If the port is in SS.Inactive or Compliance Mode, the hub_port_reset()
3325 * There are some SS USB devices which take longer time for link training.
3342 * This routine should only be called when persist is enabled for a SS
5016 * SS.Inactive state.
/linux-4.4.14/drivers/net/wireless/mwifiex/
H A Djoin.c371 * - SS TLV
/linux-4.4.14/arch/m68k/include/asm/
H A DMC68VZ328.h569 #define PJ_SS 0x08 /* Use SS as PJ[3] */
/linux-4.4.14/drivers/usb/serial/
H A Dmos7720.c1058 dev_dbg(&port->dev, "SS::%p LSR:%x\n", mos7720_port, data); mos7720_open()
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/
H A Dhw.c2268 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n", rtl92cu_gpio_radio_on_off_checking()
/linux-4.4.14/include/linux/usb/
H A Dgadget.h195 * @mult: multiplier, 'mult' value for SS Isoc EPs
/linux-4.4.14/drivers/usb/host/
H A Dxhci-ring.c1571 xhci_dbg(xhci, "remote wake SS port %d\n", port_id); handle_port_status()
1600 xhci_dbg(xhci, "resume SS port %d finished\n", port_id); handle_port_status()
H A Dxhci-mem.c1295 /* Fall through - SS and HS isoc/int have same decoding */ xhci_get_endpoint_interval()
/linux-4.4.14/sound/pci/ac97/
H A Dac97_patch.c1810 * (SS vendor << 16 | device)
1854 * (SS vendor << 16 | device)
/linux-4.4.14/drivers/tty/
H A Drocket.c2970 Word_t *WordPtr; /* must be far because Win SS != DS */ sWriteTxPrioByte()
/linux-4.4.14/mm/
H A Dswapfile.c2547 (p->flags & SWP_SOLIDSTATE) ? "SS" : "",
/linux-4.4.14/kernel/debug/kdb/
H A Dkdb_main.c1253 "Breakpoint" : "SS trap", instruction_pointer(regs)); kdb_local()
/linux-4.4.14/sound/pci/rme9652/
H A Dhdspm.c1241 * So if we read SS values (32 .. 48k), check for
/linux-4.4.14/drivers/isdn/hardware/eicon/
H A Dmessage.c4512 PUT_WORD(&SSparms[4], 0x300E); /* SS not supported */ control_rc()

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