1/* 2 * Cadence SPI controller driver (master mode only) 3 * 4 * Copyright (C) 2008 - 2014 Xilinx, Inc. 5 * 6 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c) 7 * 8 * This program is free software; you can redistribute it and/or modify it under 9 * the terms of the GNU General Public License version 2 as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14#include <linux/clk.h> 15#include <linux/delay.h> 16#include <linux/interrupt.h> 17#include <linux/io.h> 18#include <linux/module.h> 19#include <linux/of_irq.h> 20#include <linux/of_address.h> 21#include <linux/platform_device.h> 22#include <linux/spi/spi.h> 23 24/* Name of this driver */ 25#define CDNS_SPI_NAME "cdns-spi" 26 27/* Register offset definitions */ 28#define CDNS_SPI_CR_OFFSET 0x00 /* Configuration Register, RW */ 29#define CDNS_SPI_ISR_OFFSET 0x04 /* Interrupt Status Register, RO */ 30#define CDNS_SPI_IER_OFFSET 0x08 /* Interrupt Enable Register, WO */ 31#define CDNS_SPI_IDR_OFFSET 0x0c /* Interrupt Disable Register, WO */ 32#define CDNS_SPI_IMR_OFFSET 0x10 /* Interrupt Enabled Mask Register, RO */ 33#define CDNS_SPI_ER_OFFSET 0x14 /* Enable/Disable Register, RW */ 34#define CDNS_SPI_DR_OFFSET 0x18 /* Delay Register, RW */ 35#define CDNS_SPI_TXD_OFFSET 0x1C /* Data Transmit Register, WO */ 36#define CDNS_SPI_RXD_OFFSET 0x20 /* Data Receive Register, RO */ 37#define CDNS_SPI_SICR_OFFSET 0x24 /* Slave Idle Count Register, RW */ 38#define CDNS_SPI_THLD_OFFSET 0x28 /* Transmit FIFO Watermark Register,RW */ 39 40/* 41 * SPI Configuration Register bit Masks 42 * 43 * This register contains various control bits that affect the operation 44 * of the SPI controller 45 */ 46#define CDNS_SPI_CR_MANSTRT_MASK 0x00010000 /* Manual TX Start */ 47#define CDNS_SPI_CR_CPHA_MASK 0x00000004 /* Clock Phase Control */ 48#define CDNS_SPI_CR_CPOL_MASK 0x00000002 /* Clock Polarity Control */ 49#define CDNS_SPI_CR_SSCTRL_MASK 0x00003C00 /* Slave Select Mask */ 50#define CDNS_SPI_CR_PERI_SEL_MASK 0x00000200 /* Peripheral Select Decode */ 51#define CDNS_SPI_CR_BAUD_DIV_MASK 0x00000038 /* Baud Rate Divisor Mask */ 52#define CDNS_SPI_CR_MSTREN_MASK 0x00000001 /* Master Enable Mask */ 53#define CDNS_SPI_CR_MANSTRTEN_MASK 0x00008000 /* Manual TX Enable Mask */ 54#define CDNS_SPI_CR_SSFORCE_MASK 0x00004000 /* Manual SS Enable Mask */ 55#define CDNS_SPI_CR_BAUD_DIV_4_MASK 0x00000008 /* Default Baud Div Mask */ 56#define CDNS_SPI_CR_DEFAULT_MASK (CDNS_SPI_CR_MSTREN_MASK | \ 57 CDNS_SPI_CR_SSCTRL_MASK | \ 58 CDNS_SPI_CR_SSFORCE_MASK | \ 59 CDNS_SPI_CR_BAUD_DIV_4_MASK) 60 61/* 62 * SPI Configuration Register - Baud rate and slave select 63 * 64 * These are the values used in the calculation of baud rate divisor and 65 * setting the slave select. 66 */ 67 68#define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */ 69#define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */ 70#define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */ 71#define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */ 72#define CDNS_SPI_SS0 0x1 /* Slave Select zero */ 73 74/* 75 * SPI Interrupt Registers bit Masks 76 * 77 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same 78 * bit definitions. 79 */ 80#define CDNS_SPI_IXR_TXOW_MASK 0x00000004 /* SPI TX FIFO Overwater */ 81#define CDNS_SPI_IXR_MODF_MASK 0x00000002 /* SPI Mode Fault */ 82#define CDNS_SPI_IXR_RXNEMTY_MASK 0x00000010 /* SPI RX FIFO Not Empty */ 83#define CDNS_SPI_IXR_DEFAULT_MASK (CDNS_SPI_IXR_TXOW_MASK | \ 84 CDNS_SPI_IXR_MODF_MASK) 85#define CDNS_SPI_IXR_TXFULL_MASK 0x00000008 /* SPI TX Full */ 86#define CDNS_SPI_IXR_ALL_MASK 0x0000007F /* SPI all interrupts */ 87 88/* 89 * SPI Enable Register bit Masks 90 * 91 * This register is used to enable or disable the SPI controller 92 */ 93#define CDNS_SPI_ER_ENABLE_MASK 0x00000001 /* SPI Enable Bit Mask */ 94#define CDNS_SPI_ER_DISABLE_MASK 0x0 /* SPI Disable Bit Mask */ 95 96/* SPI FIFO depth in bytes */ 97#define CDNS_SPI_FIFO_DEPTH 128 98 99/* Default number of chip select lines */ 100#define CDNS_SPI_DEFAULT_NUM_CS 4 101 102/** 103 * struct cdns_spi - This definition defines spi driver instance 104 * @regs: Virtual address of the SPI controller registers 105 * @ref_clk: Pointer to the peripheral clock 106 * @pclk: Pointer to the APB clock 107 * @speed_hz: Current SPI bus clock speed in Hz 108 * @txbuf: Pointer to the TX buffer 109 * @rxbuf: Pointer to the RX buffer 110 * @tx_bytes: Number of bytes left to transfer 111 * @rx_bytes: Number of bytes requested 112 * @dev_busy: Device busy flag 113 * @is_decoded_cs: Flag for decoder property set or not 114 */ 115struct cdns_spi { 116 void __iomem *regs; 117 struct clk *ref_clk; 118 struct clk *pclk; 119 u32 speed_hz; 120 const u8 *txbuf; 121 u8 *rxbuf; 122 int tx_bytes; 123 int rx_bytes; 124 u8 dev_busy; 125 u32 is_decoded_cs; 126}; 127 128/* Macros for the SPI controller read/write */ 129static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset) 130{ 131 return readl_relaxed(xspi->regs + offset); 132} 133 134static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val) 135{ 136 writel_relaxed(val, xspi->regs + offset); 137} 138 139/** 140 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller 141 * @xspi: Pointer to the cdns_spi structure 142 * 143 * On reset the SPI controller is configured to be in master mode, baud rate 144 * divisor is set to 4, threshold value for TX FIFO not full interrupt is set 145 * to 1 and size of the word to be transferred as 8 bit. 146 * This function initializes the SPI controller to disable and clear all the 147 * interrupts, enable manual slave select and manual start, deselect all the 148 * chip select lines, and enable the SPI controller. 149 */ 150static void cdns_spi_init_hw(struct cdns_spi *xspi) 151{ 152 u32 ctrl_reg = CDNS_SPI_CR_DEFAULT_MASK; 153 154 if (xspi->is_decoded_cs) 155 ctrl_reg |= CDNS_SPI_CR_PERI_SEL_MASK; 156 157 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 158 CDNS_SPI_ER_DISABLE_MASK); 159 cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET, 160 CDNS_SPI_IXR_ALL_MASK); 161 162 /* Clear the RX FIFO */ 163 while (cdns_spi_read(xspi, CDNS_SPI_ISR_OFFSET) & 164 CDNS_SPI_IXR_RXNEMTY_MASK) 165 cdns_spi_read(xspi, CDNS_SPI_RXD_OFFSET); 166 167 cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET, 168 CDNS_SPI_IXR_ALL_MASK); 169 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg); 170 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 171 CDNS_SPI_ER_ENABLE_MASK); 172} 173 174/** 175 * cdns_spi_chipselect - Select or deselect the chip select line 176 * @spi: Pointer to the spi_device structure 177 * @is_on: Select(0) or deselect (1) the chip select line 178 */ 179static void cdns_spi_chipselect(struct spi_device *spi, bool is_high) 180{ 181 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 182 u32 ctrl_reg; 183 184 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET); 185 186 if (is_high) { 187 /* Deselect the slave */ 188 ctrl_reg |= CDNS_SPI_CR_SSCTRL_MASK; 189 } else { 190 /* Select the slave */ 191 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL_MASK; 192 if (!(xspi->is_decoded_cs)) 193 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) << 194 CDNS_SPI_SS_SHIFT) & 195 CDNS_SPI_CR_SSCTRL_MASK; 196 else 197 ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) & 198 CDNS_SPI_CR_SSCTRL_MASK; 199 } 200 201 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg); 202} 203 204/** 205 * cdns_spi_config_clock_mode - Sets clock polarity and phase 206 * @spi: Pointer to the spi_device structure 207 * 208 * Sets the requested clock polarity and phase. 209 */ 210static void cdns_spi_config_clock_mode(struct spi_device *spi) 211{ 212 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 213 u32 ctrl_reg, new_ctrl_reg; 214 215 new_ctrl_reg = ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET); 216 217 /* Set the SPI clock phase and clock polarity */ 218 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA_MASK | CDNS_SPI_CR_CPOL_MASK); 219 if (spi->mode & SPI_CPHA) 220 new_ctrl_reg |= CDNS_SPI_CR_CPHA_MASK; 221 if (spi->mode & SPI_CPOL) 222 new_ctrl_reg |= CDNS_SPI_CR_CPOL_MASK; 223 224 if (new_ctrl_reg != ctrl_reg) { 225 /* 226 * Just writing the CR register does not seem to apply the clock 227 * setting changes. This is problematic when changing the clock 228 * polarity as it will cause the SPI slave to see spurious clock 229 * transitions. To workaround the issue toggle the ER register. 230 */ 231 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 232 CDNS_SPI_ER_DISABLE_MASK); 233 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, new_ctrl_reg); 234 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 235 CDNS_SPI_ER_ENABLE_MASK); 236 } 237} 238 239/** 240 * cdns_spi_config_clock_freq - Sets clock frequency 241 * @spi: Pointer to the spi_device structure 242 * @transfer: Pointer to the spi_transfer structure which provides 243 * information about next transfer setup parameters 244 * 245 * Sets the requested clock frequency. 246 * Note: If the requested frequency is not an exact match with what can be 247 * obtained using the prescalar value the driver sets the clock frequency which 248 * is lower than the requested frequency (maximum lower) for the transfer. If 249 * the requested frequency is higher or lower than that is supported by the SPI 250 * controller the driver will set the highest or lowest frequency supported by 251 * controller. 252 */ 253static void cdns_spi_config_clock_freq(struct spi_device *spi, 254 struct spi_transfer *transfer) 255{ 256 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 257 u32 ctrl_reg, baud_rate_val; 258 unsigned long frequency; 259 260 frequency = clk_get_rate(xspi->ref_clk); 261 262 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET); 263 264 /* Set the clock frequency */ 265 if (xspi->speed_hz != transfer->speed_hz) { 266 /* first valid value is 1 */ 267 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN; 268 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) && 269 (frequency / (2 << baud_rate_val)) > transfer->speed_hz) 270 baud_rate_val++; 271 272 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV_MASK; 273 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT; 274 275 xspi->speed_hz = frequency / (2 << baud_rate_val); 276 } 277 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg); 278} 279 280/** 281 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer 282 * @spi: Pointer to the spi_device structure 283 * @transfer: Pointer to the spi_transfer structure which provides 284 * information about next transfer setup parameters 285 * 286 * Sets the operational mode of SPI controller for the next SPI transfer and 287 * sets the requested clock frequency. 288 * 289 * Return: Always 0 290 */ 291static int cdns_spi_setup_transfer(struct spi_device *spi, 292 struct spi_transfer *transfer) 293{ 294 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 295 296 cdns_spi_config_clock_freq(spi, transfer); 297 298 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n", 299 __func__, spi->mode, spi->bits_per_word, 300 xspi->speed_hz); 301 302 return 0; 303} 304 305/** 306 * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible 307 * @xspi: Pointer to the cdns_spi structure 308 */ 309static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi) 310{ 311 unsigned long trans_cnt = 0; 312 313 while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) && 314 (xspi->tx_bytes > 0)) { 315 if (xspi->txbuf) 316 cdns_spi_write(xspi, CDNS_SPI_TXD_OFFSET, 317 *xspi->txbuf++); 318 else 319 cdns_spi_write(xspi, CDNS_SPI_TXD_OFFSET, 0); 320 321 xspi->tx_bytes--; 322 trans_cnt++; 323 } 324} 325 326/** 327 * cdns_spi_irq - Interrupt service routine of the SPI controller 328 * @irq: IRQ number 329 * @dev_id: Pointer to the xspi structure 330 * 331 * This function handles TX empty and Mode Fault interrupts only. 332 * On TX empty interrupt this function reads the received data from RX FIFO and 333 * fills the TX FIFO if there is any data remaining to be transferred. 334 * On Mode Fault interrupt this function indicates that transfer is completed, 335 * the SPI subsystem will identify the error as the remaining bytes to be 336 * transferred is non-zero. 337 * 338 * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise. 339 */ 340static irqreturn_t cdns_spi_irq(int irq, void *dev_id) 341{ 342 struct spi_master *master = dev_id; 343 struct cdns_spi *xspi = spi_master_get_devdata(master); 344 u32 intr_status, status; 345 346 status = IRQ_NONE; 347 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR_OFFSET); 348 cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET, intr_status); 349 350 if (intr_status & CDNS_SPI_IXR_MODF_MASK) { 351 /* Indicate that transfer is completed, the SPI subsystem will 352 * identify the error as the remaining bytes to be 353 * transferred is non-zero 354 */ 355 cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET, 356 CDNS_SPI_IXR_DEFAULT_MASK); 357 spi_finalize_current_transfer(master); 358 status = IRQ_HANDLED; 359 } else if (intr_status & CDNS_SPI_IXR_TXOW_MASK) { 360 unsigned long trans_cnt; 361 362 trans_cnt = xspi->rx_bytes - xspi->tx_bytes; 363 364 /* Read out the data from the RX FIFO */ 365 while (trans_cnt) { 366 u8 data; 367 368 data = cdns_spi_read(xspi, CDNS_SPI_RXD_OFFSET); 369 if (xspi->rxbuf) 370 *xspi->rxbuf++ = data; 371 372 xspi->rx_bytes--; 373 trans_cnt--; 374 } 375 376 if (xspi->tx_bytes) { 377 /* There is more data to send */ 378 cdns_spi_fill_tx_fifo(xspi); 379 } else { 380 /* Transfer is completed */ 381 cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET, 382 CDNS_SPI_IXR_DEFAULT_MASK); 383 spi_finalize_current_transfer(master); 384 } 385 status = IRQ_HANDLED; 386 } 387 388 return status; 389} 390static int cdns_prepare_message(struct spi_master *master, 391 struct spi_message *msg) 392{ 393 cdns_spi_config_clock_mode(msg->spi); 394 return 0; 395} 396 397/** 398 * cdns_transfer_one - Initiates the SPI transfer 399 * @master: Pointer to spi_master structure 400 * @spi: Pointer to the spi_device structure 401 * @transfer: Pointer to the spi_transfer structure which provides 402 * information about next transfer parameters 403 * 404 * This function fills the TX FIFO, starts the SPI transfer and 405 * returns a positive transfer count so that core will wait for completion. 406 * 407 * Return: Number of bytes transferred in the last transfer 408 */ 409static int cdns_transfer_one(struct spi_master *master, 410 struct spi_device *spi, 411 struct spi_transfer *transfer) 412{ 413 struct cdns_spi *xspi = spi_master_get_devdata(master); 414 415 xspi->txbuf = transfer->tx_buf; 416 xspi->rxbuf = transfer->rx_buf; 417 xspi->tx_bytes = transfer->len; 418 xspi->rx_bytes = transfer->len; 419 420 cdns_spi_setup_transfer(spi, transfer); 421 422 cdns_spi_fill_tx_fifo(xspi); 423 424 cdns_spi_write(xspi, CDNS_SPI_IER_OFFSET, 425 CDNS_SPI_IXR_DEFAULT_MASK); 426 return transfer->len; 427} 428 429/** 430 * cdns_prepare_transfer_hardware - Prepares hardware for transfer. 431 * @master: Pointer to the spi_master structure which provides 432 * information about the controller. 433 * 434 * This function enables SPI master controller. 435 * 436 * Return: 0 always 437 */ 438static int cdns_prepare_transfer_hardware(struct spi_master *master) 439{ 440 struct cdns_spi *xspi = spi_master_get_devdata(master); 441 442 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 443 CDNS_SPI_ER_ENABLE_MASK); 444 445 return 0; 446} 447 448/** 449 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer 450 * @master: Pointer to the spi_master structure which provides 451 * information about the controller. 452 * 453 * This function disables the SPI master controller. 454 * 455 * Return: 0 always 456 */ 457static int cdns_unprepare_transfer_hardware(struct spi_master *master) 458{ 459 struct cdns_spi *xspi = spi_master_get_devdata(master); 460 461 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 462 CDNS_SPI_ER_DISABLE_MASK); 463 464 return 0; 465} 466 467/** 468 * cdns_spi_probe - Probe method for the SPI driver 469 * @pdev: Pointer to the platform_device structure 470 * 471 * This function initializes the driver data structures and the hardware. 472 * 473 * Return: 0 on success and error value on error 474 */ 475static int cdns_spi_probe(struct platform_device *pdev) 476{ 477 int ret = 0, irq; 478 struct spi_master *master; 479 struct cdns_spi *xspi; 480 struct resource *res; 481 u32 num_cs; 482 483 master = spi_alloc_master(&pdev->dev, sizeof(*xspi)); 484 if (master == NULL) 485 return -ENOMEM; 486 487 xspi = spi_master_get_devdata(master); 488 master->dev.of_node = pdev->dev.of_node; 489 platform_set_drvdata(pdev, master); 490 491 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 492 xspi->regs = devm_ioremap_resource(&pdev->dev, res); 493 if (IS_ERR(xspi->regs)) { 494 ret = PTR_ERR(xspi->regs); 495 goto remove_master; 496 } 497 498 xspi->pclk = devm_clk_get(&pdev->dev, "pclk"); 499 if (IS_ERR(xspi->pclk)) { 500 dev_err(&pdev->dev, "pclk clock not found.\n"); 501 ret = PTR_ERR(xspi->pclk); 502 goto remove_master; 503 } 504 505 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk"); 506 if (IS_ERR(xspi->ref_clk)) { 507 dev_err(&pdev->dev, "ref_clk clock not found.\n"); 508 ret = PTR_ERR(xspi->ref_clk); 509 goto remove_master; 510 } 511 512 ret = clk_prepare_enable(xspi->pclk); 513 if (ret) { 514 dev_err(&pdev->dev, "Unable to enable APB clock.\n"); 515 goto remove_master; 516 } 517 518 ret = clk_prepare_enable(xspi->ref_clk); 519 if (ret) { 520 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 521 goto clk_dis_apb; 522 } 523 524 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); 525 if (ret < 0) 526 master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS; 527 else 528 master->num_chipselect = num_cs; 529 530 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs", 531 &xspi->is_decoded_cs); 532 if (ret < 0) 533 xspi->is_decoded_cs = 0; 534 535 /* SPI controller initializations */ 536 cdns_spi_init_hw(xspi); 537 538 irq = platform_get_irq(pdev, 0); 539 if (irq <= 0) { 540 ret = -ENXIO; 541 dev_err(&pdev->dev, "irq number is invalid\n"); 542 goto remove_master; 543 } 544 545 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq, 546 0, pdev->name, master); 547 if (ret != 0) { 548 ret = -ENXIO; 549 dev_err(&pdev->dev, "request_irq failed\n"); 550 goto remove_master; 551 } 552 553 master->prepare_transfer_hardware = cdns_prepare_transfer_hardware; 554 master->prepare_message = cdns_prepare_message; 555 master->transfer_one = cdns_transfer_one; 556 master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware; 557 master->set_cs = cdns_spi_chipselect; 558 master->mode_bits = SPI_CPOL | SPI_CPHA; 559 560 /* Set to default valid value */ 561 master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4; 562 xspi->speed_hz = master->max_speed_hz; 563 564 master->bits_per_word_mask = SPI_BPW_MASK(8); 565 566 ret = spi_register_master(master); 567 if (ret) { 568 dev_err(&pdev->dev, "spi_register_master failed\n"); 569 goto clk_dis_all; 570 } 571 572 return ret; 573 574clk_dis_all: 575 clk_disable_unprepare(xspi->ref_clk); 576clk_dis_apb: 577 clk_disable_unprepare(xspi->pclk); 578remove_master: 579 spi_master_put(master); 580 return ret; 581} 582 583/** 584 * cdns_spi_remove - Remove method for the SPI driver 585 * @pdev: Pointer to the platform_device structure 586 * 587 * This function is called if a device is physically removed from the system or 588 * if the driver module is being unloaded. It frees all resources allocated to 589 * the device. 590 * 591 * Return: 0 on success and error value on error 592 */ 593static int cdns_spi_remove(struct platform_device *pdev) 594{ 595 struct spi_master *master = platform_get_drvdata(pdev); 596 struct cdns_spi *xspi = spi_master_get_devdata(master); 597 598 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 599 CDNS_SPI_ER_DISABLE_MASK); 600 601 clk_disable_unprepare(xspi->ref_clk); 602 clk_disable_unprepare(xspi->pclk); 603 604 spi_unregister_master(master); 605 606 return 0; 607} 608 609/** 610 * cdns_spi_suspend - Suspend method for the SPI driver 611 * @dev: Address of the platform_device structure 612 * 613 * This function disables the SPI controller and 614 * changes the driver state to "suspend" 615 * 616 * Return: Always 0 617 */ 618static int __maybe_unused cdns_spi_suspend(struct device *dev) 619{ 620 struct platform_device *pdev = container_of(dev, 621 struct platform_device, dev); 622 struct spi_master *master = platform_get_drvdata(pdev); 623 struct cdns_spi *xspi = spi_master_get_devdata(master); 624 625 spi_master_suspend(master); 626 627 clk_disable_unprepare(xspi->ref_clk); 628 629 clk_disable_unprepare(xspi->pclk); 630 631 return 0; 632} 633 634/** 635 * cdns_spi_resume - Resume method for the SPI driver 636 * @dev: Address of the platform_device structure 637 * 638 * This function changes the driver state to "ready" 639 * 640 * Return: 0 on success and error value on error 641 */ 642static int __maybe_unused cdns_spi_resume(struct device *dev) 643{ 644 struct platform_device *pdev = container_of(dev, 645 struct platform_device, dev); 646 struct spi_master *master = platform_get_drvdata(pdev); 647 struct cdns_spi *xspi = spi_master_get_devdata(master); 648 int ret = 0; 649 650 ret = clk_prepare_enable(xspi->pclk); 651 if (ret) { 652 dev_err(dev, "Cannot enable APB clock.\n"); 653 return ret; 654 } 655 656 ret = clk_prepare_enable(xspi->ref_clk); 657 if (ret) { 658 dev_err(dev, "Cannot enable device clock.\n"); 659 clk_disable(xspi->pclk); 660 return ret; 661 } 662 spi_master_resume(master); 663 664 return 0; 665} 666 667static SIMPLE_DEV_PM_OPS(cdns_spi_dev_pm_ops, cdns_spi_suspend, 668 cdns_spi_resume); 669 670static const struct of_device_id cdns_spi_of_match[] = { 671 { .compatible = "xlnx,zynq-spi-r1p6" }, 672 { .compatible = "cdns,spi-r1p6" }, 673 { /* end of table */ } 674}; 675MODULE_DEVICE_TABLE(of, cdns_spi_of_match); 676 677/* cdns_spi_driver - This structure defines the SPI subsystem platform driver */ 678static struct platform_driver cdns_spi_driver = { 679 .probe = cdns_spi_probe, 680 .remove = cdns_spi_remove, 681 .driver = { 682 .name = CDNS_SPI_NAME, 683 .of_match_table = cdns_spi_of_match, 684 .pm = &cdns_spi_dev_pm_ops, 685 }, 686}; 687 688module_platform_driver(cdns_spi_driver); 689 690MODULE_AUTHOR("Xilinx, Inc."); 691MODULE_DESCRIPTION("Cadence SPI driver"); 692MODULE_LICENSE("GPL"); 693