1 2/* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers 3 * 4 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com> 5 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca> 6 * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> 7 * Bare & Hare Software, Inc. 8 * Based on include/asm-m68knommu/MC68332.h 9 * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>, 10 * The Silver Hammer Group, Ltd. 11 * 12 * M68VZ328 fixes by Evan Stawnyczy <evan@lineo.com> 13 * vz multiport fixes by Michael Leslie <mleslie@lineo.com> 14 */ 15 16#ifndef _MC68VZ328_H_ 17#define _MC68VZ328_H_ 18 19#define BYTE_REF(addr) (*((volatile unsigned char*)addr)) 20#define WORD_REF(addr) (*((volatile unsigned short*)addr)) 21#define LONG_REF(addr) (*((volatile unsigned long*)addr)) 22 23#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) 24#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) 25 26/********** 27 * 28 * 0xFFFFF0xx -- System Control 29 * 30 **********/ 31 32/* 33 * System Control Register (SCR) 34 */ 35#define SCR_ADDR 0xfffff000 36#define SCR BYTE_REF(SCR_ADDR) 37 38#define SCR_WDTH8 0x01 /* 8-Bit Width Select */ 39#define SCR_DMAP 0x04 /* Double Map */ 40#define SCR_SO 0x08 /* Supervisor Only */ 41#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */ 42#define SCR_PRV 0x20 /* Privilege Violation */ 43#define SCR_WPV 0x40 /* Write Protect Violation */ 44#define SCR_BETO 0x80 /* Bus-Error TimeOut */ 45 46/* 47 * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility) 48 */ 49#define MRR_ADDR 0xfffff004 50#define MRR LONG_REF(MRR_ADDR) 51 52/********** 53 * 54 * 0xFFFFF1xx -- Chip-Select logic 55 * 56 **********/ 57 58/* 59 * Chip Select Group Base Registers 60 */ 61#define CSGBA_ADDR 0xfffff100 62#define CSGBB_ADDR 0xfffff102 63 64#define CSGBC_ADDR 0xfffff104 65#define CSGBD_ADDR 0xfffff106 66 67#define CSGBA WORD_REF(CSGBA_ADDR) 68#define CSGBB WORD_REF(CSGBB_ADDR) 69#define CSGBC WORD_REF(CSGBC_ADDR) 70#define CSGBD WORD_REF(CSGBD_ADDR) 71 72/* 73 * Chip Select Registers 74 */ 75#define CSA_ADDR 0xfffff110 76#define CSB_ADDR 0xfffff112 77#define CSC_ADDR 0xfffff114 78#define CSD_ADDR 0xfffff116 79 80#define CSA WORD_REF(CSA_ADDR) 81#define CSB WORD_REF(CSB_ADDR) 82#define CSC WORD_REF(CSC_ADDR) 83#define CSD WORD_REF(CSD_ADDR) 84 85#define CSA_EN 0x0001 /* Chip-Select Enable */ 86#define CSA_SIZ_MASK 0x000e /* Chip-Select Size */ 87#define CSA_SIZ_SHIFT 1 88#define CSA_WS_MASK 0x0070 /* Wait State */ 89#define CSA_WS_SHIFT 4 90#define CSA_BSW 0x0080 /* Data Bus Width */ 91#define CSA_FLASH 0x0100 /* FLASH Memory Support */ 92#define CSA_RO 0x8000 /* Read-Only */ 93 94#define CSB_EN 0x0001 /* Chip-Select Enable */ 95#define CSB_SIZ_MASK 0x000e /* Chip-Select Size */ 96#define CSB_SIZ_SHIFT 1 97#define CSB_WS_MASK 0x0070 /* Wait State */ 98#define CSB_WS_SHIFT 4 99#define CSB_BSW 0x0080 /* Data Bus Width */ 100#define CSB_FLASH 0x0100 /* FLASH Memory Support */ 101#define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ 102#define CSB_UPSIZ_SHIFT 11 103#define CSB_ROP 0x2000 /* Readonly if protected */ 104#define CSB_SOP 0x4000 /* Supervisor only if protected */ 105#define CSB_RO 0x8000 /* Read-Only */ 106 107#define CSC_EN 0x0001 /* Chip-Select Enable */ 108#define CSC_SIZ_MASK 0x000e /* Chip-Select Size */ 109#define CSC_SIZ_SHIFT 1 110#define CSC_WS_MASK 0x0070 /* Wait State */ 111#define CSC_WS_SHIFT 4 112#define CSC_BSW 0x0080 /* Data Bus Width */ 113#define CSC_FLASH 0x0100 /* FLASH Memory Support */ 114#define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ 115#define CSC_UPSIZ_SHIFT 11 116#define CSC_ROP 0x2000 /* Readonly if protected */ 117#define CSC_SOP 0x4000 /* Supervisor only if protected */ 118#define CSC_RO 0x8000 /* Read-Only */ 119 120#define CSD_EN 0x0001 /* Chip-Select Enable */ 121#define CSD_SIZ_MASK 0x000e /* Chip-Select Size */ 122#define CSD_SIZ_SHIFT 1 123#define CSD_WS_MASK 0x0070 /* Wait State */ 124#define CSD_WS_SHIFT 4 125#define CSD_BSW 0x0080 /* Data Bus Width */ 126#define CSD_FLASH 0x0100 /* FLASH Memory Support */ 127#define CSD_DRAM 0x0200 /* Dram Selection */ 128#define CSD_COMB 0x0400 /* Combining */ 129#define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ 130#define CSD_UPSIZ_SHIFT 11 131#define CSD_ROP 0x2000 /* Readonly if protected */ 132#define CSD_SOP 0x4000 /* Supervisor only if protected */ 133#define CSD_RO 0x8000 /* Read-Only */ 134 135/* 136 * Emulation Chip-Select Register 137 */ 138#define EMUCS_ADDR 0xfffff118 139#define EMUCS WORD_REF(EMUCS_ADDR) 140 141#define EMUCS_WS_MASK 0x0070 142#define EMUCS_WS_SHIFT 4 143 144/********** 145 * 146 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control 147 * 148 **********/ 149 150/* 151 * PLL Control Register 152 */ 153#define PLLCR_ADDR 0xfffff200 154#define PLLCR WORD_REF(PLLCR_ADDR) 155 156#define PLLCR_DISPLL 0x0008 /* Disable PLL */ 157#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */ 158#define PLLCR_PRESC 0x0020 /* VCO prescaler */ 159#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */ 160#define PLLCR_SYSCLK_SEL_SHIFT 8 161#define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */ 162#define PLLCR_LCDCLK_SEL_SHIFT 11 163 164/* '328-compatible definitions */ 165#define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK 166#define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT 167 168/* 169 * PLL Frequency Select Register 170 */ 171#define PLLFSR_ADDR 0xfffff202 172#define PLLFSR WORD_REF(PLLFSR_ADDR) 173 174#define PLLFSR_PC_MASK 0x00ff /* P Count */ 175#define PLLFSR_PC_SHIFT 0 176#define PLLFSR_QC_MASK 0x0f00 /* Q Count */ 177#define PLLFSR_QC_SHIFT 8 178#define PLLFSR_PROT 0x4000 /* Protect P & Q */ 179#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */ 180 181/* 182 * Power Control Register 183 */ 184#define PCTRL_ADDR 0xfffff207 185#define PCTRL BYTE_REF(PCTRL_ADDR) 186 187#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */ 188#define PCTRL_WIDTH_SHIFT 0 189#define PCTRL_PCEN 0x80 /* Power Control Enable */ 190 191/********** 192 * 193 * 0xFFFFF3xx -- Interrupt Controller 194 * 195 **********/ 196 197/* 198 * Interrupt Vector Register 199 */ 200#define IVR_ADDR 0xfffff300 201#define IVR BYTE_REF(IVR_ADDR) 202 203#define IVR_VECTOR_MASK 0xF8 204 205/* 206 * Interrupt control Register 207 */ 208#define ICR_ADDR 0xfffff302 209#define ICR WORD_REF(ICR_ADDR) 210 211#define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */ 212#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */ 213#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */ 214#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */ 215#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */ 216#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */ 217#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */ 218#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */ 219#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */ 220 221/* 222 * Interrupt Mask Register 223 */ 224#define IMR_ADDR 0xfffff304 225#define IMR LONG_REF(IMR_ADDR) 226 227/* 228 * Define the names for bit positions first. This is useful for 229 * request_irq 230 */ 231#define SPI2_IRQ_NUM 0 /* SPI 2 interrupt */ 232#define TMR_IRQ_NUM 1 /* Timer 1 interrupt */ 233#define UART1_IRQ_NUM 2 /* UART 1 interrupt */ 234#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */ 235#define RTC_IRQ_NUM 4 /* RTC interrupt */ 236#define TMR2_IRQ_NUM 5 /* Timer 2 interrupt */ 237#define KB_IRQ_NUM 6 /* Keyboard Interrupt */ 238#define PWM1_IRQ_NUM 7 /* Pulse-Width Modulator 1 int. */ 239#define INT0_IRQ_NUM 8 /* External INT0 */ 240#define INT1_IRQ_NUM 9 /* External INT1 */ 241#define INT2_IRQ_NUM 10 /* External INT2 */ 242#define INT3_IRQ_NUM 11 /* External INT3 */ 243#define UART2_IRQ_NUM 12 /* UART 2 interrupt */ 244#define PWM2_IRQ_NUM 13 /* Pulse-Width Modulator 1 int. */ 245#define IRQ1_IRQ_NUM 16 /* IRQ1 */ 246#define IRQ2_IRQ_NUM 17 /* IRQ2 */ 247#define IRQ3_IRQ_NUM 18 /* IRQ3 */ 248#define IRQ6_IRQ_NUM 19 /* IRQ6 */ 249#define IRQ5_IRQ_NUM 20 /* IRQ5 */ 250#define SPI1_IRQ_NUM 21 /* SPI 1 interrupt */ 251#define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */ 252#define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */ 253 254#define SPI_IRQ_NUM SPI2_IRQ_NUM 255 256/* '328-compatible definitions */ 257#define SPIM_IRQ_NUM SPI_IRQ_NUM 258#define TMR1_IRQ_NUM TMR_IRQ_NUM 259#define UART_IRQ_NUM UART1_IRQ_NUM 260 261/* 262 * Here go the bitmasks themselves 263 */ 264#define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */ 265#define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */ 266#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ 267#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ 268#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */ 269#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */ 270#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */ 271#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */ 272#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */ 273#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */ 274#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */ 275#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */ 276#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */ 277#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */ 278#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */ 279#define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */ 280#define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */ 281#define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */ 282 283/* '328-compatible definitions */ 284#define IMR_MSPIM IMR_MSPI 285#define IMR_MTMR1 IMR_MTMR 286 287/* 288 * Interrupt Status Register 289 */ 290#define ISR_ADDR 0xfffff30c 291#define ISR LONG_REF(ISR_ADDR) 292 293#define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ 294#define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ 295#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ 296#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ 297#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ 298#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ 299#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ 300#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ 301#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ 302#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ 303#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ 304#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ 305#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ 306#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ 307#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ 308#define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ 309#define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ 310#define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ 311 312/* '328-compatible definitions */ 313#define ISR_SPIM ISR_SPI 314#define ISR_TMR1 ISR_TMR 315 316/* 317 * Interrupt Pending Register 318 */ 319#define IPR_ADDR 0xfffff30c 320#define IPR LONG_REF(IPR_ADDR) 321 322#define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ 323#define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ 324#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ 325#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ 326#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ 327#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ 328#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ 329#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ 330#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ 331#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ 332#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ 333#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ 334#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ 335#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ 336#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ 337#define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ 338#define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ 339#define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ 340 341/* '328-compatible definitions */ 342#define IPR_SPIM IPR_SPI 343#define IPR_TMR1 IPR_TMR 344 345/********** 346 * 347 * 0xFFFFF4xx -- Parallel Ports 348 * 349 **********/ 350 351/* 352 * Port A 353 */ 354#define PADIR_ADDR 0xfffff400 /* Port A direction reg */ 355#define PADATA_ADDR 0xfffff401 /* Port A data register */ 356#define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */ 357 358#define PADIR BYTE_REF(PADIR_ADDR) 359#define PADATA BYTE_REF(PADATA_ADDR) 360#define PAPUEN BYTE_REF(PAPUEN_ADDR) 361 362#define PA(x) (1 << (x)) 363 364/* 365 * Port B 366 */ 367#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */ 368#define PBDATA_ADDR 0xfffff409 /* Port B data register */ 369#define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */ 370#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */ 371 372#define PBDIR BYTE_REF(PBDIR_ADDR) 373#define PBDATA BYTE_REF(PBDATA_ADDR) 374#define PBPUEN BYTE_REF(PBPUEN_ADDR) 375#define PBSEL BYTE_REF(PBSEL_ADDR) 376 377#define PB(x) (1 << (x)) 378 379#define PB_CSB0 0x01 /* Use CSB0 as PB[0] */ 380#define PB_CSB1 0x02 /* Use CSB1 as PB[1] */ 381#define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */ 382#define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */ 383#define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */ 384#define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */ 385#define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */ 386#define PB_PWMO 0x80 /* Use PWMO as PB[7] */ 387 388/* 389 * Port C 390 */ 391#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */ 392#define PCDATA_ADDR 0xfffff411 /* Port C data register */ 393#define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */ 394#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */ 395 396#define PCDIR BYTE_REF(PCDIR_ADDR) 397#define PCDATA BYTE_REF(PCDATA_ADDR) 398#define PCPDEN BYTE_REF(PCPDEN_ADDR) 399#define PCSEL BYTE_REF(PCSEL_ADDR) 400 401#define PC(x) (1 << (x)) 402 403#define PC_LD0 0x01 /* Use LD0 as PC[0] */ 404#define PC_LD1 0x02 /* Use LD1 as PC[1] */ 405#define PC_LD2 0x04 /* Use LD2 as PC[2] */ 406#define PC_LD3 0x08 /* Use LD3 as PC[3] */ 407#define PC_LFLM 0x10 /* Use LFLM as PC[4] */ 408#define PC_LLP 0x20 /* Use LLP as PC[5] */ 409#define PC_LCLK 0x40 /* Use LCLK as PC[6] */ 410#define PC_LACD 0x80 /* Use LACD as PC[7] */ 411 412/* 413 * Port D 414 */ 415#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */ 416#define PDDATA_ADDR 0xfffff419 /* Port D data register */ 417#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */ 418#define PDSEL_ADDR 0xfffff41b /* Port D Select Register */ 419#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */ 420#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */ 421#define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */ 422#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */ 423 424#define PDDIR BYTE_REF(PDDIR_ADDR) 425#define PDDATA BYTE_REF(PDDATA_ADDR) 426#define PDPUEN BYTE_REF(PDPUEN_ADDR) 427#define PDSEL BYTE_REF(PDSEL_ADDR) 428#define PDPOL BYTE_REF(PDPOL_ADDR) 429#define PDIRQEN BYTE_REF(PDIRQEN_ADDR) 430#define PDKBEN BYTE_REF(PDKBEN_ADDR) 431#define PDIQEG BYTE_REF(PDIQEG_ADDR) 432 433#define PD(x) (1 << (x)) 434 435#define PD_INT0 0x01 /* Use INT0 as PD[0] */ 436#define PD_INT1 0x02 /* Use INT1 as PD[1] */ 437#define PD_INT2 0x04 /* Use INT2 as PD[2] */ 438#define PD_INT3 0x08 /* Use INT3 as PD[3] */ 439#define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */ 440#define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */ 441#define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */ 442#define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */ 443 444/* 445 * Port E 446 */ 447#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */ 448#define PEDATA_ADDR 0xfffff421 /* Port E data register */ 449#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */ 450#define PESEL_ADDR 0xfffff423 /* Port E Select Register */ 451 452#define PEDIR BYTE_REF(PEDIR_ADDR) 453#define PEDATA BYTE_REF(PEDATA_ADDR) 454#define PEPUEN BYTE_REF(PEPUEN_ADDR) 455#define PESEL BYTE_REF(PESEL_ADDR) 456 457#define PE(x) (1 << (x)) 458 459#define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */ 460#define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */ 461#define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */ 462#define PE_DWE 0x08 /* Use DWE as PE[3] */ 463#define PE_RXD 0x10 /* Use RXD as PE[4] */ 464#define PE_TXD 0x20 /* Use TXD as PE[5] */ 465#define PE_RTS 0x40 /* Use RTS as PE[6] */ 466#define PE_CTS 0x80 /* Use CTS as PE[7] */ 467 468/* 469 * Port F 470 */ 471#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */ 472#define PFDATA_ADDR 0xfffff429 /* Port F data register */ 473#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */ 474#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */ 475 476#define PFDIR BYTE_REF(PFDIR_ADDR) 477#define PFDATA BYTE_REF(PFDATA_ADDR) 478#define PFPUEN BYTE_REF(PFPUEN_ADDR) 479#define PFSEL BYTE_REF(PFSEL_ADDR) 480 481#define PF(x) (1 << (x)) 482 483#define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */ 484#define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */ 485#define PF_CLKO 0x04 /* Use CLKO as PF[2] */ 486#define PF_A20 0x08 /* Use A20 as PF[3] */ 487#define PF_A21 0x10 /* Use A21 as PF[4] */ 488#define PF_A22 0x20 /* Use A22 as PF[5] */ 489#define PF_A23 0x40 /* Use A23 as PF[6] */ 490#define PF_CSA1 0x80 /* Use CSA1 as PF[7] */ 491 492/* 493 * Port G 494 */ 495#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */ 496#define PGDATA_ADDR 0xfffff431 /* Port G data register */ 497#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */ 498#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */ 499 500#define PGDIR BYTE_REF(PGDIR_ADDR) 501#define PGDATA BYTE_REF(PGDATA_ADDR) 502#define PGPUEN BYTE_REF(PGPUEN_ADDR) 503#define PGSEL BYTE_REF(PGSEL_ADDR) 504 505#define PG(x) (1 << (x)) 506 507#define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */ 508#define PG_A0 0x02 /* Use A0 as PG[1] */ 509#define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */ 510#define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */ 511#define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */ 512#define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */ 513 514/* 515 * Port J 516 */ 517#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */ 518#define PJDATA_ADDR 0xfffff439 /* Port J data register */ 519#define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enb. reg */ 520#define PJSEL_ADDR 0xfffff43B /* Port J Select Register */ 521 522#define PJDIR BYTE_REF(PJDIR_ADDR) 523#define PJDATA BYTE_REF(PJDATA_ADDR) 524#define PJPUEN BYTE_REF(PJPUEN_ADDR) 525#define PJSEL BYTE_REF(PJSEL_ADDR) 526 527#define PJ(x) (1 << (x)) 528 529/* 530 * Port K 531 */ 532#define PKDIR_ADDR 0xfffff440 /* Port K direction reg */ 533#define PKDATA_ADDR 0xfffff441 /* Port K data register */ 534#define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enb. reg */ 535#define PKSEL_ADDR 0xfffff443 /* Port K Select Register */ 536 537#define PKDIR BYTE_REF(PKDIR_ADDR) 538#define PKDATA BYTE_REF(PKDATA_ADDR) 539#define PKPUEN BYTE_REF(PKPUEN_ADDR) 540#define PKSEL BYTE_REF(PKSEL_ADDR) 541 542#define PK(x) (1 << (x)) 543 544#define PK_DATAREADY 0x01 /* Use ~DATA_READY as PK[0] */ 545#define PK_PWM2 0x01 /* Use PWM2 as PK[0] */ 546#define PK_R_W 0x02 /* Use R/W as PK[1] */ 547#define PK_LDS 0x04 /* Use /LDS as PK[2] */ 548#define PK_UDS 0x08 /* Use /UDS as PK[3] */ 549#define PK_LD4 0x10 /* Use LD4 as PK[4] */ 550#define PK_LD5 0x20 /* Use LD5 as PK[5] */ 551#define PK_LD6 0x40 /* Use LD6 as PK[6] */ 552#define PK_LD7 0x80 /* Use LD7 as PK[7] */ 553 554#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */ 555#define PJDATA_ADDR 0xfffff439 /* Port J data register */ 556#define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enable reg */ 557#define PJSEL_ADDR 0xfffff43B /* Port J Select Register */ 558 559#define PJDIR BYTE_REF(PJDIR_ADDR) 560#define PJDATA BYTE_REF(PJDATA_ADDR) 561#define PJPUEN BYTE_REF(PJPUEN_ADDR) 562#define PJSEL BYTE_REF(PJSEL_ADDR) 563 564#define PJ(x) (1 << (x)) 565 566#define PJ_MOSI 0x01 /* Use MOSI as PJ[0] */ 567#define PJ_MISO 0x02 /* Use MISO as PJ[1] */ 568#define PJ_SPICLK1 0x04 /* Use SPICLK1 as PJ[2] */ 569#define PJ_SS 0x08 /* Use SS as PJ[3] */ 570#define PJ_RXD2 0x10 /* Use RXD2 as PJ[4] */ 571#define PJ_TXD2 0x20 /* Use TXD2 as PJ[5] */ 572#define PJ_RTS2 0x40 /* Use RTS2 as PJ[5] */ 573#define PJ_CTS2 0x80 /* Use CTS2 as PJ[5] */ 574 575/* 576 * Port M 577 */ 578#define PMDIR_ADDR 0xfffff448 /* Port M direction reg */ 579#define PMDATA_ADDR 0xfffff449 /* Port M data register */ 580#define PMPUEN_ADDR 0xfffff44a /* Port M Pull-Up enable reg */ 581#define PMSEL_ADDR 0xfffff44b /* Port M Select Register */ 582 583#define PMDIR BYTE_REF(PMDIR_ADDR) 584#define PMDATA BYTE_REF(PMDATA_ADDR) 585#define PMPUEN BYTE_REF(PMPUEN_ADDR) 586#define PMSEL BYTE_REF(PMSEL_ADDR) 587 588#define PM(x) (1 << (x)) 589 590#define PM_SDCLK 0x01 /* Use SDCLK as PM[0] */ 591#define PM_SDCE 0x02 /* Use SDCE as PM[1] */ 592#define PM_DQMH 0x04 /* Use DQMH as PM[2] */ 593#define PM_DQML 0x08 /* Use DQML as PM[3] */ 594#define PM_SDA10 0x10 /* Use SDA10 as PM[4] */ 595#define PM_DMOE 0x20 /* Use DMOE as PM[5] */ 596 597/********** 598 * 599 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM) 600 * 601 **********/ 602 603/* 604 * PWM Control Register 605 */ 606#define PWMC_ADDR 0xfffff500 607#define PWMC WORD_REF(PWMC_ADDR) 608 609#define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */ 610#define PWMC_CLKSEL_SHIFT 0 611#define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */ 612#define PWMC_REPEAT_SHIFT 2 613#define PWMC_EN 0x0010 /* Enable PWM */ 614#define PMNC_FIFOAV 0x0020 /* FIFO Available */ 615#define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */ 616#define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */ 617#define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */ 618#define PWMC_PRESCALER_SHIFT 8 619#define PWMC_CLKSRC 0x8000 /* Clock Source Select */ 620 621/* '328-compatible definitions */ 622#define PWMC_PWMEN PWMC_EN 623 624/* 625 * PWM Sample Register 626 */ 627#define PWMS_ADDR 0xfffff502 628#define PWMS WORD_REF(PWMS_ADDR) 629 630/* 631 * PWM Period Register 632 */ 633#define PWMP_ADDR 0xfffff504 634#define PWMP BYTE_REF(PWMP_ADDR) 635 636/* 637 * PWM Counter Register 638 */ 639#define PWMCNT_ADDR 0xfffff505 640#define PWMCNT BYTE_REF(PWMCNT_ADDR) 641 642/********** 643 * 644 * 0xFFFFF6xx -- General-Purpose Timer 645 * 646 **********/ 647 648/* 649 * Timer Control register 650 */ 651#define TCTL_ADDR 0xfffff600 652#define TCTL WORD_REF(TCTL_ADDR) 653 654#define TCTL_TEN 0x0001 /* Timer Enable */ 655#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */ 656#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */ 657#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */ 658#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */ 659#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */ 660#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */ 661#define TCTL_IRQEN 0x0010 /* IRQ Enable */ 662#define TCTL_OM 0x0020 /* Output Mode */ 663#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */ 664#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */ 665#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */ 666#define TCTL_FRR 0x0010 /* Free-Run Mode */ 667 668/* '328-compatible definitions */ 669#define TCTL1_ADDR TCTL_ADDR 670#define TCTL1 TCTL 671 672/* 673 * Timer Prescaler Register 674 */ 675#define TPRER_ADDR 0xfffff602 676#define TPRER WORD_REF(TPRER_ADDR) 677 678/* '328-compatible definitions */ 679#define TPRER1_ADDR TPRER_ADDR 680#define TPRER1 TPRER 681 682/* 683 * Timer Compare Register 684 */ 685#define TCMP_ADDR 0xfffff604 686#define TCMP WORD_REF(TCMP_ADDR) 687 688/* '328-compatible definitions */ 689#define TCMP1_ADDR TCMP_ADDR 690#define TCMP1 TCMP 691 692/* 693 * Timer Capture register 694 */ 695#define TCR_ADDR 0xfffff606 696#define TCR WORD_REF(TCR_ADDR) 697 698/* '328-compatible definitions */ 699#define TCR1_ADDR TCR_ADDR 700#define TCR1 TCR 701 702/* 703 * Timer Counter Register 704 */ 705#define TCN_ADDR 0xfffff608 706#define TCN WORD_REF(TCN_ADDR) 707 708/* '328-compatible definitions */ 709#define TCN1_ADDR TCN_ADDR 710#define TCN1 TCN 711 712/* 713 * Timer Status Register 714 */ 715#define TSTAT_ADDR 0xfffff60a 716#define TSTAT WORD_REF(TSTAT_ADDR) 717 718#define TSTAT_COMP 0x0001 /* Compare Event occurred */ 719#define TSTAT_CAPT 0x0001 /* Capture Event occurred */ 720 721/* '328-compatible definitions */ 722#define TSTAT1_ADDR TSTAT_ADDR 723#define TSTAT1 TSTAT 724 725/********** 726 * 727 * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM) 728 * 729 **********/ 730 731/* 732 * SPIM Data Register 733 */ 734#define SPIMDATA_ADDR 0xfffff800 735#define SPIMDATA WORD_REF(SPIMDATA_ADDR) 736 737/* 738 * SPIM Control/Status Register 739 */ 740#define SPIMCONT_ADDR 0xfffff802 741#define SPIMCONT WORD_REF(SPIMCONT_ADDR) 742 743#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */ 744#define SPIMCONT_BIT_COUNT_SHIFT 0 745#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */ 746#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */ 747#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */ 748#define SPIMCONT_IRQ 0x0080 /* Interrupt Request */ 749#define SPIMCONT_XCH 0x0100 /* Exchange */ 750#define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */ 751#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */ 752#define SPIMCONT_DATA_RATE_SHIFT 13 753 754/* '328-compatible definitions */ 755#define SPIMCONT_SPIMIRQ SPIMCONT_IRQ 756#define SPIMCONT_SPIMEN SPIMCONT_ENABLE 757 758/********** 759 * 760 * 0xFFFFF9xx -- UART 761 * 762 **********/ 763 764/* 765 * UART Status/Control Register 766 */ 767 768#define USTCNT_ADDR 0xfffff900 769#define USTCNT WORD_REF(USTCNT_ADDR) 770 771#define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */ 772#define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */ 773#define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */ 774#define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */ 775#define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */ 776#define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */ 777#define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */ 778#define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */ 779#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */ 780#define USTCNT_STOP 0x0200 /* Stop bit transmission */ 781#define USTCNT_ODD 0x0400 /* Odd Parity */ 782#define USTCNT_PEN 0x0800 /* Parity Enable */ 783#define USTCNT_CLKM 0x1000 /* Clock Mode Select */ 784#define USTCNT_TXEN 0x2000 /* Transmitter Enable */ 785#define USTCNT_RXEN 0x4000 /* Receiver Enable */ 786#define USTCNT_UEN 0x8000 /* UART Enable */ 787 788/* '328-compatible definitions */ 789#define USTCNT_TXAVAILEN USTCNT_TXAE 790#define USTCNT_TXHALFEN USTCNT_TXHE 791#define USTCNT_TXEMPTYEN USTCNT_TXEE 792#define USTCNT_RXREADYEN USTCNT_RXRE 793#define USTCNT_RXHALFEN USTCNT_RXHE 794#define USTCNT_RXFULLEN USTCNT_RXFE 795#define USTCNT_CTSDELTAEN USTCNT_CTSD 796#define USTCNT_ODD_EVEN USTCNT_ODD 797#define USTCNT_PARITYEN USTCNT_PEN 798#define USTCNT_CLKMODE USTCNT_CLKM 799#define USTCNT_UARTEN USTCNT_UEN 800 801/* 802 * UART Baud Control Register 803 */ 804#define UBAUD_ADDR 0xfffff902 805#define UBAUD WORD_REF(UBAUD_ADDR) 806 807#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */ 808#define UBAUD_PRESCALER_SHIFT 0 809#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */ 810#define UBAUD_DIVIDE_SHIFT 8 811#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */ 812#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */ 813 814/* 815 * UART Receiver Register 816 */ 817#define URX_ADDR 0xfffff904 818#define URX WORD_REF(URX_ADDR) 819 820#define URX_RXDATA_ADDR 0xfffff905 821#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR) 822 823#define URX_RXDATA_MASK 0x00ff /* Received data */ 824#define URX_RXDATA_SHIFT 0 825#define URX_PARITY_ERROR 0x0100 /* Parity Error */ 826#define URX_BREAK 0x0200 /* Break Detected */ 827#define URX_FRAME_ERROR 0x0400 /* Framing Error */ 828#define URX_OVRUN 0x0800 /* Serial Overrun */ 829#define URX_OLD_DATA 0x1000 /* Old data in FIFO */ 830#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */ 831#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */ 832#define URX_FIFO_FULL 0x8000 /* FIFO is Full */ 833 834/* 835 * UART Transmitter Register 836 */ 837#define UTX_ADDR 0xfffff906 838#define UTX WORD_REF(UTX_ADDR) 839 840#define UTX_TXDATA_ADDR 0xfffff907 841#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR) 842 843#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */ 844#define UTX_TXDATA_SHIFT 0 845#define UTX_CTS_DELTA 0x0100 /* CTS changed */ 846#define UTX_CTS_STAT 0x0200 /* CTS State */ 847#define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */ 848#define UTX_NOCTS 0x0800 /* Ignore CTS */ 849#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */ 850#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */ 851#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */ 852#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */ 853 854/* '328-compatible definitions */ 855#define UTX_CTS_STATUS UTX_CTS_STAT 856#define UTX_IGNORE_CTS UTX_NOCTS 857 858/* 859 * UART Miscellaneous Register 860 */ 861#define UMISC_ADDR 0xfffff908 862#define UMISC WORD_REF(UMISC_ADDR) 863 864#define UMISC_TX_POL 0x0004 /* Transmit Polarity */ 865#define UMISC_RX_POL 0x0008 /* Receive Polarity */ 866#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */ 867#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */ 868#define UMISC_RTS 0x0040 /* Set RTS status */ 869#define UMISC_RTSCONT 0x0080 /* Choose RTS control */ 870#define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */ 871#define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */ 872#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */ 873#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */ 874#define UMISC_CLKSRC 0x4000 /* Clock Source */ 875#define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */ 876 877/* 878 * UART Non-integer Prescaler Register 879 */ 880#define NIPR_ADDR 0xfffff90a 881#define NIPR WORD_REF(NIPR_ADDR) 882 883#define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */ 884#define NIPR_STEP_VALUE_SHIFT 0 885#define NIPR_SELECT_MASK 0x0700 /* Tap Selection */ 886#define NIPR_SELECT_SHIFT 8 887#define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */ 888 889 890/* generalization of uart control registers to support multiple ports: */ 891typedef struct { 892 volatile unsigned short int ustcnt; 893 volatile unsigned short int ubaud; 894 union { 895 volatile unsigned short int w; 896 struct { 897 volatile unsigned char status; 898 volatile unsigned char rxdata; 899 } b; 900 } urx; 901 union { 902 volatile unsigned short int w; 903 struct { 904 volatile unsigned char status; 905 volatile unsigned char txdata; 906 } b; 907 } utx; 908 volatile unsigned short int umisc; 909 volatile unsigned short int nipr; 910 volatile unsigned short int hmark; 911 volatile unsigned short int unused; 912} __attribute__((packed)) m68328_uart; 913 914 915 916 917/********** 918 * 919 * 0xFFFFFAxx -- LCD Controller 920 * 921 **********/ 922 923/* 924 * LCD Screen Starting Address Register 925 */ 926#define LSSA_ADDR 0xfffffa00 927#define LSSA LONG_REF(LSSA_ADDR) 928 929#define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */ 930 931/* 932 * LCD Virtual Page Width Register 933 */ 934#define LVPW_ADDR 0xfffffa05 935#define LVPW BYTE_REF(LVPW_ADDR) 936 937/* 938 * LCD Screen Width Register (not compatible with '328 !!!) 939 */ 940#define LXMAX_ADDR 0xfffffa08 941#define LXMAX WORD_REF(LXMAX_ADDR) 942 943#define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */ 944 945/* 946 * LCD Screen Height Register 947 */ 948#define LYMAX_ADDR 0xfffffa0a 949#define LYMAX WORD_REF(LYMAX_ADDR) 950 951#define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */ 952 953/* 954 * LCD Cursor X Position Register 955 */ 956#define LCXP_ADDR 0xfffffa18 957#define LCXP WORD_REF(LCXP_ADDR) 958 959#define LCXP_CC_MASK 0xc000 /* Cursor Control */ 960#define LCXP_CC_TRAMSPARENT 0x0000 961#define LCXP_CC_BLACK 0x4000 962#define LCXP_CC_REVERSED 0x8000 963#define LCXP_CC_WHITE 0xc000 964#define LCXP_CXP_MASK 0x02ff /* Cursor X position */ 965 966/* 967 * LCD Cursor Y Position Register 968 */ 969#define LCYP_ADDR 0xfffffa1a 970#define LCYP WORD_REF(LCYP_ADDR) 971 972#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */ 973 974/* 975 * LCD Cursor Width and Heigth Register 976 */ 977#define LCWCH_ADDR 0xfffffa1c 978#define LCWCH WORD_REF(LCWCH_ADDR) 979 980#define LCWCH_CH_MASK 0x001f /* Cursor Height */ 981#define LCWCH_CH_SHIFT 0 982#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */ 983#define LCWCH_CW_SHIFT 8 984 985/* 986 * LCD Blink Control Register 987 */ 988#define LBLKC_ADDR 0xfffffa1f 989#define LBLKC BYTE_REF(LBLKC_ADDR) 990 991#define LBLKC_BD_MASK 0x7f /* Blink Divisor */ 992#define LBLKC_BD_SHIFT 0 993#define LBLKC_BKEN 0x80 /* Blink Enabled */ 994 995/* 996 * LCD Panel Interface Configuration Register 997 */ 998#define LPICF_ADDR 0xfffffa20 999#define LPICF BYTE_REF(LPICF_ADDR) 1000 1001#define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */ 1002#define LPICF_GS_BW 0x00 1003#define LPICF_GS_GRAY_4 0x01 1004#define LPICF_GS_GRAY_16 0x02 1005#define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */ 1006#define LPICF_PBSIZ_1 0x00 1007#define LPICF_PBSIZ_2 0x04 1008#define LPICF_PBSIZ_4 0x08 1009 1010/* 1011 * LCD Polarity Configuration Register 1012 */ 1013#define LPOLCF_ADDR 0xfffffa21 1014#define LPOLCF BYTE_REF(LPOLCF_ADDR) 1015 1016#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */ 1017#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */ 1018#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */ 1019#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */ 1020 1021/* 1022 * LACD (LCD Alternate Crystal Direction) Rate Control Register 1023 */ 1024#define LACDRC_ADDR 0xfffffa23 1025#define LACDRC BYTE_REF(LACDRC_ADDR) 1026 1027#define LACDRC_ACDSLT 0x80 /* Signal Source Select */ 1028#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */ 1029#define LACDRC_ACD_SHIFT 0 1030 1031/* 1032 * LCD Pixel Clock Divider Register 1033 */ 1034#define LPXCD_ADDR 0xfffffa25 1035#define LPXCD BYTE_REF(LPXCD_ADDR) 1036 1037#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */ 1038#define LPXCD_PCD_SHIFT 0 1039 1040/* 1041 * LCD Clocking Control Register 1042 */ 1043#define LCKCON_ADDR 0xfffffa27 1044#define LCKCON BYTE_REF(LCKCON_ADDR) 1045 1046#define LCKCON_DWS_MASK 0x0f /* Display Wait-State */ 1047#define LCKCON_DWS_SHIFT 0 1048#define LCKCON_DWIDTH 0x40 /* Display Memory Width */ 1049#define LCKCON_LCDON 0x80 /* Enable LCD Controller */ 1050 1051/* '328-compatible definitions */ 1052#define LCKCON_DW_MASK LCKCON_DWS_MASK 1053#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT 1054 1055/* 1056 * LCD Refresh Rate Adjustment Register 1057 */ 1058#define LRRA_ADDR 0xfffffa29 1059#define LRRA BYTE_REF(LRRA_ADDR) 1060 1061/* 1062 * LCD Panning Offset Register 1063 */ 1064#define LPOSR_ADDR 0xfffffa2d 1065#define LPOSR BYTE_REF(LPOSR_ADDR) 1066 1067#define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */ 1068#define LPOSR_POS_SHIFT 0 1069 1070/* 1071 * LCD Frame Rate Control Modulation Register 1072 */ 1073#define LFRCM_ADDR 0xfffffa31 1074#define LFRCM BYTE_REF(LFRCM_ADDR) 1075 1076#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */ 1077#define LFRCM_YMOD_SHIFT 0 1078#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */ 1079#define LFRCM_XMOD_SHIFT 4 1080 1081/* 1082 * LCD Gray Palette Mapping Register 1083 */ 1084#define LGPMR_ADDR 0xfffffa33 1085#define LGPMR BYTE_REF(LGPMR_ADDR) 1086 1087#define LGPMR_G1_MASK 0x0f 1088#define LGPMR_G1_SHIFT 0 1089#define LGPMR_G2_MASK 0xf0 1090#define LGPMR_G2_SHIFT 4 1091 1092/* 1093 * PWM Contrast Control Register 1094 */ 1095#define PWMR_ADDR 0xfffffa36 1096#define PWMR WORD_REF(PWMR_ADDR) 1097 1098#define PWMR_PW_MASK 0x00ff /* Pulse Width */ 1099#define PWMR_PW_SHIFT 0 1100#define PWMR_CCPEN 0x0100 /* Contrast Control Enable */ 1101#define PWMR_SRC_MASK 0x0600 /* Input Clock Source */ 1102#define PWMR_SRC_LINE 0x0000 /* Line Pulse */ 1103#define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */ 1104#define PWMR_SRC_LCD 0x4000 /* LCD clock */ 1105 1106/********** 1107 * 1108 * 0xFFFFFBxx -- Real-Time Clock (RTC) 1109 * 1110 **********/ 1111 1112/* 1113 * RTC Hours Minutes and Seconds Register 1114 */ 1115#define RTCTIME_ADDR 0xfffffb00 1116#define RTCTIME LONG_REF(RTCTIME_ADDR) 1117 1118#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */ 1119#define RTCTIME_SECONDS_SHIFT 0 1120#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */ 1121#define RTCTIME_MINUTES_SHIFT 16 1122#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */ 1123#define RTCTIME_HOURS_SHIFT 24 1124 1125/* 1126 * RTC Alarm Register 1127 */ 1128#define RTCALRM_ADDR 0xfffffb04 1129#define RTCALRM LONG_REF(RTCALRM_ADDR) 1130 1131#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */ 1132#define RTCALRM_SECONDS_SHIFT 0 1133#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */ 1134#define RTCALRM_MINUTES_SHIFT 16 1135#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */ 1136#define RTCALRM_HOURS_SHIFT 24 1137 1138/* 1139 * Watchdog Timer Register 1140 */ 1141#define WATCHDOG_ADDR 0xfffffb0a 1142#define WATCHDOG WORD_REF(WATCHDOG_ADDR) 1143 1144#define WATCHDOG_EN 0x0001 /* Watchdog Enabled */ 1145#define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */ 1146#define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occurred */ 1147#define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */ 1148#define WATCHDOG_CNT_SHIFT 8 1149 1150/* 1151 * RTC Control Register 1152 */ 1153#define RTCCTL_ADDR 0xfffffb0c 1154#define RTCCTL WORD_REF(RTCCTL_ADDR) 1155 1156#define RTCCTL_XTL 0x0020 /* Crystal Selection */ 1157#define RTCCTL_EN 0x0080 /* RTC Enable */ 1158 1159/* '328-compatible definitions */ 1160#define RTCCTL_384 RTCCTL_XTL 1161#define RTCCTL_ENABLE RTCCTL_EN 1162 1163/* 1164 * RTC Interrupt Status Register 1165 */ 1166#define RTCISR_ADDR 0xfffffb0e 1167#define RTCISR WORD_REF(RTCISR_ADDR) 1168 1169#define RTCISR_SW 0x0001 /* Stopwatch timed out */ 1170#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */ 1171#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */ 1172#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */ 1173#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */ 1174#define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */ 1175#define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */ 1176#define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */ 1177#define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */ 1178#define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */ 1179#define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */ 1180#define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */ 1181#define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */ 1182#define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */ 1183 1184/* 1185 * RTC Interrupt Enable Register 1186 */ 1187#define RTCIENR_ADDR 0xfffffb10 1188#define RTCIENR WORD_REF(RTCIENR_ADDR) 1189 1190#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */ 1191#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */ 1192#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */ 1193#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */ 1194#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */ 1195#define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */ 1196#define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */ 1197#define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */ 1198#define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */ 1199#define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */ 1200#define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */ 1201#define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */ 1202#define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */ 1203#define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */ 1204 1205/* 1206 * Stopwatch Minutes Register 1207 */ 1208#define STPWCH_ADDR 0xfffffb12 1209#define STPWCH WORD_REF(STPWCH_ADDR) 1210 1211#define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */ 1212#define SPTWCH_CNT_SHIFT 0 1213 1214/* 1215 * RTC Day Count Register 1216 */ 1217#define DAYR_ADDR 0xfffffb1a 1218#define DAYR WORD_REF(DAYR_ADDR) 1219 1220#define DAYR_DAYS_MASK 0x1ff /* Day Setting */ 1221#define DAYR_DAYS_SHIFT 0 1222 1223/* 1224 * RTC Day Alarm Register 1225 */ 1226#define DAYALARM_ADDR 0xfffffb1c 1227#define DAYALARM WORD_REF(DAYALARM_ADDR) 1228 1229#define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */ 1230#define DAYALARM_DAYSAL_SHIFT 0 1231 1232/********** 1233 * 1234 * 0xFFFFFCxx -- DRAM Controller 1235 * 1236 **********/ 1237 1238/* 1239 * DRAM Memory Configuration Register 1240 */ 1241#define DRAMMC_ADDR 0xfffffc00 1242#define DRAMMC WORD_REF(DRAMMC_ADDR) 1243 1244#define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */ 1245#define DRAMMC_ROW12_PA10 0x0000 1246#define DRAMMC_ROW12_PA21 0x4000 1247#define DRAMMC_ROW12_PA23 0x8000 1248#define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */ 1249#define DRAMMC_ROW0_PA11 0x0000 1250#define DRAMMC_ROW0_PA22 0x1000 1251#define DRAMMC_ROW0_PA23 0x2000 1252#define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */ 1253#define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */ 1254#define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */ 1255#define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */ 1256#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */ 1257#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */ 1258#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */ 1259#define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */ 1260#define DRAMMC_REF_SHIFT 0 1261 1262/* 1263 * DRAM Control Register 1264 */ 1265#define DRAMC_ADDR 0xfffffc02 1266#define DRAMC WORD_REF(DRAMC_ADDR) 1267 1268#define DRAMC_DWE 0x0001 /* DRAM Write Enable */ 1269#define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */ 1270#define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */ 1271#define DRAMC_SLW 0x0008 /* Slow RAM */ 1272#define DRAMC_LSP 0x0010 /* Light Sleep */ 1273#define DRAMC_MSW 0x0020 /* Slow Multiplexing */ 1274#define DRAMC_WS_MASK 0x00c0 /* Wait-states */ 1275#define DRAMC_WS_SHIFT 6 1276#define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */ 1277#define DRAMC_PGSZ_SHIFT 8 1278#define DRAMC_PGSZ_256K 0x0000 1279#define DRAMC_PGSZ_512K 0x0100 1280#define DRAMC_PGSZ_1024K 0x0200 1281#define DRAMC_PGSZ_2048K 0x0300 1282#define DRAMC_EDO 0x0400 /* EDO DRAM */ 1283#define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */ 1284#define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */ 1285#define DRAMC_BC_SHIFT 12 1286#define DRAMC_RM 0x4000 /* Refresh Mode */ 1287#define DRAMC_EN 0x8000 /* DRAM Controller enable */ 1288 1289 1290/********** 1291 * 1292 * 0xFFFFFDxx -- In-Circuit Emulation (ICE) 1293 * 1294 **********/ 1295 1296/* 1297 * ICE Module Address Compare Register 1298 */ 1299#define ICEMACR_ADDR 0xfffffd00 1300#define ICEMACR LONG_REF(ICEMACR_ADDR) 1301 1302/* 1303 * ICE Module Address Mask Register 1304 */ 1305#define ICEMAMR_ADDR 0xfffffd04 1306#define ICEMAMR LONG_REF(ICEMAMR_ADDR) 1307 1308/* 1309 * ICE Module Control Compare Register 1310 */ 1311#define ICEMCCR_ADDR 0xfffffd08 1312#define ICEMCCR WORD_REF(ICEMCCR_ADDR) 1313 1314#define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */ 1315#define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */ 1316 1317/* 1318 * ICE Module Control Mask Register 1319 */ 1320#define ICEMCMR_ADDR 0xfffffd0a 1321#define ICEMCMR WORD_REF(ICEMCMR_ADDR) 1322 1323#define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */ 1324#define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */ 1325 1326/* 1327 * ICE Module Control Register 1328 */ 1329#define ICEMCR_ADDR 0xfffffd0c 1330#define ICEMCR WORD_REF(ICEMCR_ADDR) 1331 1332#define ICEMCR_CEN 0x0001 /* Compare Enable */ 1333#define ICEMCR_PBEN 0x0002 /* Program Break Enable */ 1334#define ICEMCR_SB 0x0004 /* Single Breakpoint */ 1335#define ICEMCR_HMDIS 0x0008 /* HardMap disable */ 1336#define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */ 1337 1338/* 1339 * ICE Module Status Register 1340 */ 1341#define ICEMSR_ADDR 0xfffffd0e 1342#define ICEMSR WORD_REF(ICEMSR_ADDR) 1343 1344#define ICEMSR_EMUEN 0x0001 /* Emulation Enable */ 1345#define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */ 1346#define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */ 1347#define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */ 1348 1349#endif /* _MC68VZ328_H_ */ 1350