1/* 2 * ata_piix.c - Intel PATA/SATA controllers 3 * 4 * Maintained by: Tejun Heo <tj@kernel.org> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * 9 * Copyright 2003-2005 Red Hat Inc 10 * Copyright 2003-2005 Jeff Garzik 11 * 12 * 13 * Copyright header from piix.c: 14 * 15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 17 * Copyright (C) 2003 Red Hat Inc 18 * 19 * 20 * This program is free software; you can redistribute it and/or modify 21 * it under the terms of the GNU General Public License as published by 22 * the Free Software Foundation; either version 2, or (at your option) 23 * any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; see the file COPYING. If not, write to 32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 33 * 34 * 35 * libata documentation is available via 'make {ps|pdf}docs', 36 * as Documentation/DocBook/libata.* 37 * 38 * Hardware documentation available at http://developer.intel.com/ 39 * 40 * Documentation 41 * Publicly available from Intel web site. Errata documentation 42 * is also publicly available. As an aide to anyone hacking on this 43 * driver the list of errata that are relevant is below, going back to 44 * PIIX4. Older device documentation is now a bit tricky to find. 45 * 46 * The chipsets all follow very much the same design. The original Triton 47 * series chipsets do _not_ support independent device timings, but this 48 * is fixed in Triton II. With the odd mobile exception the chips then 49 * change little except in gaining more modes until SATA arrives. This 50 * driver supports only the chips with independent timing (that is those 51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix 52 * for the early chip drivers. 53 * 54 * Errata of note: 55 * 56 * Unfixable 57 * PIIX4 errata #9 - Only on ultra obscure hw 58 * ICH3 errata #13 - Not observed to affect real hw 59 * by Intel 60 * 61 * Things we must deal with 62 * PIIX4 errata #10 - BM IDE hang with non UDMA 63 * (must stop/start dma to recover) 64 * 440MX errata #15 - As PIIX4 errata #10 65 * PIIX4 errata #15 - Must not read control registers 66 * during a PIO transfer 67 * 440MX errata #13 - As PIIX4 errata #15 68 * ICH2 errata #21 - DMA mode 0 doesn't work right 69 * ICH0/1 errata #55 - As ICH2 errata #21 70 * ICH2 spec c #9 - Extra operations needed to handle 71 * drive hotswap [NOT YET SUPPORTED] 72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary 73 * and must be dword aligned 74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 75 * ICH7 errata #16 - MWDMA1 timings are incorrect 76 * 77 * Should have been BIOS fixed: 78 * 450NX: errata #19 - DMA hangs on old 450NX 79 * 450NX: errata #20 - DMA hangs on old 450NX 80 * 450NX: errata #25 - Corruption with DMA on old 450NX 81 * ICH3 errata #15 - IDE deadlock under high load 82 * (BIOS must set dev 31 fn 0 bit 23) 83 * ICH3 errata #18 - Don't use native mode 84 */ 85 86#include <linux/kernel.h> 87#include <linux/module.h> 88#include <linux/pci.h> 89#include <linux/init.h> 90#include <linux/blkdev.h> 91#include <linux/delay.h> 92#include <linux/device.h> 93#include <linux/gfp.h> 94#include <scsi/scsi_host.h> 95#include <linux/libata.h> 96#include <linux/dmi.h> 97 98#define DRV_NAME "ata_piix" 99#define DRV_VERSION "2.13" 100 101enum { 102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 103 ICH5_PMR = 0x90, /* address map register */ 104 ICH5_PCS = 0x92, /* port control and status */ 105 PIIX_SIDPR_BAR = 5, 106 PIIX_SIDPR_LEN = 16, 107 PIIX_SIDPR_IDX = 0, 108 PIIX_SIDPR_DATA = 4, 109 110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ 111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ 112 113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, 114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, 115 116 PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/ 117 118 PIIX_80C_PRI = (1 << 5) | (1 << 4), 119 PIIX_80C_SEC = (1 << 7) | (1 << 6), 120 121 /* constants for mapping table */ 122 P0 = 0, /* port 0 */ 123 P1 = 1, /* port 1 */ 124 P2 = 2, /* port 2 */ 125 P3 = 3, /* port 3 */ 126 IDE = -1, /* IDE */ 127 NA = -2, /* not available */ 128 RV = -3, /* reserved */ 129 130 PIIX_AHCI_DEVICE = 6, 131 132 /* host->flags bits */ 133 PIIX_HOST_BROKEN_SUSPEND = (1 << 24), 134}; 135 136enum piix_controller_ids { 137 /* controller IDs */ 138 piix_pata_mwdma, /* PIIX3 MWDMA only */ 139 piix_pata_33, /* PIIX4 at 33Mhz */ 140 ich_pata_33, /* ICH up to UDMA 33 only */ 141 ich_pata_66, /* ICH up to 66 Mhz */ 142 ich_pata_100, /* ICH up to UDMA 100 */ 143 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/ 144 ich5_sata, 145 ich6_sata, 146 ich6m_sata, 147 ich8_sata, 148 ich8_2port_sata, 149 ich8m_apple_sata, /* locks up on second port enable */ 150 tolapai_sata, 151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ 152 ich8_sata_snb, 153 ich8_2port_sata_snb, 154 ich8_2port_sata_byt, 155}; 156 157struct piix_map_db { 158 const u32 mask; 159 const u16 port_enable; 160 const int map[][4]; 161}; 162 163struct piix_host_priv { 164 const int *map; 165 u32 saved_iocfg; 166 void __iomem *sidpr; 167}; 168 169static unsigned int in_module_init = 1; 170 171static const struct pci_device_id piix_pci_tbl[] = { 172 /* Intel PIIX3 for the 430HX etc */ 173 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, 174 /* VMware ICH4 */ 175 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw }, 176 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ 177 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ 178 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 179 /* Intel PIIX4 */ 180 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 181 /* Intel PIIX4 */ 182 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 183 /* Intel PIIX */ 184 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 185 /* Intel ICH (i810, i815, i840) UDMA 66*/ 186 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, 187 /* Intel ICH0 : UDMA 33*/ 188 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, 189 /* Intel ICH2M */ 190 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 191 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ 192 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 193 /* Intel ICH3M */ 194 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 195 /* Intel ICH3 (E7500/1) UDMA 100 */ 196 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 197 /* Intel ICH4-L */ 198 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 199 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ 200 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 201 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 202 /* Intel ICH5 */ 203 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 204 /* C-ICH (i810E2) */ 205 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 206 /* ESB (855GME/875P + 6300ESB) UDMA 100 */ 207 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 208 /* ICH6 (and 6) (i915) UDMA 100 */ 209 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 210 /* ICH7/7-R (i945, i975) UDMA 100*/ 211 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, 212 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, 213 /* ICH8 Mobile PATA Controller */ 214 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 215 216 /* SATA ports */ 217 218 /* 82801EB (ICH5) */ 219 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 220 /* 82801EB (ICH5) */ 221 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 222 /* 6300ESB (ICH5 variant with broken PCS present bits) */ 223 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 224 /* 6300ESB pretending RAID */ 225 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 226 /* 82801FB/FW (ICH6/ICH6W) */ 227 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 228 /* 82801FR/FRW (ICH6R/ICH6RW) */ 229 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 230 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented). 231 * Attach iff the controller is in IDE mode. */ 232 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 233 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata }, 234 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 235 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 236 /* 82801GBM/GHM (ICH7M, identical to ICH6M) */ 237 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata }, 238 /* Enterprise Southbridge 2 (631xESB/632xESB) */ 239 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 240 /* SATA Controller 1 IDE (ICH8) */ 241 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 242 /* SATA Controller 2 IDE (ICH8) */ 243 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 244 /* Mobile SATA Controller IDE (ICH8M), Apple */ 245 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, 246 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata }, 247 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata }, 248 /* Mobile SATA Controller IDE (ICH8M) */ 249 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 250 /* SATA Controller IDE (ICH9) */ 251 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 252 /* SATA Controller IDE (ICH9) */ 253 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 254 /* SATA Controller IDE (ICH9) */ 255 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 256 /* SATA Controller IDE (ICH9M) */ 257 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 258 /* SATA Controller IDE (ICH9M) */ 259 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 260 /* SATA Controller IDE (ICH9M) */ 261 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 262 /* SATA Controller IDE (Tolapai) */ 263 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata }, 264 /* SATA Controller IDE (ICH10) */ 265 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 266 /* SATA Controller IDE (ICH10) */ 267 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 268 /* SATA Controller IDE (ICH10) */ 269 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 270 /* SATA Controller IDE (ICH10) */ 271 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 272 /* SATA Controller IDE (PCH) */ 273 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 274 /* SATA Controller IDE (PCH) */ 275 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 276 /* SATA Controller IDE (PCH) */ 277 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 278 /* SATA Controller IDE (PCH) */ 279 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 280 /* SATA Controller IDE (PCH) */ 281 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 282 /* SATA Controller IDE (PCH) */ 283 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 284 /* SATA Controller IDE (CPT) */ 285 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 286 /* SATA Controller IDE (CPT) */ 287 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 288 /* SATA Controller IDE (CPT) */ 289 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 290 /* SATA Controller IDE (CPT) */ 291 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 292 /* SATA Controller IDE (PBG) */ 293 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 294 /* SATA Controller IDE (PBG) */ 295 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 296 /* SATA Controller IDE (Panther Point) */ 297 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 298 /* SATA Controller IDE (Panther Point) */ 299 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 300 /* SATA Controller IDE (Panther Point) */ 301 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 302 /* SATA Controller IDE (Panther Point) */ 303 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 304 /* SATA Controller IDE (Lynx Point) */ 305 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 306 /* SATA Controller IDE (Lynx Point) */ 307 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 308 /* SATA Controller IDE (Lynx Point) */ 309 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb }, 310 /* SATA Controller IDE (Lynx Point) */ 311 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 312 /* SATA Controller IDE (Lynx Point-LP) */ 313 { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 314 /* SATA Controller IDE (Lynx Point-LP) */ 315 { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 316 /* SATA Controller IDE (Lynx Point-LP) */ 317 { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 318 /* SATA Controller IDE (Lynx Point-LP) */ 319 { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 320 /* SATA Controller IDE (DH89xxCC) */ 321 { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 322 /* SATA Controller IDE (Avoton) */ 323 { 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 324 /* SATA Controller IDE (Avoton) */ 325 { 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 326 /* SATA Controller IDE (Avoton) */ 327 { 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 328 /* SATA Controller IDE (Avoton) */ 329 { 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 330 /* SATA Controller IDE (Wellsburg) */ 331 { 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 332 /* SATA Controller IDE (Wellsburg) */ 333 { 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb }, 334 /* SATA Controller IDE (Wellsburg) */ 335 { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 336 /* SATA Controller IDE (Wellsburg) */ 337 { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 338 /* SATA Controller IDE (BayTrail) */ 339 { 0x8086, 0x0F20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt }, 340 { 0x8086, 0x0F21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt }, 341 /* SATA Controller IDE (Coleto Creek) */ 342 { 0x8086, 0x23a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 343 /* SATA Controller IDE (9 Series) */ 344 { 0x8086, 0x8c88, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb }, 345 /* SATA Controller IDE (9 Series) */ 346 { 0x8086, 0x8c89, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb }, 347 /* SATA Controller IDE (9 Series) */ 348 { 0x8086, 0x8c80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 349 /* SATA Controller IDE (9 Series) */ 350 { 0x8086, 0x8c81, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 351 352 { } /* terminate list */ 353}; 354 355static const struct piix_map_db ich5_map_db = { 356 .mask = 0x7, 357 .port_enable = 0x3, 358 .map = { 359 /* PM PS SM SS MAP */ 360 { P0, NA, P1, NA }, /* 000b */ 361 { P1, NA, P0, NA }, /* 001b */ 362 { RV, RV, RV, RV }, 363 { RV, RV, RV, RV }, 364 { P0, P1, IDE, IDE }, /* 100b */ 365 { P1, P0, IDE, IDE }, /* 101b */ 366 { IDE, IDE, P0, P1 }, /* 110b */ 367 { IDE, IDE, P1, P0 }, /* 111b */ 368 }, 369}; 370 371static const struct piix_map_db ich6_map_db = { 372 .mask = 0x3, 373 .port_enable = 0xf, 374 .map = { 375 /* PM PS SM SS MAP */ 376 { P0, P2, P1, P3 }, /* 00b */ 377 { IDE, IDE, P1, P3 }, /* 01b */ 378 { P0, P2, IDE, IDE }, /* 10b */ 379 { RV, RV, RV, RV }, 380 }, 381}; 382 383static const struct piix_map_db ich6m_map_db = { 384 .mask = 0x3, 385 .port_enable = 0x5, 386 387 /* Map 01b isn't specified in the doc but some notebooks use 388 * it anyway. MAP 01b have been spotted on both ICH6M and 389 * ICH7M. 390 */ 391 .map = { 392 /* PM PS SM SS MAP */ 393 { P0, P2, NA, NA }, /* 00b */ 394 { IDE, IDE, P1, P3 }, /* 01b */ 395 { P0, P2, IDE, IDE }, /* 10b */ 396 { RV, RV, RV, RV }, 397 }, 398}; 399 400static const struct piix_map_db ich8_map_db = { 401 .mask = 0x3, 402 .port_enable = 0xf, 403 .map = { 404 /* PM PS SM SS MAP */ 405 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ 406 { RV, RV, RV, RV }, 407 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ 408 { RV, RV, RV, RV }, 409 }, 410}; 411 412static const struct piix_map_db ich8_2port_map_db = { 413 .mask = 0x3, 414 .port_enable = 0x3, 415 .map = { 416 /* PM PS SM SS MAP */ 417 { P0, NA, P1, NA }, /* 00b */ 418 { RV, RV, RV, RV }, /* 01b */ 419 { RV, RV, RV, RV }, /* 10b */ 420 { RV, RV, RV, RV }, 421 }, 422}; 423 424static const struct piix_map_db ich8m_apple_map_db = { 425 .mask = 0x3, 426 .port_enable = 0x1, 427 .map = { 428 /* PM PS SM SS MAP */ 429 { P0, NA, NA, NA }, /* 00b */ 430 { RV, RV, RV, RV }, 431 { P0, P2, IDE, IDE }, /* 10b */ 432 { RV, RV, RV, RV }, 433 }, 434}; 435 436static const struct piix_map_db tolapai_map_db = { 437 .mask = 0x3, 438 .port_enable = 0x3, 439 .map = { 440 /* PM PS SM SS MAP */ 441 { P0, NA, P1, NA }, /* 00b */ 442 { RV, RV, RV, RV }, /* 01b */ 443 { RV, RV, RV, RV }, /* 10b */ 444 { RV, RV, RV, RV }, 445 }, 446}; 447 448static const struct piix_map_db *piix_map_db_table[] = { 449 [ich5_sata] = &ich5_map_db, 450 [ich6_sata] = &ich6_map_db, 451 [ich6m_sata] = &ich6m_map_db, 452 [ich8_sata] = &ich8_map_db, 453 [ich8_2port_sata] = &ich8_2port_map_db, 454 [ich8m_apple_sata] = &ich8m_apple_map_db, 455 [tolapai_sata] = &tolapai_map_db, 456 [ich8_sata_snb] = &ich8_map_db, 457 [ich8_2port_sata_snb] = &ich8_2port_map_db, 458 [ich8_2port_sata_byt] = &ich8_2port_map_db, 459}; 460 461static struct pci_bits piix_enable_bits[] = { 462 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 463 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 464}; 465 466MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); 467MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); 468MODULE_LICENSE("GPL"); 469MODULE_DEVICE_TABLE(pci, piix_pci_tbl); 470MODULE_VERSION(DRV_VERSION); 471 472struct ich_laptop { 473 u16 device; 474 u16 subvendor; 475 u16 subdevice; 476}; 477 478/* 479 * List of laptops that use short cables rather than 80 wire 480 */ 481 482static const struct ich_laptop ich_laptop[] = { 483 /* devid, subvendor, subdev */ 484 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ 485 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ 486 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ 487 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */ 488 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 489 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ 490 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */ 491 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */ 492 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */ 493 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ 494 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */ 495 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */ 496 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ 497 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */ 498 /* end marker */ 499 { 0, } 500}; 501 502static int piix_port_start(struct ata_port *ap) 503{ 504 if (!(ap->flags & PIIX_FLAG_PIO16)) 505 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; 506 507 return ata_bmdma_port_start(ap); 508} 509 510/** 511 * ich_pata_cable_detect - Probe host controller cable detect info 512 * @ap: Port for which cable detect info is desired 513 * 514 * Read 80c cable indicator from ATA PCI device's PCI config 515 * register. This register is normally set by firmware (BIOS). 516 * 517 * LOCKING: 518 * None (inherited from caller). 519 */ 520 521static int ich_pata_cable_detect(struct ata_port *ap) 522{ 523 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 524 struct piix_host_priv *hpriv = ap->host->private_data; 525 const struct ich_laptop *lap = &ich_laptop[0]; 526 u8 mask; 527 528 /* Check for specials */ 529 while (lap->device) { 530 if (lap->device == pdev->device && 531 lap->subvendor == pdev->subsystem_vendor && 532 lap->subdevice == pdev->subsystem_device) 533 return ATA_CBL_PATA40_SHORT; 534 535 lap++; 536 } 537 538 /* check BIOS cable detect results */ 539 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; 540 if ((hpriv->saved_iocfg & mask) == 0) 541 return ATA_CBL_PATA40; 542 return ATA_CBL_PATA80; 543} 544 545/** 546 * piix_pata_prereset - prereset for PATA host controller 547 * @link: Target link 548 * @deadline: deadline jiffies for the operation 549 * 550 * LOCKING: 551 * None (inherited from caller). 552 */ 553static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) 554{ 555 struct ata_port *ap = link->ap; 556 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 557 558 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) 559 return -ENOENT; 560 return ata_sff_prereset(link, deadline); 561} 562 563static DEFINE_SPINLOCK(piix_lock); 564 565static void piix_set_timings(struct ata_port *ap, struct ata_device *adev, 566 u8 pio) 567{ 568 struct pci_dev *dev = to_pci_dev(ap->host->dev); 569 unsigned long flags; 570 unsigned int is_slave = (adev->devno != 0); 571 unsigned int master_port= ap->port_no ? 0x42 : 0x40; 572 unsigned int slave_port = 0x44; 573 u16 master_data; 574 u8 slave_data; 575 u8 udma_enable; 576 int control = 0; 577 578 /* 579 * See Intel Document 298600-004 for the timing programing rules 580 * for ICH controllers. 581 */ 582 583 static const /* ISP RTC */ 584 u8 timings[][2] = { { 0, 0 }, 585 { 0, 0 }, 586 { 1, 0 }, 587 { 2, 1 }, 588 { 2, 3 }, }; 589 590 if (pio >= 2) 591 control |= 1; /* TIME1 enable */ 592 if (ata_pio_need_iordy(adev)) 593 control |= 2; /* IE enable */ 594 /* Intel specifies that the PPE functionality is for disk only */ 595 if (adev->class == ATA_DEV_ATA) 596 control |= 4; /* PPE enable */ 597 /* 598 * If the drive MWDMA is faster than it can do PIO then 599 * we must force PIO into PIO0 600 */ 601 if (adev->pio_mode < XFER_PIO_0 + pio) 602 /* Enable DMA timing only */ 603 control |= 8; /* PIO cycles in PIO0 */ 604 605 spin_lock_irqsave(&piix_lock, flags); 606 607 /* PIO configuration clears DTE unconditionally. It will be 608 * programmed in set_dmamode which is guaranteed to be called 609 * after set_piomode if any DMA mode is available. 610 */ 611 pci_read_config_word(dev, master_port, &master_data); 612 if (is_slave) { 613 /* clear TIME1|IE1|PPE1|DTE1 */ 614 master_data &= 0xff0f; 615 /* enable PPE1, IE1 and TIME1 as needed */ 616 master_data |= (control << 4); 617 pci_read_config_byte(dev, slave_port, &slave_data); 618 slave_data &= (ap->port_no ? 0x0f : 0xf0); 619 /* Load the timing nibble for this slave */ 620 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) 621 << (ap->port_no ? 4 : 0); 622 } else { 623 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ 624 master_data &= 0xccf0; 625 /* Enable PPE, IE and TIME as appropriate */ 626 master_data |= control; 627 /* load ISP and RCT */ 628 master_data |= 629 (timings[pio][0] << 12) | 630 (timings[pio][1] << 8); 631 } 632 633 /* Enable SITRE (separate slave timing register) */ 634 master_data |= 0x4000; 635 pci_write_config_word(dev, master_port, master_data); 636 if (is_slave) 637 pci_write_config_byte(dev, slave_port, slave_data); 638 639 /* Ensure the UDMA bit is off - it will be turned back on if 640 UDMA is selected */ 641 642 if (ap->udma_mask) { 643 pci_read_config_byte(dev, 0x48, &udma_enable); 644 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); 645 pci_write_config_byte(dev, 0x48, udma_enable); 646 } 647 648 spin_unlock_irqrestore(&piix_lock, flags); 649} 650 651/** 652 * piix_set_piomode - Initialize host controller PATA PIO timings 653 * @ap: Port whose timings we are configuring 654 * @adev: Drive in question 655 * 656 * Set PIO mode for device, in host controller PCI config space. 657 * 658 * LOCKING: 659 * None (inherited from caller). 660 */ 661 662static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) 663{ 664 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0); 665} 666 667/** 668 * do_pata_set_dmamode - Initialize host controller PATA PIO timings 669 * @ap: Port whose timings we are configuring 670 * @adev: Drive in question 671 * @isich: set if the chip is an ICH device 672 * 673 * Set UDMA mode for device, in host controller PCI config space. 674 * 675 * LOCKING: 676 * None (inherited from caller). 677 */ 678 679static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) 680{ 681 struct pci_dev *dev = to_pci_dev(ap->host->dev); 682 unsigned long flags; 683 u8 speed = adev->dma_mode; 684 int devid = adev->devno + 2 * ap->port_no; 685 u8 udma_enable = 0; 686 687 if (speed >= XFER_UDMA_0) { 688 unsigned int udma = speed - XFER_UDMA_0; 689 u16 udma_timing; 690 u16 ideconf; 691 int u_clock, u_speed; 692 693 spin_lock_irqsave(&piix_lock, flags); 694 695 pci_read_config_byte(dev, 0x48, &udma_enable); 696 697 /* 698 * UDMA is handled by a combination of clock switching and 699 * selection of dividers 700 * 701 * Handy rule: Odd modes are UDMATIMx 01, even are 02 702 * except UDMA0 which is 00 703 */ 704 u_speed = min(2 - (udma & 1), udma); 705 if (udma == 5) 706 u_clock = 0x1000; /* 100Mhz */ 707 else if (udma > 2) 708 u_clock = 1; /* 66Mhz */ 709 else 710 u_clock = 0; /* 33Mhz */ 711 712 udma_enable |= (1 << devid); 713 714 /* Load the CT/RP selection */ 715 pci_read_config_word(dev, 0x4A, &udma_timing); 716 udma_timing &= ~(3 << (4 * devid)); 717 udma_timing |= u_speed << (4 * devid); 718 pci_write_config_word(dev, 0x4A, udma_timing); 719 720 if (isich) { 721 /* Select a 33/66/100Mhz clock */ 722 pci_read_config_word(dev, 0x54, &ideconf); 723 ideconf &= ~(0x1001 << devid); 724 ideconf |= u_clock << devid; 725 /* For ICH or later we should set bit 10 for better 726 performance (WR_PingPong_En) */ 727 pci_write_config_word(dev, 0x54, ideconf); 728 } 729 730 pci_write_config_byte(dev, 0x48, udma_enable); 731 732 spin_unlock_irqrestore(&piix_lock, flags); 733 } else { 734 /* MWDMA is driven by the PIO timings. */ 735 unsigned int mwdma = speed - XFER_MW_DMA_0; 736 const unsigned int needed_pio[3] = { 737 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 738 }; 739 int pio = needed_pio[mwdma] - XFER_PIO_0; 740 741 /* XFER_PIO_0 is never used currently */ 742 piix_set_timings(ap, adev, pio); 743 } 744} 745 746/** 747 * piix_set_dmamode - Initialize host controller PATA DMA timings 748 * @ap: Port whose timings we are configuring 749 * @adev: um 750 * 751 * Set MW/UDMA mode for device, in host controller PCI config space. 752 * 753 * LOCKING: 754 * None (inherited from caller). 755 */ 756 757static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) 758{ 759 do_pata_set_dmamode(ap, adev, 0); 760} 761 762/** 763 * ich_set_dmamode - Initialize host controller PATA DMA timings 764 * @ap: Port whose timings we are configuring 765 * @adev: um 766 * 767 * Set MW/UDMA mode for device, in host controller PCI config space. 768 * 769 * LOCKING: 770 * None (inherited from caller). 771 */ 772 773static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) 774{ 775 do_pata_set_dmamode(ap, adev, 1); 776} 777 778/* 779 * Serial ATA Index/Data Pair Superset Registers access 780 * 781 * Beginning from ICH8, there's a sane way to access SCRs using index 782 * and data register pair located at BAR5 which means that we have 783 * separate SCRs for master and slave. This is handled using libata 784 * slave_link facility. 785 */ 786static const int piix_sidx_map[] = { 787 [SCR_STATUS] = 0, 788 [SCR_ERROR] = 2, 789 [SCR_CONTROL] = 1, 790}; 791 792static void piix_sidpr_sel(struct ata_link *link, unsigned int reg) 793{ 794 struct ata_port *ap = link->ap; 795 struct piix_host_priv *hpriv = ap->host->private_data; 796 797 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg], 798 hpriv->sidpr + PIIX_SIDPR_IDX); 799} 800 801static int piix_sidpr_scr_read(struct ata_link *link, 802 unsigned int reg, u32 *val) 803{ 804 struct piix_host_priv *hpriv = link->ap->host->private_data; 805 806 if (reg >= ARRAY_SIZE(piix_sidx_map)) 807 return -EINVAL; 808 809 piix_sidpr_sel(link, reg); 810 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); 811 return 0; 812} 813 814static int piix_sidpr_scr_write(struct ata_link *link, 815 unsigned int reg, u32 val) 816{ 817 struct piix_host_priv *hpriv = link->ap->host->private_data; 818 819 if (reg >= ARRAY_SIZE(piix_sidx_map)) 820 return -EINVAL; 821 822 piix_sidpr_sel(link, reg); 823 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); 824 return 0; 825} 826 827static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 828 unsigned hints) 829{ 830 return sata_link_scr_lpm(link, policy, false); 831} 832 833static bool piix_irq_check(struct ata_port *ap) 834{ 835 if (unlikely(!ap->ioaddr.bmdma_addr)) 836 return false; 837 838 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR; 839} 840 841#ifdef CONFIG_PM_SLEEP 842static int piix_broken_suspend(void) 843{ 844 static const struct dmi_system_id sysids[] = { 845 { 846 .ident = "TECRA M3", 847 .matches = { 848 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 849 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), 850 }, 851 }, 852 { 853 .ident = "TECRA M3", 854 .matches = { 855 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 856 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), 857 }, 858 }, 859 { 860 .ident = "TECRA M4", 861 .matches = { 862 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 863 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), 864 }, 865 }, 866 { 867 .ident = "TECRA M4", 868 .matches = { 869 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 870 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"), 871 }, 872 }, 873 { 874 .ident = "TECRA M5", 875 .matches = { 876 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 877 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), 878 }, 879 }, 880 { 881 .ident = "TECRA M6", 882 .matches = { 883 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 884 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), 885 }, 886 }, 887 { 888 .ident = "TECRA M7", 889 .matches = { 890 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 891 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), 892 }, 893 }, 894 { 895 .ident = "TECRA A8", 896 .matches = { 897 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 898 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), 899 }, 900 }, 901 { 902 .ident = "Satellite R20", 903 .matches = { 904 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 905 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), 906 }, 907 }, 908 { 909 .ident = "Satellite R25", 910 .matches = { 911 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 912 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), 913 }, 914 }, 915 { 916 .ident = "Satellite U200", 917 .matches = { 918 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 919 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), 920 }, 921 }, 922 { 923 .ident = "Satellite U200", 924 .matches = { 925 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 926 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), 927 }, 928 }, 929 { 930 .ident = "Satellite Pro U200", 931 .matches = { 932 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 933 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), 934 }, 935 }, 936 { 937 .ident = "Satellite U205", 938 .matches = { 939 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 940 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), 941 }, 942 }, 943 { 944 .ident = "SATELLITE U205", 945 .matches = { 946 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 947 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), 948 }, 949 }, 950 { 951 .ident = "Satellite Pro A120", 952 .matches = { 953 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 954 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"), 955 }, 956 }, 957 { 958 .ident = "Portege M500", 959 .matches = { 960 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 961 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), 962 }, 963 }, 964 { 965 .ident = "VGN-BX297XP", 966 .matches = { 967 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"), 968 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"), 969 }, 970 }, 971 972 { } /* terminate list */ 973 }; 974 static const char *oemstrs[] = { 975 "Tecra M3,", 976 }; 977 int i; 978 979 if (dmi_check_system(sysids)) 980 return 1; 981 982 for (i = 0; i < ARRAY_SIZE(oemstrs); i++) 983 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) 984 return 1; 985 986 /* TECRA M4 sometimes forgets its identify and reports bogus 987 * DMI information. As the bogus information is a bit 988 * generic, match as many entries as possible. This manual 989 * matching is necessary because dmi_system_id.matches is 990 * limited to four entries. 991 */ 992 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") && 993 dmi_match(DMI_PRODUCT_NAME, "000000") && 994 dmi_match(DMI_PRODUCT_VERSION, "000000") && 995 dmi_match(DMI_PRODUCT_SERIAL, "000000") && 996 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") && 997 dmi_match(DMI_BOARD_NAME, "Portable PC") && 998 dmi_match(DMI_BOARD_VERSION, "Version A0")) 999 return 1; 1000 1001 return 0; 1002} 1003 1004static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 1005{ 1006 struct ata_host *host = pci_get_drvdata(pdev); 1007 unsigned long flags; 1008 int rc = 0; 1009 1010 rc = ata_host_suspend(host, mesg); 1011 if (rc) 1012 return rc; 1013 1014 /* Some braindamaged ACPI suspend implementations expect the 1015 * controller to be awake on entry; otherwise, it burns cpu 1016 * cycles and power trying to do something to the sleeping 1017 * beauty. 1018 */ 1019 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) { 1020 pci_save_state(pdev); 1021 1022 /* mark its power state as "unknown", since we don't 1023 * know if e.g. the BIOS will change its device state 1024 * when we suspend. 1025 */ 1026 if (pdev->current_state == PCI_D0) 1027 pdev->current_state = PCI_UNKNOWN; 1028 1029 /* tell resume that it's waking up from broken suspend */ 1030 spin_lock_irqsave(&host->lock, flags); 1031 host->flags |= PIIX_HOST_BROKEN_SUSPEND; 1032 spin_unlock_irqrestore(&host->lock, flags); 1033 } else 1034 ata_pci_device_do_suspend(pdev, mesg); 1035 1036 return 0; 1037} 1038 1039static int piix_pci_device_resume(struct pci_dev *pdev) 1040{ 1041 struct ata_host *host = pci_get_drvdata(pdev); 1042 unsigned long flags; 1043 int rc; 1044 1045 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { 1046 spin_lock_irqsave(&host->lock, flags); 1047 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; 1048 spin_unlock_irqrestore(&host->lock, flags); 1049 1050 pci_set_power_state(pdev, PCI_D0); 1051 pci_restore_state(pdev); 1052 1053 /* PCI device wasn't disabled during suspend. Use 1054 * pci_reenable_device() to avoid affecting the enable 1055 * count. 1056 */ 1057 rc = pci_reenable_device(pdev); 1058 if (rc) 1059 dev_err(&pdev->dev, 1060 "failed to enable device after resume (%d)\n", 1061 rc); 1062 } else 1063 rc = ata_pci_device_do_resume(pdev); 1064 1065 if (rc == 0) 1066 ata_host_resume(host); 1067 1068 return rc; 1069} 1070#endif 1071 1072static u8 piix_vmw_bmdma_status(struct ata_port *ap) 1073{ 1074 return ata_bmdma_status(ap) & ~ATA_DMA_ERR; 1075} 1076 1077static struct scsi_host_template piix_sht = { 1078 ATA_BMDMA_SHT(DRV_NAME), 1079}; 1080 1081static struct ata_port_operations piix_sata_ops = { 1082 .inherits = &ata_bmdma32_port_ops, 1083 .sff_irq_check = piix_irq_check, 1084 .port_start = piix_port_start, 1085}; 1086 1087static struct ata_port_operations piix_pata_ops = { 1088 .inherits = &piix_sata_ops, 1089 .cable_detect = ata_cable_40wire, 1090 .set_piomode = piix_set_piomode, 1091 .set_dmamode = piix_set_dmamode, 1092 .prereset = piix_pata_prereset, 1093}; 1094 1095static struct ata_port_operations piix_vmw_ops = { 1096 .inherits = &piix_pata_ops, 1097 .bmdma_status = piix_vmw_bmdma_status, 1098}; 1099 1100static struct ata_port_operations ich_pata_ops = { 1101 .inherits = &piix_pata_ops, 1102 .cable_detect = ich_pata_cable_detect, 1103 .set_dmamode = ich_set_dmamode, 1104}; 1105 1106static struct device_attribute *piix_sidpr_shost_attrs[] = { 1107 &dev_attr_link_power_management_policy, 1108 NULL 1109}; 1110 1111static struct scsi_host_template piix_sidpr_sht = { 1112 ATA_BMDMA_SHT(DRV_NAME), 1113 .shost_attrs = piix_sidpr_shost_attrs, 1114}; 1115 1116static struct ata_port_operations piix_sidpr_sata_ops = { 1117 .inherits = &piix_sata_ops, 1118 .hardreset = sata_std_hardreset, 1119 .scr_read = piix_sidpr_scr_read, 1120 .scr_write = piix_sidpr_scr_write, 1121 .set_lpm = piix_sidpr_set_lpm, 1122}; 1123 1124static struct ata_port_info piix_port_info[] = { 1125 [piix_pata_mwdma] = /* PIIX3 MWDMA only */ 1126 { 1127 .flags = PIIX_PATA_FLAGS, 1128 .pio_mask = ATA_PIO4, 1129 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 1130 .port_ops = &piix_pata_ops, 1131 }, 1132 1133 [piix_pata_33] = /* PIIX4 at 33MHz */ 1134 { 1135 .flags = PIIX_PATA_FLAGS, 1136 .pio_mask = ATA_PIO4, 1137 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 1138 .udma_mask = ATA_UDMA2, 1139 .port_ops = &piix_pata_ops, 1140 }, 1141 1142 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ 1143 { 1144 .flags = PIIX_PATA_FLAGS, 1145 .pio_mask = ATA_PIO4, 1146 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */ 1147 .udma_mask = ATA_UDMA2, 1148 .port_ops = &ich_pata_ops, 1149 }, 1150 1151 [ich_pata_66] = /* ICH controllers up to 66MHz */ 1152 { 1153 .flags = PIIX_PATA_FLAGS, 1154 .pio_mask = ATA_PIO4, 1155 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */ 1156 .udma_mask = ATA_UDMA4, 1157 .port_ops = &ich_pata_ops, 1158 }, 1159 1160 [ich_pata_100] = 1161 { 1162 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 1163 .pio_mask = ATA_PIO4, 1164 .mwdma_mask = ATA_MWDMA12_ONLY, 1165 .udma_mask = ATA_UDMA5, 1166 .port_ops = &ich_pata_ops, 1167 }, 1168 1169 [ich_pata_100_nomwdma1] = 1170 { 1171 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 1172 .pio_mask = ATA_PIO4, 1173 .mwdma_mask = ATA_MWDMA2_ONLY, 1174 .udma_mask = ATA_UDMA5, 1175 .port_ops = &ich_pata_ops, 1176 }, 1177 1178 [ich5_sata] = 1179 { 1180 .flags = PIIX_SATA_FLAGS, 1181 .pio_mask = ATA_PIO4, 1182 .mwdma_mask = ATA_MWDMA2, 1183 .udma_mask = ATA_UDMA6, 1184 .port_ops = &piix_sata_ops, 1185 }, 1186 1187 [ich6_sata] = 1188 { 1189 .flags = PIIX_SATA_FLAGS, 1190 .pio_mask = ATA_PIO4, 1191 .mwdma_mask = ATA_MWDMA2, 1192 .udma_mask = ATA_UDMA6, 1193 .port_ops = &piix_sata_ops, 1194 }, 1195 1196 [ich6m_sata] = 1197 { 1198 .flags = PIIX_SATA_FLAGS, 1199 .pio_mask = ATA_PIO4, 1200 .mwdma_mask = ATA_MWDMA2, 1201 .udma_mask = ATA_UDMA6, 1202 .port_ops = &piix_sata_ops, 1203 }, 1204 1205 [ich8_sata] = 1206 { 1207 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 1208 .pio_mask = ATA_PIO4, 1209 .mwdma_mask = ATA_MWDMA2, 1210 .udma_mask = ATA_UDMA6, 1211 .port_ops = &piix_sata_ops, 1212 }, 1213 1214 [ich8_2port_sata] = 1215 { 1216 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 1217 .pio_mask = ATA_PIO4, 1218 .mwdma_mask = ATA_MWDMA2, 1219 .udma_mask = ATA_UDMA6, 1220 .port_ops = &piix_sata_ops, 1221 }, 1222 1223 [tolapai_sata] = 1224 { 1225 .flags = PIIX_SATA_FLAGS, 1226 .pio_mask = ATA_PIO4, 1227 .mwdma_mask = ATA_MWDMA2, 1228 .udma_mask = ATA_UDMA6, 1229 .port_ops = &piix_sata_ops, 1230 }, 1231 1232 [ich8m_apple_sata] = 1233 { 1234 .flags = PIIX_SATA_FLAGS, 1235 .pio_mask = ATA_PIO4, 1236 .mwdma_mask = ATA_MWDMA2, 1237 .udma_mask = ATA_UDMA6, 1238 .port_ops = &piix_sata_ops, 1239 }, 1240 1241 [piix_pata_vmw] = 1242 { 1243 .flags = PIIX_PATA_FLAGS, 1244 .pio_mask = ATA_PIO4, 1245 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 1246 .udma_mask = ATA_UDMA2, 1247 .port_ops = &piix_vmw_ops, 1248 }, 1249 1250 /* 1251 * some Sandybridge chipsets have broken 32 mode up to now, 1252 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592 1253 */ 1254 [ich8_sata_snb] = 1255 { 1256 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16, 1257 .pio_mask = ATA_PIO4, 1258 .mwdma_mask = ATA_MWDMA2, 1259 .udma_mask = ATA_UDMA6, 1260 .port_ops = &piix_sata_ops, 1261 }, 1262 1263 [ich8_2port_sata_snb] = 1264 { 1265 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR 1266 | PIIX_FLAG_PIO16, 1267 .pio_mask = ATA_PIO4, 1268 .mwdma_mask = ATA_MWDMA2, 1269 .udma_mask = ATA_UDMA6, 1270 .port_ops = &piix_sata_ops, 1271 }, 1272 1273 [ich8_2port_sata_byt] = 1274 { 1275 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16, 1276 .pio_mask = ATA_PIO4, 1277 .mwdma_mask = ATA_MWDMA2, 1278 .udma_mask = ATA_UDMA6, 1279 .port_ops = &piix_sata_ops, 1280 }, 1281 1282}; 1283 1284#define AHCI_PCI_BAR 5 1285#define AHCI_GLOBAL_CTL 0x04 1286#define AHCI_ENABLE (1 << 31) 1287static int piix_disable_ahci(struct pci_dev *pdev) 1288{ 1289 void __iomem *mmio; 1290 u32 tmp; 1291 int rc = 0; 1292 1293 /* BUG: pci_enable_device has not yet been called. This 1294 * works because this device is usually set up by BIOS. 1295 */ 1296 1297 if (!pci_resource_start(pdev, AHCI_PCI_BAR) || 1298 !pci_resource_len(pdev, AHCI_PCI_BAR)) 1299 return 0; 1300 1301 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); 1302 if (!mmio) 1303 return -ENOMEM; 1304 1305 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1306 if (tmp & AHCI_ENABLE) { 1307 tmp &= ~AHCI_ENABLE; 1308 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); 1309 1310 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1311 if (tmp & AHCI_ENABLE) 1312 rc = -EIO; 1313 } 1314 1315 pci_iounmap(pdev, mmio); 1316 return rc; 1317} 1318 1319/** 1320 * piix_check_450nx_errata - Check for problem 450NX setup 1321 * @ata_dev: the PCI device to check 1322 * 1323 * Check for the present of 450NX errata #19 and errata #25. If 1324 * they are found return an error code so we can turn off DMA 1325 */ 1326 1327static int piix_check_450nx_errata(struct pci_dev *ata_dev) 1328{ 1329 struct pci_dev *pdev = NULL; 1330 u16 cfg; 1331 int no_piix_dma = 0; 1332 1333 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { 1334 /* Look for 450NX PXB. Check for problem configurations 1335 A PCI quirk checks bit 6 already */ 1336 pci_read_config_word(pdev, 0x41, &cfg); 1337 /* Only on the original revision: IDE DMA can hang */ 1338 if (pdev->revision == 0x00) 1339 no_piix_dma = 1; 1340 /* On all revisions below 5 PXB bus lock must be disabled for IDE */ 1341 else if (cfg & (1<<14) && pdev->revision < 5) 1342 no_piix_dma = 2; 1343 } 1344 if (no_piix_dma) 1345 dev_warn(&ata_dev->dev, 1346 "450NX errata present, disabling IDE DMA%s\n", 1347 no_piix_dma == 2 ? " - a BIOS update may resolve this" 1348 : ""); 1349 1350 return no_piix_dma; 1351} 1352 1353static void piix_init_pcs(struct ata_host *host, 1354 const struct piix_map_db *map_db) 1355{ 1356 struct pci_dev *pdev = to_pci_dev(host->dev); 1357 u16 pcs, new_pcs; 1358 1359 pci_read_config_word(pdev, ICH5_PCS, &pcs); 1360 1361 new_pcs = pcs | map_db->port_enable; 1362 1363 if (new_pcs != pcs) { 1364 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); 1365 pci_write_config_word(pdev, ICH5_PCS, new_pcs); 1366 msleep(150); 1367 } 1368} 1369 1370static const int *piix_init_sata_map(struct pci_dev *pdev, 1371 struct ata_port_info *pinfo, 1372 const struct piix_map_db *map_db) 1373{ 1374 const int *map; 1375 int i, invalid_map = 0; 1376 u8 map_value; 1377 char buf[32]; 1378 char *p = buf, *end = buf + sizeof(buf); 1379 1380 pci_read_config_byte(pdev, ICH5_PMR, &map_value); 1381 1382 map = map_db->map[map_value & map_db->mask]; 1383 1384 for (i = 0; i < 4; i++) { 1385 switch (map[i]) { 1386 case RV: 1387 invalid_map = 1; 1388 p += scnprintf(p, end - p, " XX"); 1389 break; 1390 1391 case NA: 1392 p += scnprintf(p, end - p, " --"); 1393 break; 1394 1395 case IDE: 1396 WARN_ON((i & 1) || map[i + 1] != IDE); 1397 pinfo[i / 2] = piix_port_info[ich_pata_100]; 1398 i++; 1399 p += scnprintf(p, end - p, " IDE IDE"); 1400 break; 1401 1402 default: 1403 p += scnprintf(p, end - p, " P%d", map[i]); 1404 if (i & 1) 1405 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; 1406 break; 1407 } 1408 } 1409 dev_info(&pdev->dev, "MAP [%s ]\n", buf); 1410 1411 if (invalid_map) 1412 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value); 1413 1414 return map; 1415} 1416 1417static bool piix_no_sidpr(struct ata_host *host) 1418{ 1419 struct pci_dev *pdev = to_pci_dev(host->dev); 1420 1421 /* 1422 * Samsung DB-P70 only has three ATA ports exposed and 1423 * curiously the unconnected first port reports link online 1424 * while not responding to SRST protocol causing excessive 1425 * detection delay. 1426 * 1427 * Unfortunately, the system doesn't carry enough DMI 1428 * information to identify the machine but does have subsystem 1429 * vendor and device set. As it's unclear whether the 1430 * subsystem vendor/device is used only for this specific 1431 * board, the port can't be disabled solely with the 1432 * information; however, turning off SIDPR access works around 1433 * the problem. Turn it off. 1434 * 1435 * This problem is reported in bnc#441240. 1436 * 1437 * https://bugzilla.novell.com/show_bug.cgi?id=441420 1438 */ 1439 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 && 1440 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG && 1441 pdev->subsystem_device == 0xb049) { 1442 dev_warn(host->dev, 1443 "Samsung DB-P70 detected, disabling SIDPR\n"); 1444 return true; 1445 } 1446 1447 return false; 1448} 1449 1450static int piix_init_sidpr(struct ata_host *host) 1451{ 1452 struct pci_dev *pdev = to_pci_dev(host->dev); 1453 struct piix_host_priv *hpriv = host->private_data; 1454 struct ata_link *link0 = &host->ports[0]->link; 1455 u32 scontrol; 1456 int i, rc; 1457 1458 /* check for availability */ 1459 for (i = 0; i < 4; i++) 1460 if (hpriv->map[i] == IDE) 1461 return 0; 1462 1463 /* is it blacklisted? */ 1464 if (piix_no_sidpr(host)) 1465 return 0; 1466 1467 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) 1468 return 0; 1469 1470 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || 1471 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN) 1472 return 0; 1473 1474 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME)) 1475 return 0; 1476 1477 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; 1478 1479 /* SCR access via SIDPR doesn't work on some configurations. 1480 * Give it a test drive by inhibiting power save modes which 1481 * we'll do anyway. 1482 */ 1483 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); 1484 1485 /* if IPM is already 3, SCR access is probably working. Don't 1486 * un-inhibit power save modes as BIOS might have inhibited 1487 * them for a reason. 1488 */ 1489 if ((scontrol & 0xf00) != 0x300) { 1490 scontrol |= 0x300; 1491 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol); 1492 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); 1493 1494 if ((scontrol & 0xf00) != 0x300) { 1495 dev_info(host->dev, 1496 "SCR access via SIDPR is available but doesn't work\n"); 1497 return 0; 1498 } 1499 } 1500 1501 /* okay, SCRs available, set ops and ask libata for slave_link */ 1502 for (i = 0; i < 2; i++) { 1503 struct ata_port *ap = host->ports[i]; 1504 1505 ap->ops = &piix_sidpr_sata_ops; 1506 1507 if (ap->flags & ATA_FLAG_SLAVE_POSS) { 1508 rc = ata_slave_link_init(ap); 1509 if (rc) 1510 return rc; 1511 } 1512 } 1513 1514 return 0; 1515} 1516 1517static void piix_iocfg_bit18_quirk(struct ata_host *host) 1518{ 1519 static const struct dmi_system_id sysids[] = { 1520 { 1521 /* Clevo M570U sets IOCFG bit 18 if the cdrom 1522 * isn't used to boot the system which 1523 * disables the channel. 1524 */ 1525 .ident = "M570U", 1526 .matches = { 1527 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), 1528 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), 1529 }, 1530 }, 1531 1532 { } /* terminate list */ 1533 }; 1534 struct pci_dev *pdev = to_pci_dev(host->dev); 1535 struct piix_host_priv *hpriv = host->private_data; 1536 1537 if (!dmi_check_system(sysids)) 1538 return; 1539 1540 /* The datasheet says that bit 18 is NOOP but certain systems 1541 * seem to use it to disable a channel. Clear the bit on the 1542 * affected systems. 1543 */ 1544 if (hpriv->saved_iocfg & (1 << 18)) { 1545 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n"); 1546 pci_write_config_dword(pdev, PIIX_IOCFG, 1547 hpriv->saved_iocfg & ~(1 << 18)); 1548 } 1549} 1550 1551static bool piix_broken_system_poweroff(struct pci_dev *pdev) 1552{ 1553 static const struct dmi_system_id broken_systems[] = { 1554 { 1555 .ident = "HP Compaq 2510p", 1556 .matches = { 1557 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1558 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"), 1559 }, 1560 /* PCI slot number of the controller */ 1561 .driver_data = (void *)0x1FUL, 1562 }, 1563 { 1564 .ident = "HP Compaq nc6000", 1565 .matches = { 1566 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1567 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"), 1568 }, 1569 /* PCI slot number of the controller */ 1570 .driver_data = (void *)0x1FUL, 1571 }, 1572 1573 { } /* terminate list */ 1574 }; 1575 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1576 1577 if (dmi) { 1578 unsigned long slot = (unsigned long)dmi->driver_data; 1579 /* apply the quirk only to on-board controllers */ 1580 return slot == PCI_SLOT(pdev->devfn); 1581 } 1582 1583 return false; 1584} 1585 1586static int prefer_ms_hyperv = 1; 1587module_param(prefer_ms_hyperv, int, 0); 1588MODULE_PARM_DESC(prefer_ms_hyperv, 1589 "Prefer Hyper-V paravirtualization drivers instead of ATA, " 1590 "0 - Use ATA drivers, " 1591 "1 (Default) - Use the paravirtualization drivers."); 1592 1593static void piix_ignore_devices_quirk(struct ata_host *host) 1594{ 1595#if IS_ENABLED(CONFIG_HYPERV_STORAGE) 1596 static const struct dmi_system_id ignore_hyperv[] = { 1597 { 1598 /* On Hyper-V hypervisors the disks are exposed on 1599 * both the emulated SATA controller and on the 1600 * paravirtualised drivers. The CD/DVD devices 1601 * are only exposed on the emulated controller. 1602 * Request we ignore ATA devices on this host. 1603 */ 1604 .ident = "Hyper-V Virtual Machine", 1605 .matches = { 1606 DMI_MATCH(DMI_SYS_VENDOR, 1607 "Microsoft Corporation"), 1608 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"), 1609 }, 1610 }, 1611 { } /* terminate list */ 1612 }; 1613 static const struct dmi_system_id allow_virtual_pc[] = { 1614 { 1615 /* In MS Virtual PC guests the DMI ident is nearly 1616 * identical to a Hyper-V guest. One difference is the 1617 * product version which is used here to identify 1618 * a Virtual PC guest. This entry allows ata_piix to 1619 * drive the emulated hardware. 1620 */ 1621 .ident = "MS Virtual PC 2007", 1622 .matches = { 1623 DMI_MATCH(DMI_SYS_VENDOR, 1624 "Microsoft Corporation"), 1625 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"), 1626 DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"), 1627 }, 1628 }, 1629 { } /* terminate list */ 1630 }; 1631 const struct dmi_system_id *ignore = dmi_first_match(ignore_hyperv); 1632 const struct dmi_system_id *allow = dmi_first_match(allow_virtual_pc); 1633 1634 if (ignore && !allow && prefer_ms_hyperv) { 1635 host->flags |= ATA_HOST_IGNORE_ATA; 1636 dev_info(host->dev, "%s detected, ATA device ignore set\n", 1637 ignore->ident); 1638 } 1639#endif 1640} 1641 1642/** 1643 * piix_init_one - Register PIIX ATA PCI device with kernel services 1644 * @pdev: PCI device to register 1645 * @ent: Entry in piix_pci_tbl matching with @pdev 1646 * 1647 * Called from kernel PCI layer. We probe for combined mode (sigh), 1648 * and then hand over control to libata, for it to do the rest. 1649 * 1650 * LOCKING: 1651 * Inherited from PCI layer (may sleep). 1652 * 1653 * RETURNS: 1654 * Zero on success, or -ERRNO value. 1655 */ 1656 1657static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1658{ 1659 struct device *dev = &pdev->dev; 1660 struct ata_port_info port_info[2]; 1661 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; 1662 struct scsi_host_template *sht = &piix_sht; 1663 unsigned long port_flags; 1664 struct ata_host *host; 1665 struct piix_host_priv *hpriv; 1666 int rc; 1667 1668 ata_print_version_once(&pdev->dev, DRV_VERSION); 1669 1670 /* no hotplugging support for later devices (FIXME) */ 1671 if (!in_module_init && ent->driver_data >= ich5_sata) 1672 return -ENODEV; 1673 1674 if (piix_broken_system_poweroff(pdev)) { 1675 piix_port_info[ent->driver_data].flags |= 1676 ATA_FLAG_NO_POWEROFF_SPINDOWN | 1677 ATA_FLAG_NO_HIBERNATE_SPINDOWN; 1678 dev_info(&pdev->dev, "quirky BIOS, skipping spindown " 1679 "on poweroff and hibernation\n"); 1680 } 1681 1682 port_info[0] = piix_port_info[ent->driver_data]; 1683 port_info[1] = piix_port_info[ent->driver_data]; 1684 1685 port_flags = port_info[0].flags; 1686 1687 /* enable device and prepare host */ 1688 rc = pcim_enable_device(pdev); 1689 if (rc) 1690 return rc; 1691 1692 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1693 if (!hpriv) 1694 return -ENOMEM; 1695 1696 /* Save IOCFG, this will be used for cable detection, quirk 1697 * detection and restoration on detach. This is necessary 1698 * because some ACPI implementations mess up cable related 1699 * bits on _STM. Reported on kernel bz#11879. 1700 */ 1701 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg); 1702 1703 /* ICH6R may be driven by either ata_piix or ahci driver 1704 * regardless of BIOS configuration. Make sure AHCI mode is 1705 * off. 1706 */ 1707 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { 1708 rc = piix_disable_ahci(pdev); 1709 if (rc) 1710 return rc; 1711 } 1712 1713 /* SATA map init can change port_info, do it before prepping host */ 1714 if (port_flags & ATA_FLAG_SATA) 1715 hpriv->map = piix_init_sata_map(pdev, port_info, 1716 piix_map_db_table[ent->driver_data]); 1717 1718 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); 1719 if (rc) 1720 return rc; 1721 host->private_data = hpriv; 1722 1723 /* initialize controller */ 1724 if (port_flags & ATA_FLAG_SATA) { 1725 piix_init_pcs(host, piix_map_db_table[ent->driver_data]); 1726 rc = piix_init_sidpr(host); 1727 if (rc) 1728 return rc; 1729 if (host->ports[0]->ops == &piix_sidpr_sata_ops) 1730 sht = &piix_sidpr_sht; 1731 } 1732 1733 /* apply IOCFG bit18 quirk */ 1734 piix_iocfg_bit18_quirk(host); 1735 1736 /* On ICH5, some BIOSen disable the interrupt using the 1737 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. 1738 * On ICH6, this bit has the same effect, but only when 1739 * MSI is disabled (and it is disabled, as we don't use 1740 * message-signalled interrupts currently). 1741 */ 1742 if (port_flags & PIIX_FLAG_CHECKINTR) 1743 pci_intx(pdev, 1); 1744 1745 if (piix_check_450nx_errata(pdev)) { 1746 /* This writes into the master table but it does not 1747 really matter for this errata as we will apply it to 1748 all the PIIX devices on the board */ 1749 host->ports[0]->mwdma_mask = 0; 1750 host->ports[0]->udma_mask = 0; 1751 host->ports[1]->mwdma_mask = 0; 1752 host->ports[1]->udma_mask = 0; 1753 } 1754 host->flags |= ATA_HOST_PARALLEL_SCAN; 1755 1756 /* Allow hosts to specify device types to ignore when scanning. */ 1757 piix_ignore_devices_quirk(host); 1758 1759 pci_set_master(pdev); 1760 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht); 1761} 1762 1763static void piix_remove_one(struct pci_dev *pdev) 1764{ 1765 struct ata_host *host = pci_get_drvdata(pdev); 1766 struct piix_host_priv *hpriv = host->private_data; 1767 1768 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg); 1769 1770 ata_pci_remove_one(pdev); 1771} 1772 1773static struct pci_driver piix_pci_driver = { 1774 .name = DRV_NAME, 1775 .id_table = piix_pci_tbl, 1776 .probe = piix_init_one, 1777 .remove = piix_remove_one, 1778#ifdef CONFIG_PM_SLEEP 1779 .suspend = piix_pci_device_suspend, 1780 .resume = piix_pci_device_resume, 1781#endif 1782}; 1783 1784static int __init piix_init(void) 1785{ 1786 int rc; 1787 1788 DPRINTK("pci_register_driver\n"); 1789 rc = pci_register_driver(&piix_pci_driver); 1790 if (rc) 1791 return rc; 1792 1793 in_module_init = 0; 1794 1795 DPRINTK("done\n"); 1796 return 0; 1797} 1798 1799static void __exit piix_exit(void) 1800{ 1801 pci_unregister_driver(&piix_pci_driver); 1802} 1803 1804module_init(piix_init); 1805module_exit(piix_exit); 1806