1/** 2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19#include <linux/kernel.h> 20#include <linux/slab.h> 21#include <linux/spinlock.h> 22#include <linux/platform_device.h> 23#include <linux/pm_runtime.h> 24#include <linux/interrupt.h> 25#include <linux/io.h> 26#include <linux/list.h> 27#include <linux/dma-mapping.h> 28 29#include <linux/usb/ch9.h> 30#include <linux/usb/gadget.h> 31#include <linux/usb/composite.h> 32 33#include "core.h" 34#include "debug.h" 35#include "gadget.h" 36#include "io.h" 37 38static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); 39static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 40 struct dwc3_ep *dep, struct dwc3_request *req); 41 42static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) 43{ 44 switch (state) { 45 case EP0_UNCONNECTED: 46 return "Unconnected"; 47 case EP0_SETUP_PHASE: 48 return "Setup Phase"; 49 case EP0_DATA_PHASE: 50 return "Data Phase"; 51 case EP0_STATUS_PHASE: 52 return "Status Phase"; 53 default: 54 return "UNKNOWN"; 55 } 56} 57 58static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, 59 u32 len, u32 type, bool chain) 60{ 61 struct dwc3_gadget_ep_cmd_params params; 62 struct dwc3_trb *trb; 63 struct dwc3_ep *dep; 64 65 int ret; 66 67 dep = dwc->eps[epnum]; 68 if (dep->flags & DWC3_EP_BUSY) { 69 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name); 70 return 0; 71 } 72 73 trb = &dwc->ep0_trb[dep->free_slot]; 74 75 if (chain) 76 dep->free_slot++; 77 78 trb->bpl = lower_32_bits(buf_dma); 79 trb->bph = upper_32_bits(buf_dma); 80 trb->size = len; 81 trb->ctrl = type; 82 83 trb->ctrl |= (DWC3_TRB_CTRL_HWO 84 | DWC3_TRB_CTRL_ISP_IMI); 85 86 if (chain) 87 trb->ctrl |= DWC3_TRB_CTRL_CHN; 88 else 89 trb->ctrl |= (DWC3_TRB_CTRL_IOC 90 | DWC3_TRB_CTRL_LST); 91 92 if (chain) 93 return 0; 94 95 memset(¶ms, 0, sizeof(params)); 96 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 97 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 98 99 trace_dwc3_prepare_trb(dep, trb); 100 101 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 102 DWC3_DEPCMD_STARTTRANSFER, ¶ms); 103 if (ret < 0) { 104 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed", 105 dep->name); 106 return ret; 107 } 108 109 dep->flags |= DWC3_EP_BUSY; 110 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, 111 dep->number); 112 113 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 114 115 return 0; 116} 117 118static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 119 struct dwc3_request *req) 120{ 121 struct dwc3 *dwc = dep->dwc; 122 123 req->request.actual = 0; 124 req->request.status = -EINPROGRESS; 125 req->epnum = dep->number; 126 127 list_add_tail(&req->list, &dep->request_list); 128 129 /* 130 * Gadget driver might not be quick enough to queue a request 131 * before we get a Transfer Not Ready event on this endpoint. 132 * 133 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 134 * flag is set, it's telling us that as soon as Gadget queues the 135 * required request, we should kick the transfer here because the 136 * IRQ we were waiting for is long gone. 137 */ 138 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 139 unsigned direction; 140 141 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 142 143 if (dwc->ep0state != EP0_DATA_PHASE) { 144 dev_WARN(dwc->dev, "Unexpected pending request\n"); 145 return 0; 146 } 147 148 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 149 150 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 151 DWC3_EP0_DIR_IN); 152 153 return 0; 154 } 155 156 /* 157 * In case gadget driver asked us to delay the STATUS phase, 158 * handle it here. 159 */ 160 if (dwc->delayed_status) { 161 unsigned direction; 162 163 direction = !dwc->ep0_expect_in; 164 dwc->delayed_status = false; 165 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED); 166 167 if (dwc->ep0state == EP0_STATUS_PHASE) 168 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 169 else 170 dwc3_trace(trace_dwc3_ep0, 171 "too early for delayed status"); 172 173 return 0; 174 } 175 176 /* 177 * Unfortunately we have uncovered a limitation wrt the Data Phase. 178 * 179 * Section 9.4 says we can wait for the XferNotReady(DATA) event to 180 * come before issueing Start Transfer command, but if we do, we will 181 * miss situations where the host starts another SETUP phase instead of 182 * the DATA phase. Such cases happen at least on TD.7.6 of the Link 183 * Layer Compliance Suite. 184 * 185 * The problem surfaces due to the fact that in case of back-to-back 186 * SETUP packets there will be no XferNotReady(DATA) generated and we 187 * will be stuck waiting for XferNotReady(DATA) forever. 188 * 189 * By looking at tables 9-13 and 9-14 of the Databook, we can see that 190 * it tells us to start Data Phase right away. It also mentions that if 191 * we receive a SETUP phase instead of the DATA phase, core will issue 192 * XferComplete for the DATA phase, before actually initiating it in 193 * the wire, with the TRB's status set to "SETUP_PENDING". Such status 194 * can only be used to print some debugging logs, as the core expects 195 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, 196 * just so it completes right away, without transferring anything and, 197 * only then, we can go back to the SETUP phase. 198 * 199 * Because of this scenario, SNPS decided to change the programming 200 * model of control transfers and support on-demand transfers only for 201 * the STATUS phase. To fix the issue we have now, we will always wait 202 * for gadget driver to queue the DATA phase's struct usb_request, then 203 * start it right away. 204 * 205 * If we're actually in a 2-stage transfer, we will wait for 206 * XferNotReady(STATUS). 207 */ 208 if (dwc->three_stage_setup) { 209 unsigned direction; 210 211 direction = dwc->ep0_expect_in; 212 dwc->ep0state = EP0_DATA_PHASE; 213 214 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 215 216 dep->flags &= ~DWC3_EP0_DIR_IN; 217 } 218 219 return 0; 220} 221 222int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 223 gfp_t gfp_flags) 224{ 225 struct dwc3_request *req = to_dwc3_request(request); 226 struct dwc3_ep *dep = to_dwc3_ep(ep); 227 struct dwc3 *dwc = dep->dwc; 228 229 unsigned long flags; 230 231 int ret; 232 233 spin_lock_irqsave(&dwc->lock, flags); 234 if (!dep->endpoint.desc) { 235 dwc3_trace(trace_dwc3_ep0, 236 "trying to queue request %p to disabled %s", 237 request, dep->name); 238 ret = -ESHUTDOWN; 239 goto out; 240 } 241 242 /* we share one TRB for ep0/1 */ 243 if (!list_empty(&dep->request_list)) { 244 ret = -EBUSY; 245 goto out; 246 } 247 248 dwc3_trace(trace_dwc3_ep0, 249 "queueing request %p to %s length %d state '%s'", 250 request, dep->name, request->length, 251 dwc3_ep0_state_string(dwc->ep0state)); 252 253 ret = __dwc3_gadget_ep0_queue(dep, req); 254 255out: 256 spin_unlock_irqrestore(&dwc->lock, flags); 257 258 return ret; 259} 260 261static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 262{ 263 struct dwc3_ep *dep; 264 265 /* reinitialize physical ep1 */ 266 dep = dwc->eps[1]; 267 dep->flags = DWC3_EP_ENABLED; 268 269 /* stall is always issued on EP0 */ 270 dep = dwc->eps[0]; 271 __dwc3_gadget_ep_set_halt(dep, 1, false); 272 dep->flags = DWC3_EP_ENABLED; 273 dwc->delayed_status = false; 274 275 if (!list_empty(&dep->request_list)) { 276 struct dwc3_request *req; 277 278 req = next_request(&dep->request_list); 279 dwc3_gadget_giveback(dep, req, -ECONNRESET); 280 } 281 282 dwc->ep0state = EP0_SETUP_PHASE; 283 dwc3_ep0_out_start(dwc); 284} 285 286int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 287{ 288 struct dwc3_ep *dep = to_dwc3_ep(ep); 289 struct dwc3 *dwc = dep->dwc; 290 291 dwc3_ep0_stall_and_restart(dwc); 292 293 return 0; 294} 295 296int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 297{ 298 struct dwc3_ep *dep = to_dwc3_ep(ep); 299 struct dwc3 *dwc = dep->dwc; 300 unsigned long flags; 301 int ret; 302 303 spin_lock_irqsave(&dwc->lock, flags); 304 ret = __dwc3_gadget_ep0_set_halt(ep, value); 305 spin_unlock_irqrestore(&dwc->lock, flags); 306 307 return ret; 308} 309 310void dwc3_ep0_out_start(struct dwc3 *dwc) 311{ 312 int ret; 313 314 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, 315 DWC3_TRBCTL_CONTROL_SETUP, false); 316 WARN_ON(ret < 0); 317} 318 319static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 320{ 321 struct dwc3_ep *dep; 322 u32 windex = le16_to_cpu(wIndex_le); 323 u32 epnum; 324 325 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 326 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 327 epnum |= 1; 328 329 dep = dwc->eps[epnum]; 330 if (dep->flags & DWC3_EP_ENABLED) 331 return dep; 332 333 return NULL; 334} 335 336static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 337{ 338} 339/* 340 * ch 9.4.5 341 */ 342static int dwc3_ep0_handle_status(struct dwc3 *dwc, 343 struct usb_ctrlrequest *ctrl) 344{ 345 struct dwc3_ep *dep; 346 u32 recip; 347 u32 reg; 348 u16 usb_status = 0; 349 __le16 *response_pkt; 350 351 recip = ctrl->bRequestType & USB_RECIP_MASK; 352 switch (recip) { 353 case USB_RECIP_DEVICE: 354 /* 355 * LTM will be set once we know how to set this in HW. 356 */ 357 usb_status |= dwc->gadget.is_selfpowered; 358 359 if (dwc->speed == DWC3_DSTS_SUPERSPEED) { 360 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 361 if (reg & DWC3_DCTL_INITU1ENA) 362 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; 363 if (reg & DWC3_DCTL_INITU2ENA) 364 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; 365 } 366 367 break; 368 369 case USB_RECIP_INTERFACE: 370 /* 371 * Function Remote Wake Capable D0 372 * Function Remote Wakeup D1 373 */ 374 break; 375 376 case USB_RECIP_ENDPOINT: 377 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 378 if (!dep) 379 return -EINVAL; 380 381 if (dep->flags & DWC3_EP_STALL) 382 usb_status = 1 << USB_ENDPOINT_HALT; 383 break; 384 default: 385 return -EINVAL; 386 } 387 388 response_pkt = (__le16 *) dwc->setup_buf; 389 *response_pkt = cpu_to_le16(usb_status); 390 391 dep = dwc->eps[0]; 392 dwc->ep0_usb_req.dep = dep; 393 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 394 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 395 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 396 397 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 398} 399 400static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 401 struct usb_ctrlrequest *ctrl, int set) 402{ 403 struct dwc3_ep *dep; 404 u32 recip; 405 u32 wValue; 406 u32 wIndex; 407 u32 reg; 408 int ret; 409 enum usb_device_state state; 410 411 wValue = le16_to_cpu(ctrl->wValue); 412 wIndex = le16_to_cpu(ctrl->wIndex); 413 recip = ctrl->bRequestType & USB_RECIP_MASK; 414 state = dwc->gadget.state; 415 416 switch (recip) { 417 case USB_RECIP_DEVICE: 418 419 switch (wValue) { 420 case USB_DEVICE_REMOTE_WAKEUP: 421 break; 422 /* 423 * 9.4.1 says only only for SS, in AddressState only for 424 * default control pipe 425 */ 426 case USB_DEVICE_U1_ENABLE: 427 if (state != USB_STATE_CONFIGURED) 428 return -EINVAL; 429 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 430 return -EINVAL; 431 432 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 433 if (set) 434 reg |= DWC3_DCTL_INITU1ENA; 435 else 436 reg &= ~DWC3_DCTL_INITU1ENA; 437 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 438 break; 439 440 case USB_DEVICE_U2_ENABLE: 441 if (state != USB_STATE_CONFIGURED) 442 return -EINVAL; 443 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 444 return -EINVAL; 445 446 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 447 if (set) 448 reg |= DWC3_DCTL_INITU2ENA; 449 else 450 reg &= ~DWC3_DCTL_INITU2ENA; 451 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 452 break; 453 454 case USB_DEVICE_LTM_ENABLE: 455 return -EINVAL; 456 457 case USB_DEVICE_TEST_MODE: 458 if ((wIndex & 0xff) != 0) 459 return -EINVAL; 460 if (!set) 461 return -EINVAL; 462 463 dwc->test_mode_nr = wIndex >> 8; 464 dwc->test_mode = true; 465 break; 466 default: 467 return -EINVAL; 468 } 469 break; 470 471 case USB_RECIP_INTERFACE: 472 switch (wValue) { 473 case USB_INTRF_FUNC_SUSPEND: 474 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) 475 /* XXX enable Low power suspend */ 476 ; 477 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) 478 /* XXX enable remote wakeup */ 479 ; 480 break; 481 default: 482 return -EINVAL; 483 } 484 break; 485 486 case USB_RECIP_ENDPOINT: 487 switch (wValue) { 488 case USB_ENDPOINT_HALT: 489 dep = dwc3_wIndex_to_dep(dwc, wIndex); 490 if (!dep) 491 return -EINVAL; 492 if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) 493 break; 494 ret = __dwc3_gadget_ep_set_halt(dep, set, true); 495 if (ret) 496 return -EINVAL; 497 break; 498 default: 499 return -EINVAL; 500 } 501 break; 502 503 default: 504 return -EINVAL; 505 } 506 507 return 0; 508} 509 510static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 511{ 512 enum usb_device_state state = dwc->gadget.state; 513 u32 addr; 514 u32 reg; 515 516 addr = le16_to_cpu(ctrl->wValue); 517 if (addr > 127) { 518 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr); 519 return -EINVAL; 520 } 521 522 if (state == USB_STATE_CONFIGURED) { 523 dwc3_trace(trace_dwc3_ep0, 524 "trying to set address when configured"); 525 return -EINVAL; 526 } 527 528 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 529 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 530 reg |= DWC3_DCFG_DEVADDR(addr); 531 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 532 533 if (addr) 534 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS); 535 else 536 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); 537 538 return 0; 539} 540 541static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 542{ 543 int ret; 544 545 spin_unlock(&dwc->lock); 546 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); 547 spin_lock(&dwc->lock); 548 return ret; 549} 550 551static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 552{ 553 enum usb_device_state state = dwc->gadget.state; 554 u32 cfg; 555 int ret; 556 u32 reg; 557 558 cfg = le16_to_cpu(ctrl->wValue); 559 560 switch (state) { 561 case USB_STATE_DEFAULT: 562 return -EINVAL; 563 564 case USB_STATE_ADDRESS: 565 ret = dwc3_ep0_delegate_req(dwc, ctrl); 566 /* if the cfg matches and the cfg is non zero */ 567 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { 568 569 /* 570 * only change state if set_config has already 571 * been processed. If gadget driver returns 572 * USB_GADGET_DELAYED_STATUS, we will wait 573 * to change the state on the next usb_ep_queue() 574 */ 575 if (ret == 0) 576 usb_gadget_set_state(&dwc->gadget, 577 USB_STATE_CONFIGURED); 578 579 /* 580 * Enable transition to U1/U2 state when 581 * nothing is pending from application. 582 */ 583 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 584 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); 585 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 586 587 dwc->resize_fifos = true; 588 dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET"); 589 } 590 break; 591 592 case USB_STATE_CONFIGURED: 593 ret = dwc3_ep0_delegate_req(dwc, ctrl); 594 if (!cfg && !ret) 595 usb_gadget_set_state(&dwc->gadget, 596 USB_STATE_ADDRESS); 597 break; 598 default: 599 ret = -EINVAL; 600 } 601 return ret; 602} 603 604static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) 605{ 606 struct dwc3_ep *dep = to_dwc3_ep(ep); 607 struct dwc3 *dwc = dep->dwc; 608 609 u32 param = 0; 610 u32 reg; 611 612 struct timing { 613 u8 u1sel; 614 u8 u1pel; 615 u16 u2sel; 616 u16 u2pel; 617 } __packed timing; 618 619 int ret; 620 621 memcpy(&timing, req->buf, sizeof(timing)); 622 623 dwc->u1sel = timing.u1sel; 624 dwc->u1pel = timing.u1pel; 625 dwc->u2sel = le16_to_cpu(timing.u2sel); 626 dwc->u2pel = le16_to_cpu(timing.u2pel); 627 628 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 629 if (reg & DWC3_DCTL_INITU2ENA) 630 param = dwc->u2pel; 631 if (reg & DWC3_DCTL_INITU1ENA) 632 param = dwc->u1pel; 633 634 /* 635 * According to Synopsys Databook, if parameter is 636 * greater than 125, a value of zero should be 637 * programmed in the register. 638 */ 639 if (param > 125) 640 param = 0; 641 642 /* now that we have the time, issue DGCMD Set Sel */ 643 ret = dwc3_send_gadget_generic_command(dwc, 644 DWC3_DGCMD_SET_PERIODIC_PAR, param); 645 WARN_ON(ret < 0); 646} 647 648static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 649{ 650 struct dwc3_ep *dep; 651 enum usb_device_state state = dwc->gadget.state; 652 u16 wLength; 653 u16 wValue; 654 655 if (state == USB_STATE_DEFAULT) 656 return -EINVAL; 657 658 wValue = le16_to_cpu(ctrl->wValue); 659 wLength = le16_to_cpu(ctrl->wLength); 660 661 if (wLength != 6) { 662 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", 663 wLength); 664 return -EINVAL; 665 } 666 667 /* 668 * To handle Set SEL we need to receive 6 bytes from Host. So let's 669 * queue a usb_request for 6 bytes. 670 * 671 * Remember, though, this controller can't handle non-wMaxPacketSize 672 * aligned transfers on the OUT direction, so we queue a request for 673 * wMaxPacketSize instead. 674 */ 675 dep = dwc->eps[0]; 676 dwc->ep0_usb_req.dep = dep; 677 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; 678 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 679 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; 680 681 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 682} 683 684static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 685{ 686 u16 wLength; 687 u16 wValue; 688 u16 wIndex; 689 690 wValue = le16_to_cpu(ctrl->wValue); 691 wLength = le16_to_cpu(ctrl->wLength); 692 wIndex = le16_to_cpu(ctrl->wIndex); 693 694 if (wIndex || wLength) 695 return -EINVAL; 696 697 /* 698 * REVISIT It's unclear from Databook what to do with this 699 * value. For now, just cache it. 700 */ 701 dwc->isoch_delay = wValue; 702 703 return 0; 704} 705 706static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 707{ 708 int ret; 709 710 switch (ctrl->bRequest) { 711 case USB_REQ_GET_STATUS: 712 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS"); 713 ret = dwc3_ep0_handle_status(dwc, ctrl); 714 break; 715 case USB_REQ_CLEAR_FEATURE: 716 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE"); 717 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 718 break; 719 case USB_REQ_SET_FEATURE: 720 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE"); 721 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 722 break; 723 case USB_REQ_SET_ADDRESS: 724 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS"); 725 ret = dwc3_ep0_set_address(dwc, ctrl); 726 break; 727 case USB_REQ_SET_CONFIGURATION: 728 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION"); 729 ret = dwc3_ep0_set_config(dwc, ctrl); 730 break; 731 case USB_REQ_SET_SEL: 732 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL"); 733 ret = dwc3_ep0_set_sel(dwc, ctrl); 734 break; 735 case USB_REQ_SET_ISOCH_DELAY: 736 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY"); 737 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); 738 break; 739 default: 740 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver"); 741 ret = dwc3_ep0_delegate_req(dwc, ctrl); 742 break; 743 } 744 745 return ret; 746} 747 748static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 749 const struct dwc3_event_depevt *event) 750{ 751 struct usb_ctrlrequest *ctrl = dwc->ctrl_req; 752 int ret = -EINVAL; 753 u32 len; 754 755 if (!dwc->gadget_driver) 756 goto out; 757 758 trace_dwc3_ctrl_req(ctrl); 759 760 len = le16_to_cpu(ctrl->wLength); 761 if (!len) { 762 dwc->three_stage_setup = false; 763 dwc->ep0_expect_in = false; 764 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 765 } else { 766 dwc->three_stage_setup = true; 767 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 768 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 769 } 770 771 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 772 ret = dwc3_ep0_std_request(dwc, ctrl); 773 else 774 ret = dwc3_ep0_delegate_req(dwc, ctrl); 775 776 if (ret == USB_GADGET_DELAYED_STATUS) 777 dwc->delayed_status = true; 778 779out: 780 if (ret < 0) 781 dwc3_ep0_stall_and_restart(dwc); 782} 783 784static void dwc3_ep0_complete_data(struct dwc3 *dwc, 785 const struct dwc3_event_depevt *event) 786{ 787 struct dwc3_request *r = NULL; 788 struct usb_request *ur; 789 struct dwc3_trb *trb; 790 struct dwc3_ep *ep0; 791 unsigned transfer_size = 0; 792 unsigned maxp; 793 unsigned remaining_ur_length; 794 void *buf; 795 u32 transferred = 0; 796 u32 status; 797 u32 length; 798 u8 epnum; 799 800 epnum = event->endpoint_number; 801 ep0 = dwc->eps[0]; 802 803 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 804 805 trb = dwc->ep0_trb; 806 807 trace_dwc3_complete_trb(ep0, trb); 808 809 r = next_request(&ep0->request_list); 810 if (!r) 811 return; 812 813 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 814 if (status == DWC3_TRBSTS_SETUP_PENDING) { 815 dwc3_trace(trace_dwc3_ep0, "Setup Pending received"); 816 817 if (r) 818 dwc3_gadget_giveback(ep0, r, -ECONNRESET); 819 820 return; 821 } 822 823 ur = &r->request; 824 buf = ur->buf; 825 remaining_ur_length = ur->length; 826 827 length = trb->size & DWC3_TRB_SIZE_MASK; 828 829 maxp = ep0->endpoint.maxpacket; 830 831 if (dwc->ep0_bounced) { 832 /* 833 * Handle the first TRB before handling the bounce buffer if 834 * the request length is greater than the bounce buffer size 835 */ 836 if (ur->length > DWC3_EP0_BOUNCE_SIZE) { 837 transfer_size = ALIGN(ur->length - maxp, maxp); 838 transferred = transfer_size - length; 839 buf = (u8 *)buf + transferred; 840 ur->actual += transferred; 841 remaining_ur_length -= transferred; 842 843 trb++; 844 length = trb->size & DWC3_TRB_SIZE_MASK; 845 846 ep0->free_slot = 0; 847 } 848 849 transfer_size = roundup((ur->length - transfer_size), 850 maxp); 851 852 transferred = min_t(u32, remaining_ur_length, 853 transfer_size - length); 854 memcpy(buf, dwc->ep0_bounce, transferred); 855 } else { 856 transferred = ur->length - length; 857 } 858 859 ur->actual += transferred; 860 861 if ((epnum & 1) && ur->actual < ur->length) { 862 /* for some reason we did not get everything out */ 863 864 dwc3_ep0_stall_and_restart(dwc); 865 } else { 866 dwc3_gadget_giveback(ep0, r, 0); 867 868 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && 869 ur->length && ur->zero) { 870 int ret; 871 872 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 873 874 ret = dwc3_ep0_start_trans(dwc, epnum, 875 dwc->ctrl_req_addr, 0, 876 DWC3_TRBCTL_CONTROL_DATA, false); 877 WARN_ON(ret < 0); 878 } 879 } 880} 881 882static void dwc3_ep0_complete_status(struct dwc3 *dwc, 883 const struct dwc3_event_depevt *event) 884{ 885 struct dwc3_request *r; 886 struct dwc3_ep *dep; 887 struct dwc3_trb *trb; 888 u32 status; 889 890 dep = dwc->eps[0]; 891 trb = dwc->ep0_trb; 892 893 trace_dwc3_complete_trb(dep, trb); 894 895 if (!list_empty(&dep->request_list)) { 896 r = next_request(&dep->request_list); 897 898 dwc3_gadget_giveback(dep, r, 0); 899 } 900 901 if (dwc->test_mode) { 902 int ret; 903 904 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); 905 if (ret < 0) { 906 dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d", 907 dwc->test_mode_nr); 908 dwc3_ep0_stall_and_restart(dwc); 909 return; 910 } 911 } 912 913 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 914 if (status == DWC3_TRBSTS_SETUP_PENDING) 915 dwc3_trace(trace_dwc3_ep0, "Setup Pending received"); 916 917 dwc->ep0state = EP0_SETUP_PHASE; 918 dwc3_ep0_out_start(dwc); 919} 920 921static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 922 const struct dwc3_event_depevt *event) 923{ 924 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 925 926 dep->flags &= ~DWC3_EP_BUSY; 927 dep->resource_index = 0; 928 dwc->setup_packet_pending = false; 929 930 switch (dwc->ep0state) { 931 case EP0_SETUP_PHASE: 932 dwc3_trace(trace_dwc3_ep0, "Setup Phase"); 933 dwc3_ep0_inspect_setup(dwc, event); 934 break; 935 936 case EP0_DATA_PHASE: 937 dwc3_trace(trace_dwc3_ep0, "Data Phase"); 938 dwc3_ep0_complete_data(dwc, event); 939 break; 940 941 case EP0_STATUS_PHASE: 942 dwc3_trace(trace_dwc3_ep0, "Status Phase"); 943 dwc3_ep0_complete_status(dwc, event); 944 break; 945 default: 946 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 947 } 948} 949 950static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 951 struct dwc3_ep *dep, struct dwc3_request *req) 952{ 953 int ret; 954 955 req->direction = !!dep->number; 956 957 if (req->request.length == 0) { 958 ret = dwc3_ep0_start_trans(dwc, dep->number, 959 dwc->ctrl_req_addr, 0, 960 DWC3_TRBCTL_CONTROL_DATA, false); 961 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) 962 && (dep->number == 0)) { 963 u32 transfer_size = 0; 964 u32 maxpacket; 965 966 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 967 dep->number); 968 if (ret) { 969 dev_dbg(dwc->dev, "failed to map request\n"); 970 return; 971 } 972 973 maxpacket = dep->endpoint.maxpacket; 974 975 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) { 976 transfer_size = ALIGN(req->request.length - maxpacket, 977 maxpacket); 978 ret = dwc3_ep0_start_trans(dwc, dep->number, 979 req->request.dma, 980 transfer_size, 981 DWC3_TRBCTL_CONTROL_DATA, 982 true); 983 } 984 985 transfer_size = roundup((req->request.length - transfer_size), 986 maxpacket); 987 988 dwc->ep0_bounced = true; 989 990 ret = dwc3_ep0_start_trans(dwc, dep->number, 991 dwc->ep0_bounce_addr, transfer_size, 992 DWC3_TRBCTL_CONTROL_DATA, false); 993 } else { 994 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 995 dep->number); 996 if (ret) { 997 dev_dbg(dwc->dev, "failed to map request\n"); 998 return; 999 } 1000 1001 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma, 1002 req->request.length, DWC3_TRBCTL_CONTROL_DATA, 1003 false); 1004 } 1005 1006 WARN_ON(ret < 0); 1007} 1008 1009static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 1010{ 1011 struct dwc3 *dwc = dep->dwc; 1012 u32 type; 1013 1014 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 1015 : DWC3_TRBCTL_CONTROL_STATUS2; 1016 1017 return dwc3_ep0_start_trans(dwc, dep->number, 1018 dwc->ctrl_req_addr, 0, type, false); 1019} 1020 1021static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) 1022{ 1023 if (dwc->resize_fifos) { 1024 dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs"); 1025 dwc3_gadget_resize_tx_fifos(dwc); 1026 dwc->resize_fifos = 0; 1027 } 1028 1029 WARN_ON(dwc3_ep0_start_control_status(dep)); 1030} 1031 1032static void dwc3_ep0_do_control_status(struct dwc3 *dwc, 1033 const struct dwc3_event_depevt *event) 1034{ 1035 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 1036 1037 __dwc3_ep0_do_control_status(dwc, dep); 1038} 1039 1040static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) 1041{ 1042 struct dwc3_gadget_ep_cmd_params params; 1043 u32 cmd; 1044 int ret; 1045 1046 if (!dep->resource_index) 1047 return; 1048 1049 cmd = DWC3_DEPCMD_ENDTRANSFER; 1050 cmd |= DWC3_DEPCMD_CMDIOC; 1051 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 1052 memset(¶ms, 0, sizeof(params)); 1053 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 1054 WARN_ON_ONCE(ret); 1055 dep->resource_index = 0; 1056} 1057 1058static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 1059 const struct dwc3_event_depevt *event) 1060{ 1061 dwc->setup_packet_pending = true; 1062 1063 switch (event->status) { 1064 case DEPEVT_STATUS_CONTROL_DATA: 1065 dwc3_trace(trace_dwc3_ep0, "Control Data"); 1066 1067 /* 1068 * We already have a DATA transfer in the controller's cache, 1069 * if we receive a XferNotReady(DATA) we will ignore it, unless 1070 * it's for the wrong direction. 1071 * 1072 * In that case, we must issue END_TRANSFER command to the Data 1073 * Phase we already have started and issue SetStall on the 1074 * control endpoint. 1075 */ 1076 if (dwc->ep0_expect_in != event->endpoint_number) { 1077 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; 1078 1079 dwc3_trace(trace_dwc3_ep0, 1080 "Wrong direction for Data phase"); 1081 dwc3_ep0_end_control_data(dwc, dep); 1082 dwc3_ep0_stall_and_restart(dwc); 1083 return; 1084 } 1085 1086 break; 1087 1088 case DEPEVT_STATUS_CONTROL_STATUS: 1089 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) 1090 return; 1091 1092 dwc3_trace(trace_dwc3_ep0, "Control Status"); 1093 1094 dwc->ep0state = EP0_STATUS_PHASE; 1095 1096 if (dwc->delayed_status) { 1097 WARN_ON_ONCE(event->endpoint_number != 1); 1098 dwc3_trace(trace_dwc3_ep0, "Delayed Status"); 1099 return; 1100 } 1101 1102 dwc3_ep0_do_control_status(dwc, event); 1103 } 1104} 1105 1106void dwc3_ep0_interrupt(struct dwc3 *dwc, 1107 const struct dwc3_event_depevt *event) 1108{ 1109 u8 epnum = event->endpoint_number; 1110 1111 dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'", 1112 dwc3_ep_event_string(event->endpoint_event), 1113 epnum >> 1, (epnum & 1) ? "in" : "out", 1114 dwc3_ep0_state_string(dwc->ep0state)); 1115 1116 switch (event->endpoint_event) { 1117 case DWC3_DEPEVT_XFERCOMPLETE: 1118 dwc3_ep0_xfer_complete(dwc, event); 1119 break; 1120 1121 case DWC3_DEPEVT_XFERNOTREADY: 1122 dwc3_ep0_xfernotready(dwc, event); 1123 break; 1124 1125 case DWC3_DEPEVT_XFERINPROGRESS: 1126 case DWC3_DEPEVT_RXTXFIFOEVT: 1127 case DWC3_DEPEVT_STREAMEVT: 1128 case DWC3_DEPEVT_EPCMDCMPLT: 1129 break; 1130 } 1131} 1132