Searched refs:reset (Results 1 - 200 of 5336) sorted by relevance

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/linux-4.1.27/arch/mips/lantiq/falcon/
H A DMakefile1 obj-y := prom.o reset.o sysctrl.o
/linux-4.1.27/arch/mips/pnx833x/common/
H A DMakefile1 obj-y := interrupts.o platform.o prom.o setup.o reset.o
H A Dreset.c2 * reset.c: reset support for PNX833X.
/linux-4.1.27/arch/mips/jazz/
H A DMakefile5 obj-y := irq.o jazzdma.o reset.o setup.o
/linux-4.1.27/arch/mips/lantiq/xway/
H A DMakefile1 obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
H A Dreset.c17 #include <linux/reset-controller.h>
28 /* reset request register */
30 /* reset status register */
41 /* reset cause */
47 /* remapped base addr of the reset control unit */
70 /* reset / boot a gphy */
79 /* reset and boot a gphy. these phys only exist on xrx200 SoC */ xrx200_gphy_boot()
109 /* reset a io domain for u micro seconds */ ltq_reset_once()
155 .reset = ltq_reset_device,
170 "lantiq,xway-reset"); ltq_rst_init()
172 pr_err("Failed to find reset controller node"); ltq_rst_init()
212 /* check if all the reset register range is available */ mips_reboot_setup()
214 panic("Failed to load reset resources from devicetree"); mips_reboot_setup()
/linux-4.1.27/include/linux/
H A Dreset-controller.h11 * @reset: for self-deasserting resets, does all necessary
12 * things to reset the device
13 * @assert: manually assert the reset line, if supported
14 * @deassert: manually deassert the reset line, if supported
15 * @status: return the status of the reset line, if supported
18 int (*reset)(struct reset_controller_dev *rcdev, unsigned long id); member in struct:reset_control_ops
29 * struct reset_controller_dev - reset controller entity that might
30 * provide multiple reset controls
32 * @owner: kernel module of the reset controller driver
33 * @list: internal list of reset controller devices
35 * @of_reset_n_cells: number of cells in reset line specifiers
37 * device tree to id as given to the reset control ops
38 * @nr_resets: number of reset controls in this reset controller device
H A Dmdio-gpio.h28 /* reset callback */
29 int (*reset)(struct mii_bus *bus); member in struct:mdio_gpio_platform_data
H A Dhtcpld.h6 unsigned int reset; member in struct:htcpld_chip_platform_data
H A Di2c-pca-platform.h5 int gpio; /* pin to reset chip. driver will work when
H A Dmdio-bitbang.h35 /* reset callback */
36 int (*reset)(struct mii_bus *bus); member in struct:mdiobb_ctrl
H A Dmg_disk.h22 /* except MG_BOOT_DEV, reset-out pin should be assigned */
30 /* same as MG_STORAGE_DEV, but bootloader already done reset sequence */
/linux-4.1.27/include/linux/platform_data/
H A Dpcmcia-pxa2xx_viper.h8 void (*reset)(int state); member in struct:arcom_pcmcia_pdata
H A Dst1232_pdata.h7 * Use this if you want the driver to drive the reset pin.
H A Dbd6107.h15 int reset; /* Reset GPIO */ member in struct:bd6107_platform_data
H A Domap-wd-timer.h19 * Standardized OMAP reset source bits
28 * @read_reset_sources - fn ptr for the SoC to indicate the last reset cause
H A Dnet-cw1200.h17 int reset; /* GPIO to RSTn signal (0 disables) */ member in struct:cw1200_platform_data_spi
33 int reset; /* GPIO to RSTn signal (0 disables) */ member in struct:cw1200_platform_data_sdio
50 .reset = GPIO_RF_RESET,
H A Dbrcmfmac-sdio.h46 .reset = brcmfmac_reset
107 * unloaded. At this point the device can be powered down or otherwise be reset.
108 * So if an actual power_off is not supported but reset is then reset the device
111 * reset) then provide NULL.
113 * reset: This function can get called if the device communication broke down.
115 * possible to reset a dongle via sdio data interface, but it requires that
117 * function should return only after the complete reset has completed.
132 void (*reset)(void); member in struct:brcmfmac_sdio_platform_data
H A Dkeypad-ep93xx.h7 #define EP93XX_KEYPAD_DISABLE_3_KEY (1<<0) /* disable 3-key reset */
/linux-4.1.27/net/wimax/
H A DMakefile7 op-reset.o \
H A Dop-reset.c24 * This implements a simple synchronous call to reset a WiMAX device.
27 * however, when that fails, it falls back to a cold reset (that will
49 * %0 if ok and a warm reset was done (the device still exists in
52 * -%ENODEV if a cold/bus reset had to be done (device has
63 * Called when wanting to reset the device for any reason. Device is
67 * reset process and is ready to operate.
98 * Parse the reset command from user space, return error code.
/linux-4.1.27/arch/m68k/coldfire/
H A DMakefile18 obj-$(CONFIG_M5206) += m5206.o timers.o intc.o reset.o
19 obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o
20 obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o
21 obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o
22 obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o
23 obj-$(CONFIG_M525x) += m525x.o timers.o intc.o intc-525x.o reset.o
24 obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o
26 obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o
27 obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o
28 obj-$(CONFIG_M53xx) += m53xx.o timers.o intc-simr.o reset.o
29 obj-$(CONFIG_M5407) += m5407.o timers.o intc.o reset.o
31 obj-$(CONFIG_M5441x) += m5441x.o pit.o intc-simr.o reset.o
H A Dreset.c2 * reset.c -- common ColdFire SoC reset support
29 /* Set watchdog to soft reset, and enabled */ mcf_cpu_reset()
/linux-4.1.27/drivers/reset/sti/
H A Dreset-syscfg.h15 #include <linux/reset-controller.h>
19 * reset controller.
23 * @reset: Regmap field description of the channel's reset bit.
28 struct reg_field reset; member in struct:syscfg_reset_channel_data
34 .reset = REG_FIELD(_rr, _rb, _rb), \
39 .reset = REG_FIELD(_rr, _rb, _rb), }
42 * Description of a system configuration register based reset controller.
44 * @wait_for_ack: The controller will wait for reset assert and de-assert to
47 * the reset bit puts the hardware into reset.
48 * @nr_channels: The number of reset channels in this controller.
49 * @channels: An array of reset channel descriptions.
60 * reset controller drivers. This registers a reset
H A Dreset-syscfg.c21 #include "reset-syscfg.h"
26 * @reset: regmap field for the channel's reset bit.
30 struct regmap_field *reset; member in struct:syscfg_reset_channel
35 * A reset controller which groups together a set of related reset bits, which
38 * @rst: base reset controller structure.
40 * the reset bit puts the hardware into reset.
41 * @channels: An array of reset channels for this controller.
65 err = regmap_field_write(ch->reset, ctrl_val); syscfg_reset_program_hw()
114 .reset = syscfg_reset_dev,
150 f = devm_regmap_field_alloc(dev, map, data->channels[i].reset); syscfg_reset_controller_register()
154 rc->channels[i].reset = f; syscfg_reset_controller_register()
H A Dreset-stih407.c14 #include <dt-bindings/reset-controller/stih407-resets.h>
15 #include "reset-syscfg.h"
36 /* Ethernet powerdown/status/reset */
101 /* PicoPHY reset/control */
148 .name = "reset-stih407",
H A Dreset-stih415.c16 #include <dt-bindings/reset-controller/stih415-resets.h>
18 #include "reset-syscfg.h"
103 .name = "reset-stih415",
/linux-4.1.27/drivers/reset/
H A Dcore.c17 #include <linux/reset.h>
18 #include <linux/reset-controller.h>
25 * struct reset_control - a reset control
26 * @rcdev: a pointer to the reset controller device
27 * this reset control belongs to
28 * @id: ID of the reset controller in the reset
38 * of_reset_simple_xlate - translate reset_spec to the reset line number
39 * @rcdev: a pointer to the reset controller device
40 * @reset_spec: reset line specifier as found in the device tree
43 * This simple translation function should be used for reset controllers
44 * with 1:1 mapping, where reset lines can be indexed by number without gaps.
59 * reset_controller_register - register a reset controller device
60 * @rcdev: a pointer to the initialized reset controller device
78 * reset_controller_unregister - unregister a reset controller device
79 * @rcdev: a pointer to the reset controller device
90 * reset_control_reset - reset the controlled device
91 * @rstc: reset controller
95 if (rstc->rcdev->ops->reset) reset_control_reset()
96 return rstc->rcdev->ops->reset(rstc->rcdev, rstc->id); reset_control_reset()
103 * reset_control_assert - asserts the reset line
104 * @rstc: reset controller
116 * reset_control_deassert - deasserts the reset line
117 * @rstc: reset controller
130 * positive value if the reset line is asserted, or zero if the reset
132 * @rstc: reset controller
144 * of_reset_control_get - Lookup and obtain a reference to a reset controller.
145 * @node: device to be reset by the controller
146 * @id: reset line name
164 "reset-names", id); of_reset_control_get()
165 ret = of_parse_phandle_with_args(node, "resets", "#reset-cells", of_reset_control_get()
208 * reset_control_get - Lookup and obtain a reference to a reset controller.
209 * @dev: device to be reset by the controller
210 * @id: reset line name
232 * reset_control_put - free the reset controller
233 * @rstc: reset controller
253 * @dev: device to be reset by the controller
254 * @id: reset line name
256 * Managed reset_control_get(). For reset controllers returned from this
282 * device_reset - find reset controller associated with the device
283 * and perform reset
284 * @dev: device to be reset by the controller
287 * This is useful for the common case of devices with single, dedicated reset
H A Dreset-berlin.c18 #include <linux/reset-controller.h>
42 /* let the reset be effective */ berlin_reset_reset()
49 .reset = berlin_reset_reset,
H A Dreset-socfpga.c22 #include <linux/reset-controller.h>
108 if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) { socfpga_reset_probe()
109 dev_err(&pdev->dev, "%s missing #reset-cells property\n", socfpga_reset_probe()
152 .name = "socfpga-reset",
/linux-4.1.27/arch/arm/mach-berlin/
H A Dheadsmp.S16 * If the following instruction is set in the reset exception vector, CPUs
17 * will fetch the value of the software reset address vector when being
18 * reset.
H A Dplatsmp.c44 * Reset the CPU, making it to execute the instruction in the reset berlin_boot_secondary()
78 * Write the first instruction the CPU will execute after being reset berlin_smp_prepare_cpus()
79 * in the reset exception vector. berlin_smp_prepare_cpus()
84 * Write the secondary startup address into the SW reset address berlin_smp_prepare_cpus()
/linux-4.1.27/arch/mips/cobalt/
H A DMakefile5 obj-y := buttons.o irq.o lcd.o led.o mtd.o reset.o rtc.o serial.o setup.o time.o
/linux-4.1.27/arch/mips/include/asm/mach-bcm63xx/
H A Dbcm63xx_reset.h19 void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset);
H A Dboard_bcm963xx.h51 /* External PHY reset GPIO */
54 /* External PHY reset GPIO flags from gpio.h */
/linux-4.1.27/arch/arm/mach-pxa/include/mach/
H A Daudio.h9 * @reset_gpio: AC97 reset gpio (normally gpio113 or gpio95)
10 * a -1 value means no gpio will be used for reset
14 * bug prevents correct operation of the reset line. If not specified,
16 * AC97 reset line, which is the default on most boards.
H A Dreset.h14 * init_gpio_reset() - register GPIO as reset generator
/linux-4.1.27/arch/arm/mach-omap2/
H A Dprminst44xx.c91 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
94 * @shift: register bit shift corresponding to the reset line to check
113 * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
115 * @shift: register bit shift corresponding to the reset line to assert
118 * reset line to be asserted / deasserted in order to fully enable the
119 * IP. These modules may have multiple hard-reset lines that reset
121 * place the submodule into reset. Returns 0 upon success or -EINVAL
137 * @shift: register bit shift corresponding to the reset line to deassert
138 * @st_shift: status bit offset corresponding to the reset line
141 * @rstctrl_offs: reset register offset
142 * @rstst_offs: reset status register offset
145 * reset line to be asserted / deasserted in order to fully enable the
146 * IP. These modules may have multiple hard-reset lines that reset
148 * take the submodule out of reset and wait until the PRCM indicates
149 * that the reset has completed before returning. Returns 0 upon success or
151 * of reset, or -EBUSY if the submodule did not exit reset promptly.
165 /* Clear the reset status by writing 1 to the status bit */ omap4_prminst_deassert_hardreset()
168 /* de-assert the reset control line */ omap4_prminst_deassert_hardreset()
H A Dprm33xx.c56 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
58 * @shift: register bit shift corresponding to the reset line to check
80 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
81 * @shift: register bit shift corresponding to the reset line to assert
87 * reset line to be asserted / deasserted in order to fully enable the
88 * IP. These modules may have multiple hard-reset lines that reset
90 * place the submodule into reset. Returns 0 upon success or -EINVAL
106 * @shift: register bit shift corresponding to the reset line to deassert
107 * @st_shift: reset status register bit shift corresponding to the reset line
114 * reset line to be asserted / deasserted in order to fully enable the
115 * IP. These modules may have multiple hard-reset lines that reset
117 * take the submodule out of reset and wait until the PRCM indicates
118 * that the reset has completed before returning. Returns 0 upon success or
120 * of reset, or -EBUSY if the submodule did not exit reset promptly.
133 /* Clear the reset status by writing 1 to the status bit */ am33xx_prm_deassert_hardreset()
136 /* de-assert the reset control line */ am33xx_prm_deassert_hardreset()
340 * am33xx_prm_global_warm_sw_reset - reboot the device via warm reset
342 * Immediately reboots the device through warm reset.
H A Dprm2xxx_3xxx.c25 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
27 * @shift: register bit shift corresponding to the reset line to check
43 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
44 * @shift: register bit shift corresponding to the reset line to assert
50 * reset line to be asserted / deasserted in order to fully enable the
51 * IP. These modules may have multiple hard-reset lines that reset
53 * place the submodule into reset. Returns 0 upon success or -EINVAL
69 * @rst_shift: register bit shift corresponding to the reset line to deassert
73 * @rst_offset: reset register offset, not used for OMAP2
74 * @st_offset: reset status register offset, not used for OMAP2
77 * reset line to be asserted / deasserted in order to fully enable the
78 * IP. These modules may have multiple hard-reset lines that reset
80 * take the submodule out of reset and wait until the PRCM indicates
81 * that the reset has completed before returning. Returns 0 upon success or
83 * of reset, or -EBUSY if the submodule did not exit reset promptly.
98 /* Clear the reset status by writing 1 to the status bit */ omap2_prm_deassert_hardreset()
100 /* de-assert the reset control line */ omap2_prm_deassert_hardreset()
H A Dwd_timer.c27 * settings, WDT module is reset during init. This enables the watchdog
28 * timer. Hence it is required to disable the watchdog after the WDT reset
64 * omap2_wdtimer_reset - reset and disable the WDTIMER IP block
67 * After the WDTIMER IP blocks are reset on OMAP2/3, we must also take
71 * re-armed after an OCP soft-reset.) Returns -ETIMEDOUT if the reset
H A Dmsdi.c2 * MSDI IP block reset
47 /* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
51 * omap_msdi_reset - reset the MSDI IP block
55 * fields set inside its CON register for a reset to complete
H A Domap_hwmod_reset.c2 * OMAP IP block custom reset and preprogramming stubs
7 * A small number of IP blocks need custom reset and preprogramming
39 * AESS reset, we must enable autogating after the hwmod code resets
H A Dhdq1w.c7 * Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by
39 * omap_hdq1w_reset - reset the OMAP HDQ1W module
42 * OCP soft reset the HDQ1W IP block. Section 20.6.1.4 "HDQ1W/1-Wire
45 * the reset to succeed, the HDQ1W module's internal clock gate must be
47 * module. In this sense, it's rather similar to the I2C custom reset
H A Dprm2xxx.c38 * reset source ID bit shifts (which is an OMAP SoC-independent
52 * omap2xxx_prm_read_reset_sources - return the last SoC reset source
54 * Return a u32 representing the last reset sources of the SoC. The
55 * returned reset source bits are standardized across OMAP SoCs.
104 * omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC
106 * Set the DPLL reset bit, which should reboot the SoC. This is the
H A Domap_hwmod_common_ipblock_data.c33 .reset = omap_dss_reset,
/linux-4.1.27/include/linux/spi/
H A Difx_modem.h5 unsigned short rst_out; /* modem reset out */
7 unsigned short rst_pmu; /* reset modem */
H A Dcc2520.h22 int reset; member in struct:cc2520_platform_data
/linux-4.1.27/arch/s390/include/asm/
H A Dreset.h16 extern void register_reset_call(struct reset_call *reset);
17 extern void unregister_reset_call(struct reset_call *reset);
/linux-4.1.27/include/linux/mfd/
H A Dds1wm.h7 /* sleep following a reset pulse. Zero */
11 /* a reset pulse/presence detect sequence.*/
/linux-4.1.27/drivers/clk/qcom/
H A Dcommon.c18 #include <linux/reset-controller.h>
23 #include "reset.h"
26 struct qcom_reset_controller reset; member in struct:qcom_cc
82 struct qcom_reset_controller *reset; qcom_cc_really_probe() local
112 reset = &cc->reset; qcom_cc_really_probe()
113 reset->rcdev.of_node = dev->of_node; qcom_cc_really_probe()
114 reset->rcdev.ops = &qcom_reset_ops; qcom_cc_really_probe()
115 reset->rcdev.owner = dev->driver->owner; qcom_cc_really_probe()
116 reset->rcdev.nr_resets = desc->num_resets; qcom_cc_really_probe()
117 reset->regmap = regmap; qcom_cc_really_probe()
118 reset->reset_map = desc->resets; qcom_cc_really_probe()
119 platform_set_drvdata(pdev, &reset->rcdev); qcom_cc_really_probe()
121 ret = reset_controller_register(&reset->rcdev); qcom_cc_really_probe()
H A Dreset.c17 #include <linux/reset-controller.h>
20 #include "reset.h"
59 .reset = qcom_reset,
/linux-4.1.27/arch/arm/mach-omap1/
H A Dreset.c2 * OMAP1 reset support
13 /* ARM_SYSST bit shifts related to SoC reset sources */
19 /* Standardized reset source bits (across all OMAP SoCs) */
41 * omap1_get_reset_sources - return the source of the SoC's last reset
43 * Returns bits that represent the last reset source for the SoC. The
/linux-4.1.27/arch/arm/plat-samsung/
H A Dwatchdog-reset.c1 /* arch/arm/plat-samsung/watchdog-reset.c
8 * Watchdog reset support for Samsung SoCs.
37 pr_err("%s: wdt reset not initialized\n", __func__); samsung_wdt_reset()
53 /* set the watchdog to go and reset... */ samsung_wdt_reset()
58 /* wait for reset to assert... */ samsung_wdt_reset()
61 pr_err("Watchdog reset failed to assert reset\n"); samsung_wdt_reset()
/linux-4.1.27/arch/blackfin/kernel/
H A Dreboot.c14 /* A system soft reset makes external memory unusable so force
19 * reset while the Core B bit (on dual core parts) is cleared by
20 * the core reset.
36 /* Initiate System software reset. */ bfin_reset()
39 /* Due to the way reset is handled in the hardware, we need bfin_reset()
52 /* Clear System software reset */ bfin_reset()
55 /* The BF526 ROM will crash during reset */ bfin_reset()
62 * though as the System state is all reset now. bfin_reset()
73 /* Issue core reset */ bfin_reset()
/linux-4.1.27/drivers/net/can/softing/
H A Dsofting_platform.h33 * reset() function
34 * bring pdev in or out of reset, depending on value
36 int (*reset)(struct platform_device *pdev, int value); member in struct:softing_platform_data
H A Dsofting_cs.c49 .reset = softingcs_reset,
61 .reset = softingcs_reset,
73 .reset = softingcs_reset,
85 .reset = softingcs_reset,
97 .reset = softingcs_reset,
109 .reset = softingcs_reset,
121 .reset = softingcs_reset,
133 .reset = softingcs_reset,
145 .reset = softingcs_reset,
/linux-4.1.27/arch/mips/dec/
H A DMakefile6 kn02-irq.o kn02xa-berr.o platform.o reset.o setup.o time.o
/linux-4.1.27/drivers/acpi/
H A Dreboot.c18 /* ACPI reset register was only introduced with v2 of the FADT */ acpi_reboot()
23 /* Is the reset register supported? The spec says we should be acpi_reboot()
31 /* The reset register can only exist in I/O, Memory or PCI config space acpi_reboot()
35 /* The reset register can only live on bus 0. */ acpi_reboot()
/linux-4.1.27/arch/arm/mach-gemini/
H A DMakefile7 obj-y := irq.o mm.o time.o devices.o gpio.o idle.o reset.o
/linux-4.1.27/arch/mn10300/include/asm/
H A Dreset-regs.h32 #define WDCTR_WDRST 0x40 /* binary counter reset */
35 #define RSTCTR __SYSREG(0xc0001004, u8) /* reset control reg */
36 #define RSTCTR_CHIPRST 0x01 /* chip reset */
37 #define RSTCTR_DBFRST 0x02 /* double fault reset flag */
38 #define RSTCTR_WDTRST 0x04 /* watchdog timer reset flag */
39 #define RSTCTR_WDREN 0x08 /* watchdog timer reset enable */
/linux-4.1.27/drivers/media/tuners/
H A Dtua9001.h41 * RESETN - chip reset
42 * 0 = reset disabled (chip reset off)
43 * 1 = reset enabled (chip reset on)
H A Dfc0011.h19 * @FC0011_FE_CALLBACK_RESET: Request a tuner reset.
/linux-4.1.27/arch/microblaze/kernel/
H A Dreset.c18 static int handle; /* reset pin handle */
25 "hard-reset-gpios", 0); of_platform_reset_gpio_probe()
29 handle, "reset"); of_platform_reset_gpio_probe()
33 ret = gpio_request(handle, "reset"); of_platform_reset_gpio_probe()
71 pr_notice("No reset GPIO present - halting!\n"); gpio_system_reset()
H A DMakefile20 reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
/linux-4.1.27/arch/cris/arch-v10/kernel/
H A Ddma.c231 *R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, reset); cris_free_dma()
233 IO_STATE_VALUE(R_DMA_CH0_CMD, cmd, reset)); cris_free_dma()
236 *R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, reset); cris_free_dma()
238 IO_STATE_VALUE(R_DMA_CH1_CMD, cmd, reset)); cris_free_dma()
241 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, reset); cris_free_dma()
243 IO_STATE_VALUE(R_DMA_CH2_CMD, cmd, reset)); cris_free_dma()
246 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, reset); cris_free_dma()
248 IO_STATE_VALUE(R_DMA_CH3_CMD, cmd, reset)); cris_free_dma()
251 *R_DMA_CH4_CMD = IO_STATE(R_DMA_CH4_CMD, cmd, reset); cris_free_dma()
253 IO_STATE_VALUE(R_DMA_CH4_CMD, cmd, reset)); cris_free_dma()
256 *R_DMA_CH5_CMD = IO_STATE(R_DMA_CH5_CMD, cmd, reset); cris_free_dma()
258 IO_STATE_VALUE(R_DMA_CH5_CMD, cmd, reset)); cris_free_dma()
261 *R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, reset); cris_free_dma()
263 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset)); cris_free_dma()
266 *R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, reset); cris_free_dma()
268 IO_STATE_VALUE(R_DMA_CH7_CMD, cmd, reset)); cris_free_dma()
271 *R_DMA_CH8_CMD = IO_STATE(R_DMA_CH8_CMD, cmd, reset); cris_free_dma()
273 IO_STATE_VALUE(R_DMA_CH8_CMD, cmd, reset)); cris_free_dma()
276 *R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, reset); cris_free_dma()
278 IO_STATE_VALUE(R_DMA_CH9_CMD, cmd, reset)); cris_free_dma()
/linux-4.1.27/arch/arm/mach-prima2/
H A Drstc.c2 * reset controller for CSR SiRFprimaII
18 #include <linux/reset-controller.h>
39 * Writing 0 to this bit de-asserts reset signal of the sirfsoc_reset_module()
41 * delay between the set and clear of reset bit. it could sirfsoc_reset_module()
58 .reset = sirfsoc_reset_module,
/linux-4.1.27/drivers/phy/
H A Dphy-sun9i-usb.c30 #include <linux/reset.h>
47 struct reset_control *reset; member in struct:sun9i_usb_phy
88 ret = reset_control_deassert(phy->reset); sun9i_usb_phy_init()
110 reset_control_assert(phy->reset); sun9i_usb_phy_exit()
149 phy->reset = devm_reset_control_get(dev, "hsic"); sun9i_usb_phy_probe()
150 if (IS_ERR(phy->reset)) { sun9i_usb_phy_probe()
151 dev_err(dev, "failed to get reset control\n"); sun9i_usb_phy_probe()
152 return PTR_ERR(phy->reset); sun9i_usb_phy_probe()
161 phy->reset = devm_reset_control_get(dev, "phy"); sun9i_usb_phy_probe()
162 if (IS_ERR(phy->reset)) { sun9i_usb_phy_probe()
163 dev_err(dev, "failed to get reset control\n"); sun9i_usb_phy_probe()
164 return PTR_ERR(phy->reset); sun9i_usb_phy_probe()
H A Dphy-stih407-usb.c21 #include <linux/reset.h>
77 * Only port reset is asserted, phy global reset is kept untouched stih407_usb2_exit_port()
78 * as other ports may still be active. When all ports are in reset stih407_usb2_exit_port()
81 * reset (like here) or global reset should be equivalent. stih407_usb2_exit_port()
110 dev_err(dev, "failed to ctrl picoPHY reset\n"); stih407_usb2_picophy_probe()
116 dev_err(dev, "failed to ctrl picoPHY reset\n"); stih407_usb2_picophy_probe()
H A Dphy-exynos-mipi-video.c54 u32 val, reset; __set_phy_state() local
57 reset = EXYNOS4_MIPI_PHY_MRESETN; __set_phy_state()
59 reset = EXYNOS4_MIPI_PHY_SRESETN; __set_phy_state()
66 val |= reset; __set_phy_state()
68 val &= ~reset; __set_phy_state()
80 val |= reset; __set_phy_state()
82 val &= ~reset; __set_phy_state()
H A Dphy-sun4i-usb.c35 #include <linux/reset.h>
73 struct reset_control *reset; member in struct:sun4i_usb_phy_data::sun4i_usb_phy
154 ret = reset_control_deassert(phy->reset); sun4i_usb_phy_init()
180 reset_control_assert(phy->reset); sun4i_usb_phy_exit()
287 phy->reset = devm_reset_control_get(dev, name); sun4i_usb_phy_probe()
288 if (IS_ERR(phy->reset)) { sun4i_usb_phy_probe()
289 dev_err(dev, "failed to get reset %s\n", name); sun4i_usb_phy_probe()
290 return PTR_ERR(phy->reset); sun4i_usb_phy_probe()
/linux-4.1.27/drivers/clk/sunxi/
H A Dclk-sun9i-mmc.c22 #include <linux/reset.h>
24 #include <linux/reset-controller.h>
36 struct reset_control *reset; member in struct:sun9i_mmc_clk_data
107 /* one clock/reset pair per word */ sun9i_a80_mmc_config_clk_probe()
126 data->reset = devm_reset_control_get(&pdev->dev, NULL); sun9i_a80_mmc_config_clk_probe()
127 if (IS_ERR(data->reset)) { sun9i_a80_mmc_config_clk_probe()
128 dev_err(&pdev->dev, "Could not get reset control\n"); sun9i_a80_mmc_config_clk_probe()
129 return PTR_ERR(data->reset); sun9i_a80_mmc_config_clk_probe()
132 ret = reset_control_deassert(data->reset); sun9i_a80_mmc_config_clk_probe()
180 reset_control_assert(data->reset); sun9i_a80_mmc_config_clk_probe()
197 reset_control_assert(data->reset); sun9i_a80_mmc_config_clk_remove()
218 MODULE_DESCRIPTION("Allwinner A80 MMC clock/reset Driver");
/linux-4.1.27/drivers/power/reset/
H A Dat91-reset.c2 * Atmel AT91 SAM9 SoCs reset code
52 * reset register it can be left driving the data bus and
133 reason = "general reset"; at91_reset_status()
139 reason = "watchdog reset"; at91_reset_status()
142 reason = "software reset"; at91_reset_status()
145 reason = "user reset"; at91_reset_status()
148 reason = "unknown reset"; at91_reset_status()
180 dev_err(&pdev->dev, "Could not map reset controller address\n"); at91_reset_of_probe()
207 dev_err(&pdev->dev, "Could not map reset controller address\n"); at91_reset_platform_probe()
247 { "at91-sam9260-reset", (unsigned long)at91sam9260_restart },
248 { "at91-sam9g45-reset", (unsigned long)at91sam9g45_restart },
255 .name = "at91-reset",
H A Dkeystone-reset.c61 /* reset the SOC */ rsctrl_restart_handler()
74 {.compatible = "ti,keystone-reset", },
103 dev_err(dev, "couldn't read the reset pll offset!\n"); rsctrl_probe()
113 /* set soft/hard reset */ rsctrl_probe()
114 val = of_property_read_bool(np, "ti,soft-reset"); rsctrl_probe()
125 /* disable a reset isolation for all module clocks */ rsctrl_probe()
130 /* enable a reset for watchdogs from wdt-list */ rsctrl_probe()
173 MODULE_DESCRIPTION("Texas Instruments keystone reset driver");
H A Daxxia-reset.c49 /* Assert chip reset */ axxia_restart_handler()
80 { .compatible = "lsi,axm55xx-reset", },
88 .name = "axxia-reset",
H A Dst-poweroff.c23 /* syscfg used for reset */
26 /* syscfg used for unmask the reset */
80 /* reset syscfg updated */ st_restart()
86 /* unmask the reset */ st_restart()
/linux-4.1.27/arch/arm/mach-spear/
H A Drestart.c24 /* software reset, Jump into ROM at address 0 */ spear_restart()
27 /* hardware reset, Use on-chip reset capability */ spear_restart()
/linux-4.1.27/arch/mips/loongson/lemote-2f/
H A Dreset.c28 * reset cpu to full speed, this is needed when enabling cpu frequency reset_cpu()
34 /* reset support for fuloong2f */
40 /* send a reset signal to south bridge. fl2f_reboot()
42 * NOTE: if enable "Power Management" in kernel, rtl8169 will not reset fl2f_reboot()
43 * normally with this reset operation and it will not work in PMON, but fl2f_reboot()
44 * you can type halt command and then reboot, seems the hardware reset fl2f_reboot()
77 /* reset support for yeeloong2f and mengloong2f notebook */
83 /* sending an reset signal to EC(embedded controller) */ ml2f_reboot()
/linux-4.1.27/arch/mips/sni/
H A Dreset.c12 * controller to pulse the reset-line low. We try that for a while,
37 outb_p(0xfe, 0x64); /* pulse reset low */ sni_machine_restart()
/linux-4.1.27/arch/arc/kernel/
H A Dreset.c22 /* Soft reset : jump to reset vector */ machine_restart()
H A DMakefile11 obj-y := arcksyms.o setup.o irq.o time.o reset.o ptrace.o entry.o process.o
/linux-4.1.27/drivers/net/ethernet/mellanox/mlx4/
H A Dreset.c44 void __iomem *reset; mlx4_reset() local
66 * save off the PCI header before reset and then restore it mlx4_reset()
92 reset = ioremap(pci_resource_start(dev->persist->pdev, 0) + mlx4_reset()
95 if (!reset) { mlx4_reset()
97 mlx4_err(dev, "Couldn't map HCA reset register, aborting\n"); mlx4_reset()
104 sem = readl(reset + MLX4_SEM_OFFSET); mlx4_reset()
114 iounmap(reset); mlx4_reset()
118 /* actually hit reset */ mlx4_reset()
119 writel(MLX4_RESET_VALUE, reset + MLX4_RESET_OFFSET); mlx4_reset()
120 iounmap(reset); mlx4_reset()
136 mlx4_err(dev, "PCI device did not come back after reset, aborting\n"); mlx4_reset()
H A DMakefile4 main.o mcg.o mr.o pd.o port.o profile.o qp.o reset.o sense.o \
H A Dcatas.c79 * link was disabled and chip was already reset. mlx4_reset_master()
86 mlx4_err(dev, "Fail to reset HCA\n"); mlx4_reset_master()
109 mlx4_err(dev, "VF reset is not needed\n"); mlx4_reset_slave()
114 mlx4_err(dev, "VF reset is not supported\n"); mlx4_reset_slave()
123 mlx4_err(dev, "Communication channel isn't sync, fail to send reset\n"); mlx4_reset_slave()
128 mlx4_warn(dev, "VF is sending reset request to Firmware\n"); mlx4_reset_slave()
145 * be reset at any time by the PF and all its bits will be mlx4_reset_slave()
157 mlx4_err(dev, "Fail to send reset over the communication channel\n"); mlx4_reset_slave()
180 mlx4_err(dev, "device is going to be reset\n"); mlx4_enter_error_state()
188 mlx4_err(dev, "device was reset successfully\n"); mlx4_enter_error_state()
191 /* At that step HW was already reset, now notify clients */ mlx4_enter_error_state()
/linux-4.1.27/drivers/watchdog/
H A Dmena21_wdt.c47 int reset = 0; a21_wdt_get_bootstatus() local
49 reset |= gpio_get_value(drv->gpios[GPIO_WD_RST0]) ? (1 << 0) : 0; a21_wdt_get_bootstatus()
50 reset |= gpio_get_value(drv->gpios[GPIO_WD_RST1]) ? (1 << 1) : 0; a21_wdt_get_bootstatus()
51 reset |= gpio_get_value(drv->gpios[GPIO_WD_RST2]) ? (1 << 2) : 0; a21_wdt_get_bootstatus()
53 return reset; a21_wdt_get_bootstatus()
151 unsigned int reset = 0; a21_wdt_probe() local
201 reset = a21_wdt_get_bootstatus(drv); a21_wdt_probe()
202 if (reset == 2) a21_wdt_probe()
204 else if (reset == 4) a21_wdt_probe()
206 else if (reset == 5) a21_wdt_probe()
208 else if (reset == 7) a21_wdt_probe()
H A Dimgpdc_wdt.c35 #define PDC_WDT_TICKLE_STATUS_HRESET 0x0 /* Hard reset */
38 #define PDC_WDT_TICKLE_STATUS_SRESET 0x3 /* Soft reset */
39 #define PDC_WDT_TICKLE_STATUS_USER 0x4 /* User reset */
205 /* Find what caused the last reset */ pdc_wdt_probe()
213 "watchdog module last reset due to timeout\n"); pdc_wdt_probe()
217 "watchdog module last reset due to hard reset\n"); pdc_wdt_probe()
221 "watchdog module last reset due to soft reset\n"); pdc_wdt_probe()
225 "watchdog module last reset due to user reset\n"); pdc_wdt_probe()
H A Dmpc8xxx_wdt.c61 static bool reset = 1; variable
62 module_param(reset, bool, 0);
63 MODULE_PARM_DESC(reset,
64 "Watchdog Interrupt/Reset Mode. 0 = interrupt, 1 = reset");
109 if (reset) mpc8xxx_wdt_start()
195 reset ? "reset" : "interrupt", timeout, timeout_sec); mpc8xxx_wdt_probe()
214 reset ? "reset" : "machine check exception"); mpc8xxx_wdt_remove()
H A Dnv_tco.h39 * TCO Boot Status bit: set on TCO reset, reset by software or standby
/linux-4.1.27/arch/mips/ath25/
H A Dar5312_regs.h100 #define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
101 #define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
102 #define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC/BB */
103 #define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
104 #define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
105 #define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 MAC */
106 #define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 MAC */
107 #define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 */
108 #define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
109 #define AR5312_RESET_APB 0x00000400 /* cold reset APB ar5312 */
110 #define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
111 #define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
112 #define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BB */
114 #define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 MAC */
115 #define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 BB */
116 #define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
117 #define AR5312_RESET_WDOG 0x00100000 /* last reset was a wdt */
H A Dar2315.c184 /* try reset the system via reset control */ ar2315_restart()
187 /* Cold reset does not work on the AR2315/6, use the GPIO reset bits ar2315_restart()
189 * reset (atheros reference design workaround) */ ar2315_restart()
191 /* TODO: implement the GPIO reset workaround */ ar2315_restart()
193 /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic ar2315_restart()
194 * workaround. Attempt to jump to the mips reset location - ar2315_restart()
/linux-4.1.27/drivers/mmc/core/
H A Dpwrseq_emmc.c8 * Simple eMMC hardware reset provider
79 pwrseq->reset_gpio = gpiod_get_index(dev, "reset", 0, GPIOD_OUT_LOW); mmc_pwrseq_emmc_alloc()
86 * register reset handler to ensure emmc reset also from mmc_pwrseq_emmc_alloc()
/linux-4.1.27/drivers/oprofile/
H A Doprofile_stats.h25 /* reset all stats to zero */
/linux-4.1.27/drivers/clk/mmp/
H A Dreset.h4 #include <linux/reset-controller.h>
H A Dreset.c5 #include <linux/reset-controller.h>
7 #include "reset.h"
/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/reset-controller/
H A Dstih415-resets.h2 * This header provides constants for the reset controller
H A Dstih407-resets.h2 * This header provides constants for the reset controller
56 /* Picophy reset defines */
H A Dstih416-resets.h2 * This header provides constants for the reset controller
/linux-4.1.27/drivers/uwb/
H A DMakefile22 reset.o \
/linux-4.1.27/arch/mips/mti-malta/
H A DMakefile10 malta-reset.o malta-setup.o malta-time.o
/linux-4.1.27/arch/mips/ralink/
H A Dreset.c14 #include <linux/reset-controller.h>
62 .reset = ralink_reset_device,
77 "ralink,rt2880-reset"); ralink_rst_init()
79 pr_err("Failed to find reset controller node"); ralink_rst_init()
H A DMakefile9 obj-y := prom.o of.o reset.o clk.o irq.o timer.o
/linux-4.1.27/arch/mips/sgi-ip27/
H A DMakefile6 ip27-memory.o ip27-nmi.o ip27-reset.o ip27-timer.o ip27-hubio.o \
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/reset-controller/
H A Dstih415-resets.h2 * This header provides constants for the reset controller
H A Dstih407-resets.h2 * This header provides constants for the reset controller
56 /* Picophy reset defines */
H A Dstih416-resets.h2 * This header provides constants for the reset controller
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/reset-controller/
H A Dstih415-resets.h2 * This header provides constants for the reset controller
H A Dstih407-resets.h2 * This header provides constants for the reset controller
56 /* Picophy reset defines */
H A Dstih416-resets.h2 * This header provides constants for the reset controller
/linux-4.1.27/arch/hexagon/kernel/
H A DMakefile6 obj-y += process.o trampoline.o reset.o ptrace.o vdso.o
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/reset-controller/
H A Dstih415-resets.h2 * This header provides constants for the reset controller
H A Dstih407-resets.h2 * This header provides constants for the reset controller
56 /* Picophy reset defines */
H A Dstih416-resets.h2 * This header provides constants for the reset controller
/linux-4.1.27/arch/arm/mach-pxa/
H A Dreset.c15 #include <mach/reset.h>
29 rc = gpio_request(gpio, "reset generator"); init_gpio_reset()
53 * Trigger GPIO reset.
86 * SDRAM hangs on watchdog reset on Marvell PXA270 (erratum 71) do_hw_reset()
/linux-4.1.27/arch/arm/mach-mvebu/
H A DMakefile10 obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o pm.o pm-board.o
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/reset-controller/
H A Dstih415-resets.h2 * This header provides constants for the reset controller
H A Dstih407-resets.h2 * This header provides constants for the reset controller
56 /* Picophy reset defines */
H A Dstih416-resets.h2 * This header provides constants for the reset controller
/linux-4.1.27/include/dt-bindings/reset-controller/
H A Dstih415-resets.h2 * This header provides constants for the reset controller
H A Dstih407-resets.h2 * This header provides constants for the reset controller
56 /* Picophy reset defines */
H A Dstih416-resets.h2 * This header provides constants for the reset controller
/linux-4.1.27/arch/x86/kernel/
H A Dreboot_fixups_32.c19 /* writing 1 to the reset control register, 0x44 causes the cs5530a_warm_reset()
20 cs5530a to perform a system warm reset */ cs5530a_warm_reset()
28 /* writing 1 to the LSB of this MSR causes a hard reset */ cs5536_warm_reset()
36 /* Voluntary reset the watchdog timer */ rdc321x_reset()
38 /* Generate a CPU reset on next tick */ rdc321x_reset()
/linux-4.1.27/arch/mips/include/asm/dec/
H A Dkn02ca.h32 #define KN02CA_IO_INR_POWERON 13 /* (*) ACCESS.Bus/power-on reset */
68 #define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */
70 #define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */
71 #define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */
72 #define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */
/linux-4.1.27/arch/arm/mach-tegra/
H A Dreset.c2 * arch/arm/mach-tegra/reset.c
30 #include "reset.h"
46 * NOTE: This must be the one and only write to the EVP CPU reset tegra_cpu_reset_handler_set()
54 * Prevent further modifications to the physical reset vector. tegra_cpu_reset_handler_set()
85 pr_crit("Cannot set CPU reset handler: %d\n", err); tegra_cpu_reset_handler_enable()
H A Dplatsmp.c35 #include "reset.h"
50 * Force the CPU into reset. The CPU must remain in reset when tegra20_boot_secondary()
52 * flow controller to stop driving reset if the CPU has been tegra20_boot_secondary()
55 * in reset. tegra20_boot_secondary()
62 * stop driving reset. The CPU will remain in reset because the tegra20_boot_secondary()
63 * clock and reset block is now driving reset. tegra20_boot_secondary()
/linux-4.1.27/arch/sparc/include/asm/
H A Dfhc.h30 #define FHC_RCS_POR 0x80000000 /* Last reset was a power cycle */
31 #define FHC_RCS_SPOR 0x40000000 /* Last reset was sw power on reset */
32 #define FHC_RCS_SXIR 0x20000000 /* Last reset was sw XIR reset */
33 #define FHC_RCS_BPOR 0x10000000 /* Last reset was due to POR button */
34 #define FHC_RCS_BXIR 0x08000000 /* Last reset was due to XIR button */
35 #define FHC_RCS_WEVENT 0x04000000 /* CPU reset was due to wakeup event */
37 #define FHC_RCS_FENAB 0x01000000 /* Fatal errors elicit system reset */
H A Dbbc.h91 #define BBC_WDACTION_RST 0x01 /* When set, watchdog causes system reset.
103 #define BBC_SPG_CPUALL 0x10 /* Reset all processors and reset
118 * reset by reading this register.
120 #define BBC_PSRC_SPG0 0x0001 /* CPU 0 reset via BBC_SPG register */
121 #define BBC_PSRC_SPG1 0x0002 /* CPU 1 reset via BBC_SPG register */
122 #define BBC_PSRC_SPG2 0x0004 /* CPU 2 reset via BBC_SPG register */
123 #define BBC_PSRC_SPG3 0x0008 /* CPU 3 reset via BBC_SPG register */
124 #define BBC_PSRC_SPGSYS 0x0010 /* System reset via BBC_SPG register */
125 #define BBC_PSRC_JTAG 0x0020 /* System reset via JTAG+ */
126 #define BBC_PSRC_BUTTON 0x0040 /* System reset via push-button dongle */
127 #define BBC_PSRC_PWRUP 0x0080 /* System reset via power-up */
135 #define BBC_PSRC_SYNTH 0x8000 /* System reset when on-board clock synthesizers
138 #define BBC_PSRC_WDT 0x10000 /* System reset via Super I/O watchdog */
139 #define BBC_PSRC_RSC 0x20000 /* System reset via RSC remote monitoring
164 #define BBC_CSC_RST 0x80 /* Generate system reset when S_LOAD==1 */
/linux-4.1.27/arch/arm/mach-bcm/
H A Dboard_bcm2835.c74 * We can't really power off, but if we do the normal reset scheme, and
83 * We set the watchdog hard reset bit here to distinguish this reset bcm2835_power_off()
84 * from the normal (full) reset. bootcode.bin will not reboot after a bcm2835_power_off()
85 * hard reset. bcm2835_power_off()
92 /* Continue with normal reset mechanism */ bcm2835_power_off()
H A Dboard_bcm21664.c48 * A soft reset is triggered by writing a 0 to bit 0 of the soft reset bcm21664_restart()
57 /* Wait for reset */ bcm21664_restart()
/linux-4.1.27/arch/arm/mach-ks8695/
H A Dboard-og.c52 * The PCI bus reset is driven by a dedicated GPIO line. Toggle it here
53 * and bring the PCI bus out of reset.
59 /* Some boards use a different GPIO as the PCI reset line */ og_pci_bus_reset()
65 gpio_request(rstline, "PCI reset"); og_pci_bus_reset()
68 /* Drive a reset on the PCI reset line */ og_pci_bus_reset()
/linux-4.1.27/sound/core/seq/oss/
H A Dseq_oss_writeq.c75 * reset the write queue
80 struct snd_seq_remove_events reset; snd_seq_oss_writeq_clear() local
82 memset(&reset, 0, sizeof(reset)); snd_seq_oss_writeq_clear()
83 reset.remove_mode = SNDRV_SEQ_REMOVE_OUTPUT; /* remove all */ snd_seq_oss_writeq_clear()
84 snd_seq_oss_control(q->dp, SNDRV_SEQ_IOCTL_REMOVE_EVENTS, &reset); snd_seq_oss_writeq_clear()
/linux-4.1.27/arch/powerpc/platforms/52xx/
H A Dmpc52xx_common.c252 * It effectively does a reset. */ mpc52xx_restart()
275 * mpc5200_psc_ac97_gpio_reset: Use gpio pins to reset the ac97 bus
277 * @psc: psc number to reset (only psc 1 and 2 support ac97)
285 int reset; mpc5200_psc_ac97_gpio_reset() local
293 reset = PSC1_RESET; /* AC97_1_RES */ mpc5200_psc_ac97_gpio_reset()
299 reset = PSC2_RESET; /* AC97_2_RES */ mpc5200_psc_ac97_gpio_reset()
306 "cold-reset will be performed\n"); mpc5200_psc_ac97_gpio_reset()
317 setbits8(&wkup_gpio->wkup_gpioe, reset); mpc5200_psc_ac97_gpio_reset()
320 setbits8(&wkup_gpio->wkup_ddr, reset); mpc5200_psc_ac97_gpio_reset()
323 /* Assert cold reset */ mpc5200_psc_ac97_gpio_reset()
325 clrbits8(&wkup_gpio->wkup_dvo, reset); mpc5200_psc_ac97_gpio_reset()
330 /* Deassert reset */ mpc5200_psc_ac97_gpio_reset()
331 setbits8(&wkup_gpio->wkup_dvo, reset); mpc5200_psc_ac97_gpio_reset()
/linux-4.1.27/drivers/media/pci/sta2x11/
H A Dsta2x11_vip.h28 * @reset_name: ADV reset name
29 * @reset_pin: ADV reset pin
/linux-4.1.27/arch/mips/pmcs-msp71xx/
H A Dmsp_setup.c35 * Performs the reset for MSP7120-based boards
48 /* Cache the reset code of this function */ msp7120_reset()
84 * Set GPIO 9 HI, (tied to board reset logic) msp7120_reset()
95 * In case GPIO9 doesn't reset the board (jumper configurable!) msp7120_reset()
96 * fallback to device reset below. msp7120_reset()
99 /* Set bit 1 of the MSP7120 reset register */ msp7120_reset()
117 /* No chip-specific reset code, just jump to the ROM reset vector */ msp_restart()
/linux-4.1.27/include/linux/dma/
H A Dxilinx_dma.h28 * @reset: Reset Channel
40 int reset; member in struct:xilinx_vdma_config
/linux-4.1.27/arch/mips/mti-sead3/
H A DMakefile12 sead3-int.o sead3-platform.o sead3-reset.o \
/linux-4.1.27/arch/arm/mach-sa1100/include/mach/
H A Dh3xxx.h64 #define H3XXX_EGPIO_CARD_RESET (H3XXX_EGPIO_BASE + 1) /* reset the attached pcmcia/compactflash card. active high. */
65 #define H3XXX_EGPIO_OPT_RESET (H3XXX_EGPIO_BASE + 2) /* reset the attached option pack. active high. */
66 #define H3XXX_EGPIO_CODEC_NRESET (H3XXX_EGPIO_BASE + 3) /* reset the onboard UDA1341. active low. */
76 #define H3600_EGPIO_AUD_PWR_ON (H3XXX_EGPIO_BASE + 11) /* apply power to reset of audio circuit. active high. */
/linux-4.1.27/arch/arm/plat-samsung/include/plat/
H A Dwatchdog-reset.h1 /* arch/arm/plat-s3c/include/plat/watchdog-reset.h
/linux-4.1.27/arch/arm/mach-cns3xxx/
H A Dpm.c63 * bit 0, 28, 29 => program low to reset, cns3xxx_pwr_soft_rst_force()
82 /* SPI/I2C/GPIO use the same block, reset once. */ cns3xxx_pwr_soft_rst()
94 * To reset, we hit the on-board reset register cns3xxx_restart()
/linux-4.1.27/arch/arm/mach-imx/
H A Dsrc.c17 #include <linux/reset-controller.h>
77 .reset = imx_src_reset_module,
134 * force warm reset sources to generate cold reset imx_src_init()
/linux-4.1.27/Documentation/mic/mpssd/
H A Dmicctrl58 echo reset > $f/state
61 reset() function
157 reset $2
169 echo $"Usage: $0 {-s (status) |-r (reset) |-b (boot) |-S (shutdown) |-w (wait)}"
/linux-4.1.27/arch/alpha/oprofile/
H A Dop_model_ev6.c24 unsigned long ctl, reset, need_reset, i; ev6_reg_setup() local
45 reset = need_reset = 0; ev6_reg_setup()
54 reset |= (0x100000 - count) << (i ? 6 : 28); ev6_reg_setup()
58 reg->reset_values = reset; ev6_reg_setup()
/linux-4.1.27/include/linux/clk/
H A Dtegra.h23 * Tegra CPU clock and reset control ops
26 * keep waiting until the CPU in reset state
28 * put the CPU in reset state
30 * release the CPU from reset state
/linux-4.1.27/drivers/media/pci/cx18/
H A Dcx18-gpio.c43 * gpio0: zilog ir process reset pin
45 * gpio12: cx24227 reset pin
46 * gpio13: cs5345 reset pin
236 * 3. DBG pin must be high before chip exits reset for normal resetctrl_reset()
240 * 4. Z8F0811 won't exit reset until RESET is deasserted resetctrl_reset()
241 * 5. Zilog comes out of reset, loads reset vector address and resetctrl_reset()
258 .reset = resetctrl_reset,
309 str = "gpio-reset-ctrl"; cx18_gpio_register()
332 core, reset, CX18_GPIO_RESET_Z8F0811); cx18_reset_ir_gpio()
337 /* Xceive tuner reset function */ cx18_reset_tuner_gpio()
350 core, reset, CX18_GPIO_RESET_XC2028); cx18_reset_tuner_gpio()
/linux-4.1.27/drivers/media/pci/mantis/
H A Dhopper_vp3028.c50 mantis_gpio_set_bits(mantis, config->reset, 0); vp3028_frontend_init()
54 mantis_gpio_set_bits(mantis, config->reset, 1); vp3028_frontend_init()
87 .reset = GPIF_A03,
H A Dmantis_vp3030.c62 mantis_gpio_set_bits(mantis, config->reset, 0); vp3030_frontend_init()
66 mantis_gpio_set_bits(mantis, config->reset, 1); vp3030_frontend_init()
102 .reset = GPIF_A13,
/linux-4.1.27/arch/xtensa/platforms/iss/
H A Dsetup.c54 /* Flush and reset the mmu, simulate a processor reset, and platform_restart()
55 * jump to the reset vector. */ platform_restart()
/linux-4.1.27/arch/mips/alchemy/common/
H A Dvss.c26 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ __enable_block()
45 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ __enable_block()
61 __raw_writel(3, base + VSS_CLKRST); /* assert reset */ __disable_block()
/linux-4.1.27/include/net/
H A Dllc_if.h55 #define LLC_STATUS_CONN 0 /* connect confirm & reset confirm */
56 #define LLC_STATUS_DISC 1 /* connect confirm & reset confirm */
57 #define LLC_STATUS_FAILED 2 /* connect confirm & reset confirm */
/linux-4.1.27/include/linux/usb/
H A Dquirks.h13 /* device can't resume correctly so reset it instead */
22 /* device can't be reset(e.g morph devices), don't use reset */
H A Dsl811.h22 void (*reset)(struct device *dev); member in struct:sl811_platform_data
/linux-4.1.27/arch/blackfin/mach-bf561/
H A Dcoreb.c7 /* The Core B reset func requires code in the application that is loaded into
8 * Core B. In order to reset, the application needs to install an interrupt
11 * B to stall when Supplemental Interrupt 0 is set, and will reset PC to
/linux-4.1.27/lib/
H A Dstmp_device.c27 * a reset address and mask being either SFTRST(bit 31) or CLKGATE
55 /* set SFTRST to reset the block */ stmp_reset_block()
78 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr); stmp_reset_block()
/linux-4.1.27/drivers/media/pci/cx23885/
H A Dcx23885-cards.c1252 * we need to reset the correct gpio. */ cx23885_tuner_callback()
1272 /* Drive the tuner into reset and back out */ cx23885_tuner_callback()
1285 /* GPIO-0 cx24227 demodulator reset */ cx23885_gpio_setup()
1286 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ cx23885_gpio_setup()
1292 /* Put the parts into reset */ cx23885_gpio_setup()
1297 /* Bring the parts out of reset */ cx23885_gpio_setup()
1301 /* GPIO-0 cx24227 demodulator reset */ cx23885_gpio_setup()
1302 /* GPIO-2 xc5000 tuner reset */ cx23885_gpio_setup()
1303 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */ cx23885_gpio_setup()
1319 /* Put the demod into reset and protect the eeprom */ cx23885_gpio_setup()
1323 /* Bring the demod and blaster out of reset */ cx23885_gpio_setup()
1327 /* Force the TDA8295A into reset and back */ cx23885_gpio_setup()
1337 /* GPIO-0 tda10048 demodulator reset */ cx23885_gpio_setup()
1338 /* GPIO-2 tda18271 tuner reset */ cx23885_gpio_setup()
1340 /* Put the parts into reset and back */ cx23885_gpio_setup()
1348 /* GPIO-0 TDA10048 demodulator reset */ cx23885_gpio_setup()
1361 /* Put the parts into reset and back */ cx23885_gpio_setup()
1369 /* GPIO-0 Dibcom7000p demodulator reset */ cx23885_gpio_setup()
1370 /* GPIO-2 xc3028L tuner reset */ cx23885_gpio_setup()
1373 /* Put the parts into reset and back */ cx23885_gpio_setup()
1381 /* GPIO-0 xc5000 tuner reset i2c bus 0 */ cx23885_gpio_setup()
1382 /* GPIO-1 s5h1409 demod reset i2c bus 0 */ cx23885_gpio_setup()
1383 /* GPIO-2 xc5000 tuner reset i2c bus 1 */ cx23885_gpio_setup()
1384 /* GPIO-3 s5h1409 demod reset i2c bus 0 */ cx23885_gpio_setup()
1386 /* Put the parts into reset and back */ cx23885_gpio_setup()
1395 /* GPIO-0 portb xc3028 reset */ cx23885_gpio_setup()
1396 /* GPIO-1 portb zl10353 reset */ cx23885_gpio_setup()
1397 /* GPIO-2 portc xc3028 reset */ cx23885_gpio_setup()
1398 /* GPIO-3 portc zl10353 reset */ cx23885_gpio_setup()
1400 /* Put the parts into reset and back */ cx23885_gpio_setup()
1413 /* GPIO-2 xc3028 tuner reset */ cx23885_gpio_setup()
1416 /* GPIO-? zl10353 demod reset */ cx23885_gpio_setup()
1418 /* Put the parts into reset and back */ cx23885_gpio_setup()
1441 GPIO-2 reset chips cx23885_gpio_setup()
1452 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */ cx23885_gpio_setup()
1454 mdelay(100);/* reset delay */ cx23885_gpio_setup()
1455 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */ cx23885_gpio_setup()
1471 /* GPIO-9 Demod reset */ cx23885_gpio_setup()
1473 /* Put the parts into reset and back */ cx23885_gpio_setup()
1484 /* GPIO-1 reset XC5000 */ cx23885_gpio_setup()
1485 /* GPIO-2 demod reset */ cx23885_gpio_setup()
1493 /* GPIO-0 reset first ATBM8830 */ cx23885_gpio_setup()
1494 /* GPIO-1 reset second ATBM8830 */ cx23885_gpio_setup()
1521 /* Put the demod into reset and protect the eeprom */ cx23885_gpio_setup()
1525 /* Bring the demod out of reset */ cx23885_gpio_setup()
1533 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ cx23885_gpio_setup()
1538 GPIO-2 ~reset chips out cx23885_gpio_setup()
1550 /* GPIO-0 as INT, reset & TMS low */ cx23885_gpio_setup()
1552 mdelay(100);/* reset delay */ cx23885_gpio_setup()
1553 cx_set(GP0_IO, 0x00000004); /* reset high */ cx23885_gpio_setup()
1564 /* GPIO-8 tda10071 demod reset */ cx23885_gpio_setup()
1565 /* GPIO-9 si2165 demod reset (only HVR4400/HVR5500)*/ cx23885_gpio_setup()
1567 /* Put the parts into reset and back */ cx23885_gpio_setup()
1581 /* AF9013 demod reset */ cx23885_gpio_setup()
1596 /* XC3028L tuner reset */ cx23885_gpio_setup()
1617 * GPIO-1 reset CiMax, output, high active cx23885_gpio_setup()
1618 * GPIO-2 reset demod, output, low active cx23885_gpio_setup()
1631 mdelay(100); /* reset delay */ cx23885_gpio_setup()
1632 cx_set(GP0_IO, 0x00060004); /* GPIO as out, reset high */ cx23885_gpio_setup()
1667 /* Put the parts into reset and back */ cx23885_gpio_setup()
/linux-4.1.27/drivers/isdn/sc/
H A Dtimer.c25 * Write the proper values into the I/O ports following a reset
38 * Timed function to check the status of a previous reset
42 * Setup the ioports for the board that were cleared by the reset.
79 * Timed function to check the status of a previous reset
85 * tell IADN4Linux that it is up. Always reset the timer to
/linux-4.1.27/drivers/media/usb/dvb-usb/
H A Ddvb-usb-firmware.c39 u8 reset; usb_cypress_load_firmware() local
43 reset = 1; usb_cypress_load_firmware()
44 if ((ret = usb_cypress_writemem(udev,cypress[type].cpu_cs_register,&reset,1)) != 1) usb_cypress_load_firmware()
66 reset = 0; usb_cypress_load_firmware()
67 if (ret || usb_cypress_writemem(udev,cypress[type].cpu_cs_register,&reset,1) != 1) { usb_cypress_load_firmware()
/linux-4.1.27/drivers/isdn/hisax/
H A Disurf.c126 release_region(cs->hw.isurf.reset, 1); release_io_isurf()
136 byteout(cs->hw.isurf.reset, chips); /* Reset On */ reset_isurf()
138 byteout(cs->hw.isurf.reset, ISURF_ISAR_EA); /* Reset Off */ reset_isurf()
212 cs->hw.isurf.reset = card->para[1]; setup_isurf()
238 cs->hw.isurf.reset = pnp_port_start(pnp_d, 0); setup_isurf()
241 if (!cs->irq || !cs->hw.isurf.reset || !cs->hw.isurf.phymem) { setup_isurf()
243 cs->irq, cs->hw.isurf.reset, cs->hw.isurf.phymem); setup_isurf()
260 if (!request_region(cs->hw.isurf.reset, 1, "isurf isdn")) { setup_isurf()
263 cs->hw.isurf.reset); setup_isurf()
271 release_region(cs->hw.isurf.reset, 1); setup_isurf()
278 cs->hw.isurf.reset, setup_isurf()
/linux-4.1.27/drivers/net/irda/
H A Dmcp2120-sir.c48 .reset = mcp2120_reset,
66 /* seems no explicit power-on required here and reset switching it on anyway */ mcp2120_open()
78 /* reset and inhibit mcp2120 */ mcp2120_close()
166 * Info: -set RTS to reset mcp2120
168 * -mcp2120 defaults to 9600 baud after reset
171 * 0. Set RTS to reset mcp2120.
172 * 1. Clear RTS and wait for device reset timer of 30 ms (max).
/linux-4.1.27/drivers/video/backlight/
H A Dbd6107.c100 gpio_set_value(bd->pdata->reset, 0); bd6107_backlight_update_status()
102 gpio_set_value(bd->pdata->reset, 1); bd6107_backlight_update_status()
131 if (pdata == NULL || !pdata->reset) { bd6107_probe()
132 dev_err(&client->dev, "No reset GPIO in platform data\n"); bd6107_probe()
150 ret = devm_gpio_request_one(&client->dev, pdata->reset, bd6107_probe()
151 GPIOF_DIR_OUT | GPIOF_INIT_LOW, "reset"); bd6107_probe()
153 dev_err(&client->dev, "unable to request reset GPIO\n"); bd6107_probe()
/linux-4.1.27/arch/powerpc/sysdev/
H A Dppc4xx_soc.c195 * Apply a system reset. Alternatively a board specific value may be
196 * provided via the "reset-type" property in the cpu node.
206 prop = of_get_property(np, "reset-type", NULL); ppc4xx_reset_system()
210 * 1 - PPC4xx core reset ppc4xx_reset_system()
211 * 2 - PPC4xx chip reset ppc4xx_reset_system()
212 * 3 - PPC4xx system reset (default) ppc4xx_reset_system()
221 ; /* Just in case the reset doesn't work */ ppc4xx_reset_system()
/linux-4.1.27/arch/arm/kernel/
H A Dreboot.c28 * A temporary stack to use for CPU reset. This is static so that we
31 * should really do as little as possible before jumping to your reset
72 /* Change to the new stack and continue with the reset. */ _soft_restart()
131 * will cause the only available CPU to reset. Systems with multiple CPUs must
132 * provide a HW restart implementation, to ensure that all CPUs reset at once.
133 * This is required so that any code running after reset on the primary CPU
135 * executing pre-reset code, and using RAM that the primary CPU's code wishes
/linux-4.1.27/drivers/input/keyboard/
H A Dsunkbd.c85 volatile s8 reset; member in struct:sunkbd
99 if (sunkbd->reset <= -1) { sunkbd_interrupt()
101 * If cp[i] is 0xff, sunkbd->reset will stay -1. sunkbd_interrupt()
104 sunkbd->reset = data; sunkbd_interrupt()
119 sunkbd->reset = -1; sunkbd_interrupt()
196 sunkbd->reset = -2; sunkbd_initialize()
198 wait_event_interruptible_timeout(sunkbd->wait, sunkbd->reset >= 0, HZ); sunkbd_initialize()
199 if (sunkbd->reset < 0) sunkbd_initialize()
202 sunkbd->type = sunkbd->reset; sunkbd_initialize()
227 wait_event_interruptible_timeout(sunkbd->wait, sunkbd->reset >= 0, HZ); sunkbd_reinit()
/linux-4.1.27/drivers/video/fbdev/via/
H A Dvia_clock.c59 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ cle266_set_primary_pll_encoded()
62 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ cle266_set_primary_pll_encoded()
67 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ k800_set_primary_pll_encoded()
71 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ k800_set_primary_pll_encoded()
76 via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */ cle266_set_secondary_pll_encoded()
79 via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */ cle266_set_secondary_pll_encoded()
84 via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */ k800_set_secondary_pll_encoded()
88 via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */ k800_set_secondary_pll_encoded()
93 via_write_reg_mask(VIASR, 0x40, 0x01, 0x01); /* enable reset */ set_engine_pll_encoded()
97 via_write_reg_mask(VIASR, 0x40, 0x00, 0x01); /* disable reset */ set_engine_pll_encoded()
/linux-4.1.27/sound/soc/
H A Dsoc-ac97.c175 state = pinctrl_lookup_state(p, "ac97-reset"); snd_soc_ac97_parse_pinctl()
177 dev_err(dev, "Can't find pinctrl state ac97-reset\n"); snd_soc_ac97_parse_pinctl()
182 state = pinctrl_lookup_state(p, "ac97-warm-reset"); snd_soc_ac97_parse_pinctl()
184 dev_err(dev, "Can't find pinctrl state ac97-warm-reset\n"); snd_soc_ac97_parse_pinctl()
222 dev_err(dev, "Can't find ac97-reset gpio\n"); snd_soc_ac97_parse_pinctl()
225 ret = devm_gpio_request(dev, gpio, "AC97 link reset"); snd_soc_ac97_parse_pinctl()
227 dev_err(dev, "Failed requesting ac97-reset gpio\n"); snd_soc_ac97_parse_pinctl()
254 * snd_soc_set_ac97_ops_of_reset - Set ac97 ops with generic ac97 reset functions
256 * This function sets the reset and warm_reset properties of ops and parses
275 ops->reset = snd_soc_ac97_reset; snd_soc_set_ac97_ops_of_reset()
/linux-4.1.27/drivers/media/platform/s5p-mfc/
H A Ds5p_mfc_ctrl.c169 /* check bus reset control before reset */ s5p_mfc_reset()
175 * V6 needs RISC_ON set to 0 during reset also. s5p_mfc_reset()
184 /* reset RISC */ s5p_mfc_reset()
186 /* All reset except for MC */ s5p_mfc_reset()
248 /* 0. MFC reset */ s5p_mfc_init_hw()
249 mfc_debug(2, "MFC reset..\n"); s5p_mfc_init_hw()
254 mfc_err("Failed to reset MFC - timeout\n"); s5p_mfc_init_hw()
257 mfc_debug(2, "Done MFC reset..\n"); s5p_mfc_init_hw()
262 /* 3. Release reset signal to the RISC */ s5p_mfc_init_hw()
360 /* Release reset signal to the RISC */ s5p_mfc_v8_wait_wakeup()
365 mfc_err("Failed to reset MFCV8\n"); s5p_mfc_v8_wait_wakeup()
393 /* Release reset signal to the RISC */ s5p_mfc_wait_wakeup()
413 /* 0. MFC reset */ s5p_mfc_wakeup()
414 mfc_debug(2, "MFC reset..\n"); s5p_mfc_wakeup()
419 mfc_err("Failed to reset MFC - timeout\n"); s5p_mfc_wakeup()
423 mfc_debug(2, "Done MFC reset..\n"); s5p_mfc_wakeup()
/linux-4.1.27/drivers/staging/fbtft/
H A Dfbtft_device.c64 "List of gpios. Comma separated with the form: reset:23,dc:24 " \
217 { "reset", 25 },
240 { "reset", 25 },
261 { "reset", 25 },
280 { "reset", 25 },
300 { "reset", 25 },
318 { "reset", 25 },
354 { "reset", 13 },
375 { "reset", 25 },
396 { "reset", 25 },
410 { "reset", 25 },
425 { "reset", 17 },
456 { "reset", 24 },
474 { "reset", 25 },
495 { "reset", 25 },
517 { "reset", 25 },
538 { "reset", 25 },
560 { "reset", 7 },
609 { "reset", 25 },
629 { "reset", 25 },
649 { "reset", 25 },
663 { "reset", 25 },
679 { "reset", 25 },
697 { "reset", 25 },
736 { "reset", 25 },
775 { "reset", 24 },
802 { "reset", 23 },
822 { "reset", 25 },
840 { "reset", 25 },
922 { "reset", 25 },
953 { "reset", 24 },
972 { "reset", 25 },
992 { "reset", 25 },
1012 { "reset", 15 },
1032 { "reset", 15 },
1050 { "reset", 24 },
1070 { "reset", 27 },
1087 { "reset", 24 },
/linux-4.1.27/arch/x86/realmode/rm/
H A Dreboot.S10 * mode and jumping to the BIOS reset entry point, as if the CPU has
11 * really been reset. The previous version asked the keyboard
12 * controller to pulse the CPU reset line, which is more thorough, but
68 * switch to real mode and jump to the BIOS reset code.
80 * is more like the state of a 486 after reset. I don't know if
83 * More could be done here to set up the registers as if a CPU reset had
/linux-4.1.27/drivers/misc/mei/
H A Dinit.c106 * Return: 0 on success or < 0 if the reset hasn't succeeded
121 dev_warn(dev->dev, "unexpected reset: dev_state = %s fw status = %s\n", mei_reset()
125 /* we're already in reset, cancel the init timer mei_reset()
126 * if the reset was called due the hbm protocol error mei_reset()
132 /* enter reset flow */ mei_reset()
138 dev_err(dev->dev, "reset: reached maximal consecutive resets: disabling the device\n"); mei_reset()
144 /* fall through and remove the sw state even if hw reset has failed */ mei_reset()
176 dev_dbg(dev->dev, "powering down: end of reset\n"); mei_reset()
219 dev_dbg(dev->dev, "reset in start the mei device.\n"); mei_start()
227 dev_err(dev->dev, "reset failed ret = %d", ret); mei_start()
234 dev_err(dev->dev, "reset failed"); mei_start()
323 /* retry reset in case of failure */ mei_reset_work()
/linux-4.1.27/arch/mips/bcm63xx/
H A Dsetup.c36 /* soft reset all blocks */ bcm6348_a1_reboot()
49 printk(KERN_INFO "jumping to reset vector.\n"); bcm6348_a1_reboot()
113 printk(KERN_INFO "triggering watchdog soft-reset...\n"); bcm63xx_machine_reboot()
/linux-4.1.27/drivers/gpu/drm/sti/
H A Dsti_hdmi.h46 * @reset: reset control of the hdmi phy
65 struct reset_control *reset; member in struct:sti_hdmi
H A Dsti_compositor.h59 * @rst_main: reset control of the main path
60 * @rst_aux: reset control of the aux path
/linux-4.1.27/drivers/usb/wusbcore/
H A Dwa-hc.c86 * wa_reset_all - reset the WA device
87 * @wa: the WA to be reset
89 * For HWAs the radio controller and all other PALs are also reset.
/linux-4.1.27/arch/powerpc/platforms/83xx/
H A Dmisc.c30 /* map reset restart_reg_baseister space */ mpc83xx_restart_init()
47 /* enable software reset "RSTE" */ mpc83xx_restart()
50 /* set software hard reset */ mpc83xx_restart()
/linux-4.1.27/arch/arm64/kvm/
H A Dreset.c5 * Derived from arch/arm/kvm/reset.c
75 * kvm_reset_vcpu - sets core registers and sys_regs to reset value
79 * the virtual CPU struct to their architectually defined reset
H A DMakefile20 kvm-$(CONFIG_KVM_ARM_HOST) += guest.o reset.o sys_regs.o sys_regs_generic_v8.o
/linux-4.1.27/arch/arm/mach-shmobile/
H A Dpm-rcar-gen2.c92 /* setup reset vectors */
99 /* de-assert reset for CA15 CPUs */
107 /* de-assert reset for CA7 CPUs */
/linux-4.1.27/arch/arm/kvm/
H A Dreset.c47 * Exported reset function
51 * kvm_reset_vcpu - sets core registers and cp15 registers to reset value
55 * virtual CPU struct to their architectually defined reset values.
H A DMakefile21 obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
/linux-4.1.27/net/ceph/
H A Dauth_none.c14 static void reset(struct ceph_auth_client *ac) reset() function
110 .reset = reset,
/linux-4.1.27/sound/soc/codecs/
H A Dstac9766.c253 soc_ac97_ops->reset(ac97); stac9766_reset()
264 u16 id, reset; stac9766_codec_resume() local
266 reset = 0; stac9766_codec_resume()
267 /* give the codec an AC97 warm reset to start the link */ stac9766_codec_resume()
268 reset: stac9766_codec_resume()
269 if (reset > 5) { stac9766_codec_resume()
277 reset++; stac9766_codec_resume()
278 goto reset; stac9766_codec_resume()
342 /* do a cold reset for the controller and then try stac9766_codec_probe()
343 * a warm reset followed by an optional cold reset for codec */ stac9766_codec_probe()
347 dev_err(codec->dev, "Failed to reset: AC97 link error\n"); stac9766_codec_probe()
/linux-4.1.27/drivers/ide/
H A Dide-eh.c163 * every 50ms during an atapi drive reset operation. If the drive has not yet
178 printk(KERN_INFO "%s: ATAPI reset complete\n", drive->name); atapi_reset_pollfunc()
187 printk(KERN_ERR "%s: ATAPI reset timed-out, status=0x%02x\n", atapi_reset_pollfunc()
207 printk(KERN_ERR "%s: reset: master: ", hwif->name); ide_reset_report_error()
219 * during an ide reset operation. If the drives have not yet responded,
247 printk(KERN_ERR "%s: reset timed-out, status=0x%02x\n", reset_pollfunc()
255 printk(KERN_INFO "%s: reset: success\n", hwif->name); reset_pollfunc()
325 * ATAPI devices have their own reset mechanism which allows them to be
326 * individually reset without clobbering other devices on the same interface.
329 * us know when the reset operation has finished, so we must poll for this.
347 /* We must not reset with running handlers */ do_reset1()
387 * First, reset any device state data we were maintaining
401 * to mask unwanted interrupts from the interface during the reset.
405 * recover from reset very quickly, saving us the first 50ms wait time.
423 * state when the disks are reset this way. At least, the Winbond
435 * ide_do_reset() is the entry point to the drive/interface reset code.
/linux-4.1.27/drivers/net/can/sja1000/
H A Dplx_pci.c58 /* Pointer to device-dependent reset function */
105 /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
111 /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/
166 /* Pointer to device-dependent reset function */
359 * Also check states of some registers in reset mode.
366 * Check registers after hardware reset (the Basic mode) plx_pci_check_sja1000()
379 * Check registers after reset in the PeliCAN mode. plx_pci_check_sja1000()
391 * PLX9030/50/52 software reset
392 * Also LRESET# asserts and brings to reset device on the Local Bus (if wired).
393 * For most cards it's enough for reset the SJA1000 chips.
409 * PLX9056 software reset
410 * Assert LRESET# and reset device(s) on the Local Bus (if wired).
417 /* issue a local bus reset */ plx9056_pci_reset_common()
440 /* Special reset function for Marathon card */ plx_pci_reset_marathon()
452 dev_err(&pdev->dev, "Failed to remap reset " plx_pci_reset_marathon()
455 /* reset the SJA1000 chip */ plx_pci_reset_marathon()
/linux-4.1.27/drivers/mfd/
H A Dsun6i-prcm.c86 .name = "sun6i-a31-apb0-clock-reset",
87 .of_compatible = "allwinner,sun6i-a31-clock-reset",
107 .name = "sun6i-a31-apb0-clock-reset",
108 .of_compatible = "allwinner,sun6i-a31-clock-reset",
/linux-4.1.27/drivers/scsi/
H A Dmvme147.c103 m147_pcc->scsi_interrupt = 0x10; /* Assert SCSI bus reset */ mvme147_detect()
105 m147_pcc->scsi_interrupt = 0x00; /* Negate SCSI bus reset */ mvme147_detect()
107 m147_pcc->scsi_interrupt = 0x40; /* Clear bus reset interrupt */ mvme147_detect()
126 /* FIXME perform bus-specific reset */ mvme147_bus_reset()
H A DNCR_D700.h18 #define BOARD_RESET 0x80 /* board level reset */
/linux-4.1.27/drivers/staging/iio/adc/
H A Dad7780.h20 * power down reset signal of the AD7780.
/linux-4.1.27/drivers/net/wireless/cw1200/
H A Dcw1200_sdio.c191 if (pdata->reset) { cw1200_sdio_off()
192 gpio_set_value(pdata->reset, 0); cw1200_sdio_off()
194 gpio_free(pdata->reset); cw1200_sdio_off()
208 if (pdata->reset) { cw1200_sdio_on()
209 gpio_request(pdata->reset, "cw1200_wlan_reset"); cw1200_sdio_on()
210 gpio_direction_output(pdata->reset, 0); cw1200_sdio_on()
216 if (pdata->reset || pdata->powerup) cw1200_sdio_on()
242 if (pdata->reset) { cw1200_sdio_on()
243 gpio_set_value(pdata->reset, 1); cw1200_sdio_on()
/linux-4.1.27/drivers/net/ethernet/chelsio/cxgb3/
H A Daq100x.c68 * Ignore the caller specified wait time; always wait for the reset to aq100x_reset()
74 CH_WARN(phy->adapter, "PHY%d: reset failed (0x%x).\n", aq100x_reset()
114 /* Read (and reset) the latching version of the status */ aq100x_intr_handler()
251 .reset = aq100x_reset,
278 * The PHY has been out of reset ever since the system powered up. So t3_aq100x_phy_prep()
279 * we do a hard reset over here. t3_aq100x_phy_prep()
297 CH_WARN(adapter, "PHY%d: reset failed (0x%x, 0x%x).\n", t3_aq100x_phy_prep()
307 CH_WARN(adapter, "PHY%d: reset timed out (0x%x).\n", t3_aq100x_phy_prep()
316 CH_WARN(adapter, "PHY%d: reset took %ums\n", phy_addr, wait); t3_aq100x_phy_prep()
/linux-4.1.27/drivers/firmware/efi/
H A Dreboot.c28 * If a quirk forced an EFI reset mode, always use that. efi_reboot()
/linux-4.1.27/drivers/infiniband/hw/mthca/
H A Dmthca_reset.c60 * save off the PCI header before reset and then restore it mthca_reset()
146 /* actually hit reset */ mthca_reset()
148 void __iomem *reset = ioremap(pci_resource_start(mdev->pdev, 0) + mthca_reset() local
151 if (!reset) { mthca_reset()
153 mthca_err(mdev, "Couldn't map HCA reset register, " mthca_reset()
158 writel(MTHCA_RESET_VALUE, reset); mthca_reset()
159 iounmap(reset); mthca_reset()
173 mthca_err(mdev, "Couldn't access HCA after reset, " mthca_reset()
185 mthca_err(mdev, "PCI device did not come back after reset, " mthca_reset()
/linux-4.1.27/drivers/tty/serial/
H A Difx6x60.h115 unsigned short reset; /* modem-reset gpio */ member in struct:ifx_spi_device::__anon10355
117 unsigned short reset_out; /* modem-in-reset gpio */
122 /* modem reset */
/linux-4.1.27/include/sound/
H A Dwm0010.h21 * the reset signal and the device.
/linux-4.1.27/arch/powerpc/boot/
H A Dvirtex405-head.S15 * or reset but does turn off the data cache. We cannot assume
/linux-4.1.27/arch/powerpc/kernel/
H A Dcrash.c35 * crash_kexec_secondary on their own (eg via a system reset).
139 * for someone to activate system reset. We also give up on the crash_kexec_prepare_cpus()
140 * second time through if system reset fail to work. crash_kexec_prepare_cpus()
146 * A system reset will cause all CPUs to take an 0x100 exception. crash_kexec_prepare_cpus()
155 printk(KERN_EMERG "Activate system reset (dumprestart) " crash_kexec_prepare_cpus()
159 * A system reset will force all CPUs to execute the crash_kexec_prepare_cpus()
160 * crash code again. We need to reset cpus_in_crash so we crash_kexec_prepare_cpus()
251 * can't reset your device in the second kernel. crash_kexec_wait_realmode()
326 * If we came in via system reset, wait a while for the secondary default_machine_crash_shutdown()
/linux-4.1.27/arch/blackfin/include/asm/
H A Dbfrom.h16 #define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */
17 #define SYSCTRL_CORERESET 0x00000004 /* perform core reset */
18 #define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */
40 * when doing a system reset, so the stack cannot be outside of the chip.
/linux-4.1.27/drivers/net/wimax/i2400m/
H A Ddriver.c3 * Generic probe/disconnect, reset and message passing
27 * reset [_op_reset()] and message from user [_op_msg_from_user()].
153 * Context to wait for a reset to finalize
162 * WiMAX stack operation: reset a device
170 * Do a warm reset on the device; if it fails, resort to a cold reset
171 * and return -ENODEV. On successful warm reset, we need to block
174 * The bus-driver implementation of reset takes care of falling back
175 * to cold reset if warm fails.
433 * device could have reset itself and failed to come up again (see
453 * When the device comes out of suspend, it might go into reset and
496 * pre-reset is called before a device is going on reset
506 d_printf(1, dev, "pre-reset shut down\n"); i2400m_pre_reset()
525 * Restore device state after a reset
527 * Do the work needed after a device reset to bring it up to the same
528 * state as it was before the reset.
538 d_printf(1, dev, "post-reset start\n"); i2400m_post_reset()
579 * If someone calls a reset when the device's firmware is down, in
583 * If there is a reset context, use it; this means someone is waiting
584 * for us to tell him when the reset operation is complete and the
594 * char *' ptr with a "reason" why the reset happened (for messages).
640 "reset the device, giving up\n"); __i2400m_dev_reset_handle()
652 * We come here because the reset during operational mode __i2400m_dev_reset_handle()
654 * reset. For the dev_reset_handle() to be able to handle __i2400m_dev_reset_handle()
655 * the reset event later properly, we restore boot_mode back __i2400m_dev_reset_handle()
656 * to the state before previous reset. ie: just like we are __i2400m_dev_reset_handle()
657 * issuing the bus reset for the first time __i2400m_dev_reset_handle()
684 * i2400m_dev_reset_handle - Handle a device's reset in a thread context
686 * Schedule a device reset handling out on a thread context, so it
692 * reinitializing the driver to handle the reset, calling into the
706 * The current implementation of error recovery is to trigger a bus reset.
722 * error recovery implementation is to trigger a bus reset to the device
727 * destroyed by the error recovery mechanism (currently a bus reset).
731 * Since bus reset is used as the error recovery mechanism and we don't
/linux-4.1.27/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_83xx_init.c272 /* Clear graceful reset bit */ qlcnic_83xx_idc_clear_registers()
325 * Return 0 if all functions have acknowledged the reset request.
386 netdev_info(adapter->netdev, "%s: soft reset complete.\n", __func__); qlcnic_83xx_idc_tx_soft_reset()
395 * Detach net interface, stop TX and cleanup resources before the HW reset.
534 * Returns: reset owner id or failure indication (-EIO)
863 /* Move to need reset state and prepare for reset */ qlcnic_83xx_idc_ready_state()
868 /* Check for soft reset request */ qlcnic_83xx_idc_ready_state()
936 "%s: Waiting for reset ACK\n", __func__); qlcnic_83xx_idc_need_reset_state()
1201 /* Check if reset recovery is disabled */ qlcnic_83xx_setup_idc_parameters()
1203 /* Propagate do not reset request to other functions */ qlcnic_83xx_setup_idc_parameters()
1242 /* Check if reset recovery is enabled */ qlcnic_83xx_idc_first_to_load_function_handler()
1615 "Device is being reset err code 0x00006700.\n"); qlcnic_83xx_check_heartbeat()
1678 p_dev->ahw->reset.seq_error++; qlcnic_83xx_poll_reg()
1681 __func__, p_dev->ahw->reset.seq_index); qlcnic_83xx_poll_reg()
1693 u16 *buff = (u16 *)p_dev->ahw->reset.buff; qlcnic_83xx_reset_template_checksum()
1694 int count = p_dev->ahw->reset.hdr->size / sizeof(u16); qlcnic_83xx_reset_template_checksum()
1716 if (ahw->reset.buff != NULL) { qlcnic_83xx_get_reset_instruction_template()
1720 kfree(ahw->reset.buff); qlcnic_83xx_get_reset_instruction_template()
1725 ahw->reset.seq_error = 0; qlcnic_83xx_get_reset_instruction_template()
1726 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL); qlcnic_83xx_get_reset_instruction_template()
1727 if (p_dev->ahw->reset.buff == NULL) qlcnic_83xx_get_reset_instruction_template()
1730 p_buff = p_dev->ahw->reset.buff; qlcnic_83xx_get_reset_instruction_template()
1739 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff; qlcnic_83xx_get_reset_instruction_template()
1740 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size; qlcnic_83xx_get_reset_instruction_template()
1741 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size; qlcnic_83xx_get_reset_instruction_template()
1742 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32); qlcnic_83xx_get_reset_instruction_template()
1753 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset; qlcnic_83xx_get_reset_instruction_template()
1754 ahw->reset.start_offset = ahw->reset.buff + qlcnic_83xx_get_reset_instruction_template()
1755 ahw->reset.hdr->start_offset; qlcnic_83xx_get_reset_instruction_template()
1756 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size; qlcnic_83xx_get_reset_instruction_template()
1782 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a]; qlcnic_83xx_rmw_crb_reg()
1953 index = p_dev->ahw->reset.array_index; qlcnic_83xx_poll_read_list()
1959 p_dev->ahw->reset.array[index++] = j; qlcnic_83xx_poll_read_list()
1962 p_dev->ahw->reset.array_index = 1; qlcnic_83xx_poll_read_list()
1970 p_dev->ahw->reset.seq_end = 1; qlcnic_83xx_seq_end()
1975 p_dev->ahw->reset.template_end = 1; qlcnic_83xx_template_end()
1976 if (p_dev->ahw->reset.seq_error == 0) qlcnic_83xx_template_end()
2005 p_dev->ahw->reset.seq_end = 0; qlcnic_83xx_exec_template_cmd()
2006 p_dev->ahw->reset.template_end = 0; qlcnic_83xx_exec_template_cmd()
2007 entries = p_dev->ahw->reset.hdr->entries; qlcnic_83xx_exec_template_cmd()
2008 index = p_dev->ahw->reset.seq_index; qlcnic_83xx_exec_template_cmd()
2010 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) { qlcnic_83xx_exec_template_cmd()
2051 p_dev->ahw->reset.seq_index = index; qlcnic_83xx_exec_template_cmd()
2056 p_dev->ahw->reset.seq_index = 0; qlcnic_83xx_stop_hw()
2058 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset); qlcnic_83xx_stop_hw()
2059 if (p_dev->ahw->reset.seq_end != 1) qlcnic_83xx_stop_hw()
2065 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset); qlcnic_83xx_start_hw()
2066 if (p_dev->ahw->reset.template_end != 1) qlcnic_83xx_start_hw()
2072 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset); qlcnic_83xx_init_hw()
2073 if (p_dev->ahw->reset.seq_end != 1) qlcnic_83xx_init_hw()
2243 /* No need to run POST in next reset sequence */ qlcnic_83xx_restart_hw()
2246 /* Again reset the adapter to load regular firmware */ qlcnic_83xx_restart_hw()
/linux-4.1.27/drivers/misc/mic/host/
H A Dmic_boot.c102 mdev->ops->reset(mdev); mic_reset()
152 * The state will either be MIC_OFFLINE if the reset succeeded mic_start()
153 * or MIC_RESET_FAILED if the firmware reset failed. mic_start()
190 * mic_stop - Prepare the MIC for reset and trigger reset.
192 * @force: force a MIC to reset even if it is already offline.
267 * mic_reset_trigger_work - Trigger MIC reset.
270 * This work is scheduled whenever the host wants to reset the MIC.
330 * shutdown and reset. mic_prepare_suspend()
336 /* Force reset the card if the shutdown completion timed out */ mic_prepare_suspend()
353 /* Force reset the card if the shutdown completion timed out */ mic_prepare_suspend()
/linux-4.1.27/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-socfpga.c24 #include <linux/reset.h>
93 dev_info(dev, "Could not get reset control!\n"); socfpga_dwmac_parse_data()
207 /* On socfpga platform exit, assert and hold reset to the socfpga_dwmac_exit()
208 * enet controller - the default state after a hard reset. socfpga_dwmac_exit()
224 /* Assert reset to the enet controller before changing the phy mode */ socfpga_dwmac_init()
233 /* Deassert reset for the phy configuration to be sampled by socfpga_dwmac_init()
245 * a DMA reset. A DMA reset will "time out" if executed socfpga_dwmac_init()
/linux-4.1.27/arch/xtensa/boot/boot-elf/
H A Dbootstrap.S28 .global reset
71 reset: label
/linux-4.1.27/drivers/usb/serial/
H A Dkobil_sct.h54 /* use a predefined reset sequence */
56 /* use a predefined sequence to reset the internal queues */

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