1NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
2
3Required properties:
4- compatible : For Tegra20, must contain "nvidia,tegra20-efuse".  For Tegra30,
5  must contain "nvidia,tegra30-efuse".  For Tegra114, must contain
6  "nvidia,tegra114-efuse".  For Tegra124, must contain "nvidia,tegra124-efuse".
7  Otherwise, must contain "nvidia,<chip>-efuse", plus one of the above, where
8  <chip> is tegra132.
9  Details:
10  nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
11	due to a hardware bug. Tegra20 also lacks certain information which is
12	available in later generations such as fab code, lot code, wafer id,..
13  nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
14	The differences between these SoCs are the size of the efuse array,
15	the location of the spare (OEM programmable) bits and the location of
16	the speedo data.
17- reg: Should contain 1 entry: the entry gives the physical address and length
18       of the fuse registers.
19- clocks: Must contain an entry for each entry in clock-names.
20  See ../clocks/clock-bindings.txt for details.
21- clock-names: Must include the following entries:
22  - fuse
23- resets: Must contain an entry for each entry in reset-names.
24  See ../reset/reset.txt for details.
25- reset-names: Must include the following entries:
26 - fuse
27
28Example:
29
30	fuse@7000f800 {
31		compatible = "nvidia,tegra20-efuse";
32		reg = <0x7000F800 0x400>,
33		      <0x70000000 0x400>;
34		clocks = <&tegra_car TEGRA20_CLK_FUSE>;
35		clock-names = "fuse";
36		resets = <&tegra_car 39>;
37		reset-names = "fuse";
38	};
39
40
41