1C6X PLL Clock Controllers
2-------------------------
3
4This is a first-cut support for the SoC clock controllers. This is still
5under development and will probably change as the common device tree
6clock support is added to the kernel.
7
8Required properties:
9
10- compatible: "ti,c64x+pll"
11    May also have SoC-specific value to support SoC-specific initialization
12    in the driver. One of:
13        "ti,c6455-pll"
14        "ti,c6457-pll"
15        "ti,c6472-pll"
16        "ti,c6474-pll"
17
18- reg: base address and size of register area
19- clock-frequency: input clock frequency in hz
20
21
22Optional properties:
23
24- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
25
26- ti,c64x+pll-reset-delay:  CPU cycles to delay after PLL reset
27
28- ti,c64x+pll-lock-delay:   CPU cycles to delay after PLL frequency change
29
30Example:
31
32	clock-controller@29a0000 {
33		compatible = "ti,c6472-pll", "ti,c64x+pll";
34		reg = <0x029a0000 0x200>;
35		clock-frequency = <25000000>;
36
37		ti,c64x+pll-bypass-delay = <200>;
38		ti,c64x+pll-reset-delay = <12000>;
39		ti,c64x+pll-lock-delay = <80000>;
40	};
41