Lines Matching refs:reset
165 ;; Start MII clock to make sure it is running when tranceiver is reset
365 move.d $r0, [$r1]; assert ATA bus-reset
393 ;; reset dma4 and wait for completion
395 moveq IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0
399 cmp.b IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0
403 ;; reset dma5 and wait for completion
405 moveq IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
409 cmp.b IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
471 move.b $r0,[R_DMA_CH6_CMD] ; reset (ser0 dma out)
472 move.b $r0,[R_DMA_CH7_CMD] ; reset (ser0 dma in)
473 1: move.b [R_DMA_CH6_CMD],$r0 ; wait for reset cycle to finish
478 1: move.b [R_DMA_CH7_CMD],$r0 ; wait for reset cycle to finish
485 moveq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0
486 move.b $r0,[R_DMA_CH8_CMD] ; reset (ser1 dma out)
487 move.b $r0,[R_DMA_CH9_CMD] ; reset (ser1 dma in)
488 1: move.b [R_DMA_CH8_CMD],$r0 ; wait for reset cycle to finish
490 cmpq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0
493 1: move.b [R_DMA_CH9_CMD],$r0 ; wait for reset cycle to finish
495 cmpq IO_STATE (R_DMA_CH9_CMD, cmd, reset),$r0