Searched refs:r4 (Results 1 - 200 of 566) sorted by relevance

123

/linux-4.1.27/sound/oss/
H A Dvidc_fill.S23 ldrb r4, [r0], #1
24 eor r4, r4, #0x80
25 and r4, ip, r4, lsl #8
26 orr r4, r4, r4, lsl #16
27 str r4, [r2], #4
36 ldr r4, [r0], #2
37 and r5, r4, ip
38 and r4, ip, r4, lsl #8
39 orr r4, r4, r5, lsl #16
40 orr r4, r4, r4, lsr #8
41 str r4, [r2], #4
50 ldrb r4, [r0], #1
51 and r4, ip, r4, lsl #8
52 orr r4, r4, r4, lsl #16
53 str r4, [r2], #4
62 ldr r4, [r0], #2
63 and r5, r4, ip
64 and r4, ip, r4, lsl #8
65 orr r4, r4, r5, lsl #16
66 orr r4, r4, r4, lsr #8
67 str r4, [r2], #4
78 and r4, r5, ip
79 orr r4, r4, r4, lsl #16
80 str r4, [r2], #4
83 andlt r4, r5, ip, lsl #16
84 orrlt r4, r4, r4, lsr #16
85 strlt r4, [r2], #4
95 ldr r4, [r0], #4
96 str r4, [r2], #4
98 ldrlt r4, [r0], #4
99 strlt r4, [r2], #4
107 2: mov r4, #0
110 stmltia r2!, {r0, r1, r4, r5}
131 * r4 = corrupted
137 stmfd sp!, {r4 - r8, lr}
139 ldmia r8, {r0, r1, r2, r3, r4, r5}
141 adreq r4, vidc_fill_noaudio
154 mov pc, r4 @ Call fill routine (uses r4, ip)
168 ldmdb r8, {r3, r4, r5}
172 streq r4, [ip, #IOMD_SD0CURB]
180 strne r4, [ip, #IOMD_SD0CURB]
187 ldmfd sp!, {r4 - r8, lr}
201 .long 0 @ r4
215 .long vidc_fill_noaudio @ r4
/linux-4.1.27/arch/powerpc/platforms/powermac/
H A Dsleep.S70 mfmsr r4
71 stw r4,SL_MSR(r1)
72 mfsdr1 r4
73 stw r4,SL_SDR1(r1)
76 1: mftbu r4
77 stw r4,SL_TB(r1)
81 cmpw r3,r4
85 mfsprg r4,0
86 stw r4,SL_SPRG0(r1)
87 mfsprg r4,1
88 stw r4,SL_SPRG0+4(r1)
89 mfsprg r4,2
90 stw r4,SL_SPRG0+8(r1)
91 mfsprg r4,3
92 stw r4,SL_SPRG0+12(r1)
95 mfdbatu r4,0
96 stw r4,SL_DBAT0(r1)
97 mfdbatl r4,0
98 stw r4,SL_DBAT0+4(r1)
99 mfdbatu r4,1
100 stw r4,SL_DBAT1(r1)
101 mfdbatl r4,1
102 stw r4,SL_DBAT1+4(r1)
103 mfdbatu r4,2
104 stw r4,SL_DBAT2(r1)
105 mfdbatl r4,2
106 stw r4,SL_DBAT2+4(r1)
107 mfdbatu r4,3
108 stw r4,SL_DBAT3(r1)
109 mfdbatl r4,3
110 stw r4,SL_DBAT3+4(r1)
111 mfibatu r4,0
112 stw r4,SL_IBAT0(r1)
113 mfibatl r4,0
114 stw r4,SL_IBAT0+4(r1)
115 mfibatu r4,1
116 stw r4,SL_IBAT1(r1)
117 mfibatl r4,1
118 stw r4,SL_IBAT1+4(r1)
119 mfibatu r4,2
120 stw r4,SL_IBAT2(r1)
121 mfibatl r4,2
122 stw r4,SL_IBAT2+4(r1)
123 mfibatu r4,3
124 stw r4,SL_IBAT3(r1)
125 mfibatl r4,3
126 stw r4,SL_IBAT3+4(r1)
145 lis r4,KERNELBASE@h
150 stw r5,0(r4)
151 stw r6,4(r4)
156 stw r3,0x80(r4)
157 stw r5,0x84(r4)
216 * r4 has the physical address of SL_PC(sp) (unused)
260 li r4,0
261 3: mtsrin r3,r4
263 addis r4,r4,0x1000 /* address of next segment */
283 lwz r4,SL_SDR1(r1)
284 mtsdr1 r4
285 lwz r4,SL_SPRG0(r1)
286 mtsprg 0,r4
287 lwz r4,SL_SPRG0+4(r1)
288 mtsprg 1,r4
289 lwz r4,SL_SPRG0+8(r1)
290 mtsprg 2,r4
291 lwz r4,SL_SPRG0+12(r1)
292 mtsprg 3,r4
294 lwz r4,SL_DBAT0(r1)
295 mtdbatu 0,r4
296 lwz r4,SL_DBAT0+4(r1)
297 mtdbatl 0,r4
298 lwz r4,SL_DBAT1(r1)
299 mtdbatu 1,r4
300 lwz r4,SL_DBAT1+4(r1)
301 mtdbatl 1,r4
302 lwz r4,SL_DBAT2(r1)
303 mtdbatu 2,r4
304 lwz r4,SL_DBAT2+4(r1)
305 mtdbatl 2,r4
306 lwz r4,SL_DBAT3(r1)
307 mtdbatu 3,r4
308 lwz r4,SL_DBAT3+4(r1)
309 mtdbatl 3,r4
310 lwz r4,SL_IBAT0(r1)
311 mtibatu 0,r4
312 lwz r4,SL_IBAT0+4(r1)
313 mtibatl 0,r4
314 lwz r4,SL_IBAT1(r1)
315 mtibatu 1,r4
316 lwz r4,SL_IBAT1+4(r1)
317 mtibatl 1,r4
318 lwz r4,SL_IBAT2(r1)
319 mtibatu 2,r4
320 lwz r4,SL_IBAT2+4(r1)
321 mtibatl 2,r4
322 lwz r4,SL_IBAT3(r1)
323 mtibatu 3,r4
324 lwz r4,SL_IBAT3+4(r1)
325 mtibatl 3,r4
328 li r4,0
329 mtspr SPRN_DBAT4U,r4
330 mtspr SPRN_DBAT4L,r4
331 mtspr SPRN_DBAT5U,r4
332 mtspr SPRN_DBAT5L,r4
333 mtspr SPRN_DBAT6U,r4
334 mtspr SPRN_DBAT6L,r4
335 mtspr SPRN_DBAT7U,r4
336 mtspr SPRN_DBAT7L,r4
337 mtspr SPRN_IBAT4U,r4
338 mtspr SPRN_IBAT4L,r4
339 mtspr SPRN_IBAT5U,r4
340 mtspr SPRN_IBAT5L,r4
341 mtspr SPRN_IBAT6U,r4
342 mtspr SPRN_IBAT6L,r4
343 mtspr SPRN_IBAT7U,r4
344 mtspr SPRN_IBAT7L,r4
348 lis r4,0x1000
349 1: addic. r4,r4,-0x1000
350 tlbie r4
365 lwz r4,SL_TB+4(r1)
367 mttbl r4
380 mflr r4
381 tovirt(r4,r4)
382 mtsrr0 r4
H A Dcache.S61 rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */
63 mtspr SPRN_HID0,r4 /* Disable DPM */
73 lis r4,0xfff0
79 li r4,0
80 1: li r4,0x4000
81 mtctr r4
82 1: lwz r0,0(r4)
83 addi r4,r4,32
102 /* Get the current enable bit of the L2CR into r4 */
121 lis r4,2
122 mtctr r4
123 lis r4,0xfff0
124 1: lwz r0,0(r4)
125 addi r4,r4,32
129 lis r4,2
130 mtctr r4
131 lis r4,0xfff0
132 1: dcbf 0,r4
133 addi r4,r4,32
154 oris r4,r5,L2CR_L2I@h
155 mtspr SPRN_L2CR,r4
165 xoris r4,r4,L2CR_L2I@h
167 mtspr SPRN_L2CR,r4
212 lis r4,0
213 dcbf 0,r4
214 dcbf 0,r4
215 dcbf 0,r4
216 dcbf 0,r4
217 dcbf 0,r4
218 dcbf 0,r4
219 dcbf 0,r4
220 dcbf 0,r4
229 lis r4,0x0002
230 mtctr r4
231 li r4,0
233 lwz r0,0(r4)
234 addi r4,r4,32 /* Go to start of next cache line */
239 lis r4,0x0002
240 mtctr r4
241 li r4,0
244 dcbf 0,r4
245 addi r4,r4,32 /* Go to start of next cache line */
251 li r4,0xfe /* start with only way 0 unlocked */
254 rlwimi r6,r4,0,24,31
261 rlwinm r4,r4,1,24,30 /* move on to the next way */
262 ori r4,r4,1
263 cmpwi r4,0xff /* all done? */
266 li r4,0
267 rlwimi r6,r4,0,24,31
312 oris r4,r3,L2CR_L2I@h
313 mtspr SPRN_L2CR,r4
316 1: mfspr r4,SPRN_L2CR
317 andis. r0,r4,L2CR_L2I@h
342 ori r4,r3,L3CR_L3I
343 mtspr SPRN_L3CR,r4
344 1: mfspr r4,SPRN_L3CR
345 andi. r0,r4,L3CR_L3I
/linux-4.1.27/arch/powerpc/kernel/
H A Dswsusp_32.S57 mfmsr r4
58 stw r4,SL_MSR(r11)
59 mfsdr1 r4
60 stw r4,SL_SDR1(r11)
63 1: mftbu r4
64 stw r4,SL_TB(r11)
68 cmpw r3,r4
72 mfsprg r4,0
73 stw r4,SL_SPRG0(r11)
74 mfsprg r4,1
75 stw r4,SL_SPRG0+4(r11)
76 mfsprg r4,2
77 stw r4,SL_SPRG0+8(r11)
78 mfsprg r4,3
79 stw r4,SL_SPRG0+12(r11)
82 mfdbatu r4,0
83 stw r4,SL_DBAT0(r11)
84 mfdbatl r4,0
85 stw r4,SL_DBAT0+4(r11)
86 mfdbatu r4,1
87 stw r4,SL_DBAT1(r11)
88 mfdbatl r4,1
89 stw r4,SL_DBAT1+4(r11)
90 mfdbatu r4,2
91 stw r4,SL_DBAT2(r11)
92 mfdbatl r4,2
93 stw r4,SL_DBAT2+4(r11)
94 mfdbatu r4,3
95 stw r4,SL_DBAT3(r11)
96 mfdbatl r4,3
97 stw r4,SL_DBAT3+4(r11)
98 mfibatu r4,0
99 stw r4,SL_IBAT0(r11)
100 mfibatl r4,0
101 stw r4,SL_IBAT0+4(r11)
102 mfibatu r4,1
103 stw r4,SL_IBAT1(r11)
104 mfibatl r4,1
105 stw r4,SL_IBAT1+4(r11)
106 mfibatu r4,2
107 stw r4,SL_IBAT2(r11)
108 mfibatl r4,2
109 stw r4,SL_IBAT2+4(r11)
110 mfibatu r4,3
111 stw r4,SL_IBAT3(r11)
112 mfibatl r4,3
113 stw r4,SL_IBAT3+4(r11)
236 lwz r4,SL_SDR1(r11)
237 mtsdr1 r4
238 lwz r4,SL_SPRG0(r11)
239 mtsprg 0,r4
240 lwz r4,SL_SPRG0+4(r11)
241 mtsprg 1,r4
242 lwz r4,SL_SPRG0+8(r11)
243 mtsprg 2,r4
244 lwz r4,SL_SPRG0+12(r11)
245 mtsprg 3,r4
248 lwz r4,SL_DBAT0(r11)
249 mtdbatu 0,r4
250 lwz r4,SL_DBAT0+4(r11)
251 mtdbatl 0,r4
252 lwz r4,SL_DBAT1(r11)
253 mtdbatu 1,r4
254 lwz r4,SL_DBAT1+4(r11)
255 mtdbatl 1,r4
256 lwz r4,SL_DBAT2(r11)
257 mtdbatu 2,r4
258 lwz r4,SL_DBAT2+4(r11)
259 mtdbatl 2,r4
260 lwz r4,SL_DBAT3(r11)
261 mtdbatu 3,r4
262 lwz r4,SL_DBAT3+4(r11)
263 mtdbatl 3,r4
264 lwz r4,SL_IBAT0(r11)
265 mtibatu 0,r4
266 lwz r4,SL_IBAT0+4(r11)
267 mtibatl 0,r4
268 lwz r4,SL_IBAT1(r11)
269 mtibatu 1,r4
270 lwz r4,SL_IBAT1+4(r11)
271 mtibatl 1,r4
272 lwz r4,SL_IBAT2(r11)
273 mtibatu 2,r4
274 lwz r4,SL_IBAT2+4(r11)
275 mtibatl 2,r4
276 lwz r4,SL_IBAT3(r11)
277 mtibatu 3,r4
278 lwz r4,SL_IBAT3+4(r11)
279 mtibatl 3,r4
283 li r4,0
284 mtspr SPRN_DBAT4U,r4
285 mtspr SPRN_DBAT4L,r4
286 mtspr SPRN_DBAT5U,r4
287 mtspr SPRN_DBAT5L,r4
288 mtspr SPRN_DBAT6U,r4
289 mtspr SPRN_DBAT6L,r4
290 mtspr SPRN_DBAT7U,r4
291 mtspr SPRN_DBAT7L,r4
292 mtspr SPRN_IBAT4U,r4
293 mtspr SPRN_IBAT4L,r4
294 mtspr SPRN_IBAT5U,r4
295 mtspr SPRN_IBAT5L,r4
296 mtspr SPRN_IBAT6U,r4
297 mtspr SPRN_IBAT6L,r4
298 mtspr SPRN_IBAT7U,r4
299 mtspr SPRN_IBAT7L,r4
303 lis r4,0x1000
304 1: addic. r4,r4,-0x1000
305 tlbie r4
318 lwz r4,SL_TB+4(r11)
320 mttbl r4
344 mflr r4
345 mtsrr0 r4
H A Dswsusp_booke.S62 mfmsr r4
63 stw r4,SL_MSR(r11)
64 mfspr r4,SPRN_TCR
65 stw r4,SL_TCR(r11)
68 1: mfspr r4,SPRN_TBRU
69 stw r4,SL_TBU(r11)
73 cmpw r3,r4
77 mfspr r4,SPRN_SPRG0
78 stw r4,SL_SPRG0(r11)
79 mfspr r4,SPRN_SPRG1
80 stw r4,SL_SPRG1(r11)
81 mfspr r4,SPRN_SPRG2
82 stw r4,SL_SPRG2(r11)
83 mfspr r4,SPRN_SPRG3
84 stw r4,SL_SPRG3(r11)
85 mfspr r4,SPRN_SPRG4
86 stw r4,SL_SPRG4(r11)
87 mfspr r4,SPRN_SPRG5
88 stw r4,SL_SPRG5(r11)
89 mfspr r4,SPRN_SPRG6
90 stw r4,SL_SPRG6(r11)
91 mfspr r4,SPRN_SPRG7
92 stw r4,SL_SPRG7(r11)
152 lwz r4,SL_SPRG0(r11)
153 mtspr SPRN_SPRG0,r4
154 lwz r4,SL_SPRG1(r11)
155 mtspr SPRN_SPRG1,r4
156 lwz r4,SL_SPRG2(r11)
157 mtspr SPRN_SPRG2,r4
158 lwz r4,SL_SPRG3(r11)
159 mtspr SPRN_SPRG3,r4
160 lwz r4,SL_SPRG4(r11)
161 mtspr SPRN_SPRG4,r4
162 lwz r4,SL_SPRG5(r11)
163 mtspr SPRN_SPRG5,r4
164 lwz r4,SL_SPRG6(r11)
165 mtspr SPRN_SPRG6,r4
166 lwz r4,SL_SPRG7(r11)
167 mtspr SPRN_SPRG7,r4
177 lwz r4,SL_TBL(r11)
179 mtspr SPRN_TBWL,r4
182 lwz r4,SL_TCR(r11)
183 mtspr SPRN_TCR,r4
184 lis r4, (TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS)@h
185 mtspr SPRN_TSR,r4
H A Didle_e500.S25 lwz r4,TI_LOCAL_FLAGS(r3) /* set napping bit */
26 ori r4,r4,_TLF_NAPPING /* so when we take an exception */
27 stw r4,TI_LOCAL_FLAGS(r3) /* it will return to our caller */
48 lis r4,powersave_nap@ha
49 lwz r4,powersave_nap@l(r4)
50 cmpwi 0,r4,0
67 andi. r4,r7,L2CSR0_L2FL@l
72 mfspr r4,SPRN_HID0
73 rlwinm r4,r4,0,~(HID0_DOZE|HID0_NAP|HID0_SLEEP)
74 or r4,r4,r3
76 mtspr SPRN_HID0,r4
H A Didle_6xx.S34 mfspr r4,SPRN_HID0
35 rlwinm r4,r4,0,10,8 /* Clear NAP */
36 mtspr SPRN_HID0, r4
44 mfspr r4,SPRN_MSSCR0
46 stw r4,nap_save_msscr0@l(r6)
49 mfspr r4,SPRN_HID1
51 stw r4,nap_save_hid1@l(r6)
71 lis r4,cur_cpu_spec@ha
72 lwz r4,cur_cpu_spec@l(r4)
73 lwz r4,CPU_SPEC_FEATURES(r4)
74 andi. r0,r4,CPU_FTR_CAN_NAP
77 lis r4,powersave_nap@ha
78 lwz r4,powersave_nap@l(r4)
79 cmpwi 0,r4,0
97 mfspr r4,SPRN_MSSCR0
98 rlwinm r4,r4,0,0,29
100 mtspr SPRN_MSSCR0,r4
103 lis r4,KERNELBASE@h
104 dcbf 0,r4
105 dcbf 0,r4
106 dcbf 0,r4
107 dcbf 0,r4
112 lis r4,powersave_lowspeed@ha
113 lwz r4,powersave_lowspeed@l(r4)
114 cmpwi 0,r4,0
116 mfspr r4,SPRN_HID1
117 oris r4,r4,0x0001
118 mtspr SPRN_HID1,r4
123 mfspr r4,SPRN_HID0
128 andc r4,r4,r5
129 or r4,r4,r3
131 oris r4,r4,HID0_DPM@h /* that should be done once for all */
133 mtspr SPRN_HID0,r4
H A Dmisc_32.S67 addi r11,r4,THREAD_INFO_GAP
68 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
69 mr r1,r4
86 mr r10,r4
87 mulhwu r4,r4,r5
92 addze r4,r4
101 adde r4,r4,r8
103 2: addc r4,r4,r9
114 lis r4,1b@ha
115 addi r4,r4,1b@l
116 subf r5,r4,r5
137 lis r4,1b@ha
138 addi r4,r4,1b@l
139 subf r0,r4,r0
155 * r4 = ptr to CPU spec (relocated)
158 addis r4,r3,cur_cpu_spec@ha
159 addi r4,r4,cur_cpu_spec@l
160 lwz r4,0(r4)
161 add r4,r4,r3
162 lwz r5,CPU_SPEC_SETUP(r4)
193 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
195 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
196 or r4,r4,r5
197 mtspr SPRN_HID1,r4
204 stw r4,nap_save_hid1@l(r6)
228 mfspr r4,SPRN_HID1
229 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
231 mtspr SPRN_HID1,r4
248 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
285 stb r3,0(r4)
308 lis r4, KERNELBASE@h
309 1: iccci 0, r4
310 addi r4, r4, 16
355 subf r4,r3,r4
356 add r4,r4,r5
357 srwi. r4,r4,L1_CACHE_SHIFT
359 mtctr r4
366 mtctr r4
389 subf r4,r3,r4
390 add r4,r4,r5
391 srwi. r4,r4,L1_CACHE_SHIFT
393 mtctr r4
410 subf r4,r3,r4
411 add r4,r4,r5
412 srwi. r4,r4,L1_CACHE_SHIFT
414 mtctr r4
432 subf r4,r3,r4
433 add r4,r4,r5
434 srwi. r4,r4,L1_CACHE_SHIFT
436 mtctr r4
458 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
459 mtctr r4
477 mtctr r4
504 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
505 mtctr r4
511 mtctr r4
530 slw r0,r0,r4
544 lwz r6,4(r4); \
545 lwz r7,8(r4); \
546 lwz r8,12(r4); \
547 lwzu r9,16(r4); \
555 addi r4,r4,-4
563 11: dcbt r11,r4
567 dcbt r5,r4
575 dcbt r11,r4
603 10: lwarx r5,0,r4
605 PPC405_ERR77(0,r4)
606 stwcx. r5,0,r4
610 10: lwarx r5,0,r4
612 PPC405_ERR77(0,r4)
613 stwcx. r5,0,r4
633 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
638 or r4,r4,r6 # LSW |= t1
641 or r4,r4,r7 # LSW |= t2
648 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
649 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
651 slw r4,r4,r5 # LSW = LSW << count
657 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
661 or r4,r4,r6 # LSW |= t1
663 or r4,r4,r7 # LSW |= t2
674 cmplw r4,r6
688 cmplw r4,r6
696 rotlwi r9,r4,8
698 rlwimi r9,r4,24,0,7
700 rlwimi r9,r4,24,16,23
703 mr r4,r10
707 srawi r4,r3,31
708 xor r3,r3,r4
709 sub r3,r3,r4
736 /* r4 = reboot_code_buffer */
742 mr r30, r4
750 mr r4, r30
758 mr r30, r4
793 mfmsr r4
794 andi. r4,r4,MSR_IS@l
808 li r4,0 /* Start at TLB entry 0 */
810 1: cmpw r23,r4 /* Is this our entry? */
812 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
814 addi r4,r4,1 /* Increment */
815 cmpwi r4,64 /* Are we done? */
829 tlbre r4, r23, PPC44x_TLB_XLAT
833 mr r25, r4
861 tlbwe r4, r24, PPC44x_TLB_XLAT
896 mr r4, r3 /* RPN = EPN */
901 tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */
944 mfmsr r4 /* Get MSR */
945 andi. r4, r4, MSR_IS@l /* TS=1? */
961 * Invalidates all the tlb entries by writing to 256 RPNs(r4)
968 addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */
977 tlbwe r4, r3, 0
984 addis r4, r4, 0x100 /* Increment the EPN */
985 cmpwi r4, 0
1022 li r4, 0 /* TLB Word 0 */
1035 mr r4, r5 /* EPN = RPN */
1036 ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M)
1037 insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */
1039 tlbwe r4, r3, 0 /* Write out the entries */
1068 1: mflr r4
1069 addi r4, r4, (2f-1b) /* virtual address of 2f */
1075 and r6, r4, r11 /* offset within the current page */
1106 mr r4, r30
1121 addi r8, r4, 1f - relocate_new_kernel
1133 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
1197 mr r4, r5 /* load physical address of chunk called */
H A Dvector.S23 li r4,1
24 stw r4,THREAD_USED_VR(r3)
30 REST_32VRS(0,r4,r10)
54 li r4,VRSTATE_VSCR
55 lvx v0,r4,r3
57 REST_32VRS(0,r4,r3)
65 SAVE_32VRS(0, r4, r3)
67 li r4, VRSTATE_VSCR
68 stvx v0, r4, r3
98 PPC_LL r4,ADDROFF(last_task_used_altivec)(r3)
99 PPC_LCMPI 0,r4,0
103 toreal(r4)
104 addi r4,r4,THREAD
105 addi r6,r4,THREAD_VRSTATE
111 PPC_LL r5,PT_REGS(r4)
113 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
115 andc r4,r4,r10
116 PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
125 mfspr r4,SPRN_VRSAVE
126 cmpwi 0,r4,0
128 li r4,-1
129 mtspr SPRN_VRSAVE,r4
136 ld r4,PACACURRENT(r13)
137 addi r5,r4,THREAD /* Get THREAD */
142 li r4,1
144 stw r4,THREAD_USED_VR(r5)
147 REST_32VRS(0,r4,r6)
150 subi r4,r5,THREAD /* Back to 'current' */
151 fromreal(r4)
152 PPC_STL r4,ADDROFF(last_task_used_altivec)(r3)
159 andis. r4,r3,MSR_VEC@h
188 SAVE_32VRS(0,r4,r7)
190 li r4,VRSTATE_VSCR
191 stvx v0,r4,r7
193 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
203 andc r4,r4,r3 /* disable FP for previous task */
204 PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
208 LOAD_REG_ADDRBASE(r4,last_task_used_altivec)
209 PPC_STL r5,ADDROFF(last_task_used_altivec)(r4)
235 ld r4,0(r3)
236 cmpdi 0,r4,0
239 addi r4,r4,THREAD
240 ld r5,PT_REGS(r4)
241 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
243 andc r6,r4,r6
247 ld r4,PACACURRENT(r13)
248 addi r4,r4,THREAD /* Get THREAD */
250 stw r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */
256 ld r4,PACACURRENT(r13)
257 std r4,0(r3)
279 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
281 andc r4,r4,r3 /* disable VSX for previous task */
282 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
286 ld r4,last_task_used_vsx@got(r2)
287 std r5,0(r4)
368 1: lfsx fr0,r4,r6
385 1: lfsx fr0,r4,r6
403 1: lfsx fr0,r4,r7
423 1: lfsx fr0,r4,r7
435 * r3 -> destination, r4 -> source.
444 1: lfsx fr0,r4,r6
455 * r3 -> destination, r4 -> source.
469 1: lfsx fr0,r4,r6
H A Dfpu.S147 PPC_LL r4,ADDROFF(last_task_used_math)(r3)
148 PPC_LCMPI 0,r4,0
150 toreal(r4)
151 addi r4,r4,THREAD /* want last_task_used_math->thread */
152 addi r10,r4,THREAD_FPSTATE
156 PPC_LL r5,PT_REGS(r4)
158 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
160 andc r4,r4,r10 /* disable FP for previous task */
161 PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
167 lwz r4,THREAD_FPEXC_MODE(r5)
169 or r9,r9,r4
171 ld r4,PACACURRENT(r13)
172 addi r5,r4,THREAD /* Get THREAD */
173 lwz r4,THREAD_FPEXC_MODE(r5)
175 or r12,r12,r4
183 subi r4,r5,THREAD
184 fromreal(r4)
185 PPC_STL r4,ADDROFF(last_task_used_math)(r3)
223 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
230 andc r4,r4,r3 /* disable FP for previous task */
231 PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
235 LOAD_REG_ADDRBASE(r4,last_task_used_math)
236 PPC_STL r5,ADDROFF(last_task_used_math)(r4)
247 stfd 0,0(r4)
252 stfs 0,0(r4)
H A Dl2cr_6xx.S116 rlwinm r4,r7,0,17,15
117 rlwinm r4,r4,0,28,26 /* Turn off DR bit */
119 mtmsr r4
128 rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */
130 mtspr SPRN_HID0,r4 /* Disable DPM */
133 /* Get the current enable bit of the L2CR into r4 */
134 mfspr r4,SPRN_L2CR
142 rlwinm. r4,r4,0,0,0
165 mfspr r4,SPRN_MSSCR0
166 rlwinm r4,r4,0,0,29
168 mtspr SPRN_MSSCR0,r4
171 lis r4,KERNELBASE@h
172 dcbf 0,r4
173 dcbf 0,r4
174 dcbf 0,r4
175 dcbf 0,r4
180 lis r4,0x0002
181 mtctr r4
182 li r4,0
184 lwzx r0,r0,r4
185 addi r4,r4,32 /* Go to start of next cache line */
190 lis r4,0x0002
191 mtctr r4
192 li r4,0
195 dcbf 0,r4
196 addi r4,r4,32 /* Go to start of next cache line */
229 andis. r4,r3,0x0020
236 rlwinm. r4,r3,0,31,31
300 rlwinm r4,r7,0,17,15
301 rlwinm r4,r4,0,28,26 /* Turn off DR bit */
303 mtmsr r4
310 /* Get the current enable bit of the L3CR into r4 */
311 mfspr r4,SPRN_L3CR
319 rlwinm. r4,r4,0,0,0
327 lis r4,0x0008
328 mtctr r4
329 li r4,0
331 lwzx r0,r0,r4
332 dcbf 0,r4
333 addi r4,r4,32 /* Go to start of next cache line */
363 andi. r4,r3,0x0400
H A Dcpu_setup_44x.S23 mflr r4
27 mtlr r4
30 mflr r4
33 mtlr r4
39 mflr r4
42 mtlr r4
H A Dhead_fsl_booke.S52 * r4 - Starting address of the init RAM disk
70 mr r31,r4
82 mr r25,r4
104 addis r4,r8,(kernstart_addr - 0b)@ha
105 addi r4,r4,(kernstart_addr - 0b)@l
106 lwz r5,4(r4)
123 lis r4,KERNELBASE@h
124 ori r4,r4,KERNELBASE@l
126 rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */
128 add r3,r4,r3 /* Required Virtual Address */
152 * r4 = Current MSR[IS]
185 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
186 mtspr SPRN_IVPR,r4
235 addi r4,r2,THREAD /* init task's THREAD */
236 mtspr SPRN_SPRG_THREAD,r4
251 mr r4,r31
276 mr r4,r31
285 lis r4, KERNELBASE@h
286 ori r4, r4, KERNELBASE@l
287 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
291 lis r4,start_kernel@h
292 ori r4,r4,start_kernel@l
295 mtspr SPRN_SRR0,r4
381 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
867 lwz r4,last_task_used_spe@l(r3)
868 cmpi 0,r4,0
870 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
871 SAVE_32EVRS(0,r10,r4,THREAD_EVR0)
875 evstddx evr10, r4, r5 /* save off accumulator */
876 lwz r5,PT_REGS(r4)
877 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
879 andc r4,r4,r10 /* disable SPE for previous task */
880 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
886 li r4,1
888 stw r4,THREAD_USED_SPE(r5)
893 subi r4,r5,THREAD
894 stw r4,last_task_used_spe@l(r3)
909 mr r4,r2 /* current */
923 * into r3(higher 32bit) and r4(lower 32bit)
941 andc r4,r12,r10 /* r4 = page base */
942 or r4,r4,r11 /* r4 = devtree phys addr */
1027 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
1030 li r4,THREAD_ACC
1031 evstddx evr6, r4, r3 /* save off accumulator */
1033 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1035 andc r4,r4,r3 /* disable SPE for previous task */
1036 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1040 lis r4,last_task_used_spe@ha
1041 stw r5,last_task_used_spe@l(r4)
1072 stw r4, 0x4(r5)
1085 li r4,32
1089 slw r5,r4,r5 /* r5 = cache block size */
1103 lis r4,KERNELBASE@h
1106 1: lwz r3,0(r4) /* Load... */
1107 add r4,r4,r5
1111 lis r4,KERNELBASE@h
1114 1: dcbf 0,r4 /* ...and flush. */
1115 add r4,r4,r5
1130 mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */
1132 rlwimi r4, r5, 0, 3
1136 mtspr SPRN_L1CSR0, r4
1139 1: mfspr r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */
1140 andi. r4, r4, 2
1143 mfspr r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */
1145 rlwimi r4, r5, 0, 3
1147 mtspr SPRN_L1CSR1, r4
1169 LOAD_REG_ADDR_PIC(r4, memstart_addr)
1170 lwz r4,0(r4)
1173 subf r4,r5,r4 /* memstart_addr - phys kernel start */
1184 mr r4,r24 /* Why? */
1198 addi r4,r2,THREAD /* address of our thread_struct */
1199 mtspr SPRN_SPRG_THREAD,r4
1202 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1203 mtspr SPRN_MAS4,r4
1206 lis r4,MSR_KERNEL@h
1207 ori r4,r4,MSR_KERNEL@l
1211 mtspr SPRN_SRR1,r4
1233 mfspr r4,SPRN_PID
1234 rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */
1235 mtspr SPRN_MAS6,r4
1236 1: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */
1238 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1239 mtspr SPRN_MAS0,r4
1241 mfspr r4,SPRN_MAS1
1242 andis. r4,r4,MAS1_VALID@h
1247 0: mflr r4
1248 tlbsx 0,r4
1250 mfspr r4,SPRN_MAS1
1251 ori r4,r4,MAS1_TS /* Set the TS = 1 */
1252 mtspr SPRN_MAS1,r4
1254 mfspr r4,SPRN_MAS0
1255 rlwinm r4,r4,0,~MAS0_ESEL_MASK
1256 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1257 mtspr SPRN_MAS0,r4
1262 mfmsr r4
1263 ori r4,r4,MSR_IS | MSR_DS
1265 mtspr SPRN_SRR1,r4
1273 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1274 * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1287 * on the offset passed by r4.
1289 add r9,r9,r4
1290 add r5,r5,r4
1291 add r0,r0,r4
1313 cmpwi r4,0
H A Dcpu_setup_6xx.S197 lwz r6,CPU_SPEC_FEATURES(r4)
200 stw r6,CPU_SPEC_FEATURES(r4)
228 lwz r6,CPU_SPEC_FEATURES(r4)
233 stw r6,CPU_SPEC_FEATURES(r4)
353 mfspr r4,SPRN_MSSCR0
354 stw r4,CS_MSSCR0(r5)
355 mfspr r4,SPRN_MSSSR0
356 stw r4,CS_MSSSR0(r5)
359 mfspr r4,SPRN_HID1
360 stw r4,CS_HID1(r5)
361 mfspr r4,SPRN_ICTRL
362 stw r4,CS_ICTRL(r5)
363 mfspr r4,SPRN_LDSTCR
364 stw r4,CS_LDSTCR(r5)
365 mfspr r4,SPRN_LDSTDB
366 stw r4,CS_LDSTDB(r5)
370 mfspr r4,SPRN_HID1
371 stw r4,CS_HID1(r5)
377 mfspr r4,SPRN_HID2
378 stw r4,CS_HID2(r5)
424 lwz r4,CS_MSSCR0(r5)
426 mtspr SPRN_MSSCR0,r4
429 lwz r4,CS_MSSSR0(r5)
431 mtspr SPRN_MSSSR0,r4
436 li r4,0
437 mtspr SPRN_L2CR2,r4
440 lwz r4,CS_HID1(r5)
442 mtspr SPRN_HID1,r4
445 lwz r4,CS_ICTRL(r5)
447 mtspr SPRN_ICTRL,r4
450 lwz r4,CS_LDSTCR(r5)
452 mtspr SPRN_LDSTCR,r4
455 lwz r4,CS_LDSTDB(r5)
457 mtspr SPRN_LDSTDB,r4
470 lwz r4,CS_HID2(r5)
471 rlwinm r4,r4,0,19,17
472 mtspr SPRN_HID2,r4
475 lwz r4,CS_HID1(r5)
476 rlwinm r5,r4,0,16,14
485 mtspr SPRN_HID1,r4
H A Didle_power7.S74 * To check IRQ_HAPPENED in r4
109 cmpwi cr0,r4,0
131 mfcr r4
132 std r4,_CCR(r1)
155 li r4,KVM_HWTHREAD_IN_NAP
156 stb r4,HSTATE_HWTHREAD_STATE(r13)
205 li r4,1
243 lwz r4,ADDROFF(powersave_nap)(r3)
244 cmpwi 0,r4,0
250 mr r4,r3
257 li r4,1
263 li r4,1
320 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
321 and r4,r4,r15
322 cmpwi cr1,r4,0 /* Check if first in subcore */
356 ld r4,_SDR1(r1)
357 mtspr SPRN_SDR1,r4
358 ld r4,_RPR(r1)
359 mtspr SPRN_RPR,r4
360 ld r4,_AMOR(r1)
361 mtspr SPRN_AMOR,r4
399 ld r4,_TSCR(r1)
400 mtspr SPRN_TSCR,r4
401 ld r4,_WORC(r1)
402 mtspr SPRN_WORC,r4
437 ld r4,_SPURR(r1)
438 mtspr SPRN_SPURR,r4
439 ld r4,_PURR(r1)
440 mtspr SPRN_PURR,r4
441 ld r4,_DSCR(r1)
442 mtspr SPRN_DSCR,r4
443 ld r4,_WORT(r1)
444 mtspr SPRN_WORT,r4
467 ld r4,_MSR(r1)
472 mtspr SPRN_SRR1,r4
478 li r4,0
495 ld r4,_MSR(r1)
499 mtspr SPRN_SRR1,r4
516 ld r4,_MSR(r1)
520 mtspr SPRN_SRR1,r4
H A Dreloc_32.S109 lwz r4, 4(r9) /* r4 = rela.r_info */
110 srwi r5, r4, 8 /* ELF32_R_SYM(r_info) */
130 /* Load the relocation type to r4 */
131 extrwi r4, r4, 8, 24 /* r4 = ELF32_R_TYPE(r_info) = ((char*)r4)[3] */
134 cmpwi r4, R_PPC_RELATIVE
136 lwz r4, 0(r9) /* r_offset */
139 stwx r0, r4, r7 /* memory[r4+r7]) = (u32)r0 */
144 cmpwi r4, R_PPC_ADDR16_HI
146 lwz r4, 0(r9) /* r_offset */
155 cmpwi r4, R_PPC_ADDR16_HA
157 lwz r4, 0(r9) /* r_offset */
168 cmpwi r4, R_PPC_ADDR16_LO
170 lwz r4, 0(r9) /* r_offset */
179 sthx r0, r4, r7 /* memory[r4+r7] = (u16)r0 */
191 dcbst r4,r7
193 icbi r4,r7
H A Dtm.S49 mfmsr r4
52 and. r0, r4, r3
54 or r4, r4, r3
55 mtmsrd r4
150 andis. r0, r4, MSR_VEC@h
162 andi. r0, r4, MSR_FP
225 ld r4, GPR7(r1) /* user r7 */
230 std r4, GPR7(r7)
246 mflr r4
251 std r4, _LINK(r7)
258 mfspr r4, SPRN_DSCR
261 std r4, THREAD_TM_DSCR(r12)
273 mfspr r4, SPRN_TFIAR
276 std r4, THREAD_TM_TFIAR(r12)
289 lwz r4, 8(r1)
291 mtcr r4
340 and. r5, r4, r5
357 andis. r0, r4, MSR_VEC@h
370 andi. r0, r4, MSR_FP
384 ld r4, _CTR(r7)
388 mtctr r4
393 ld r4, THREAD_TM_TAR(r3)
394 mtspr SPRN_TAR, r4
402 li r4, 0
403 mtmsrd r4, 1
463 li r4, MSR_RI
464 mtmsrd r4, 1
469 lwz r4, 8(r1)
471 mtcr r4
H A Dentry_64.S69 std r4,GPR4(r1)
161 clrldi r4,r4,32
215 ld r4,_LINK(r1)
223 mtlr r4
248 ld r4,GPR4(r1)
388 * On entry, r3 points to the THREAD for the current task, r4
471 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
474 ld r8,KSP(r4) /* new stack pointer */
489 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
535 ld r0, THREAD_BESCR(r4)
537 ld r0, THREAD_EBBHR(r4)
539 ld r0, THREAD_EBBRR(r4)
542 ld r0,THREAD_TAR(r4)
549 ld r0,THREAD_VRSAVE(r4)
555 lwz r6,THREAD_DSCR_INHERIT(r4)
556 ld r0,THREAD_DSCR(r4)
612 ld r4,TI_FLAGS(r9)
620 andi. r0,r4,_TIF_USER_WORK_MASK
639 1: andi. r0,r4,_TIF_NEED_RESCHED
646 andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
658 mr r30,r4
660 mr r4,r30
667 andis. r8,r4,_TIF_EMULATE_STACK_STORE@h
674 mr r4,r1 /* src: current exception frame */
681 2: ldx r0,r6,r4
693 0: ldarx r4,0,r5
694 andc r4,r4,r11
695 stdcx. r4,0,r5
701 andi. r0,r4,_TIF_NEED_RESCHED
715 RECONCILE_IRQ_STATE(r3,r4)
720 ld r4,TI_FLAGS(r9)
721 andi. r0,r4,_TIF_NEED_RESCHED
788 ldarx r4,0,r1
800 ld r4,_CTR(r1)
802 mtctr r4
804 ld r4,_XER(r1)
805 mtspr SPRN_XER,r4
823 ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */
824 andc r4,r4,r0 /* r0 contains MSR_RI here */
825 mtmsrd r4,1
841 ACCOUNT_CPU_USER_EXIT(r2, r4)
854 ld r4,GPR4(r1)
902 ld r4,_TRAP(r1)
903 clrldi r4,r4,60
904 or r4,r4,r3
905 std r4,_TRAP(r1)
972 mfcr r4
973 std r4,_CCR(r1)
1012 LOAD_REG_ADDR(r4,rtas_return_loc)
1013 clrldi r4,r4,2 /* convert to realmode address */
1014 mtlr r4
1027 LOAD_REG_ADDR(r4, rtas)
1028 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
1029 ld r4,RTASBASE(r4) /* get the rtas->base value */
1040 GET_PACA(r4)
1041 clrldi r4,r4,2 /* convert to realmode address */
1053 ld r1,PACAR1(r4) /* Restore our SP */
1054 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
1057 mtspr SPRN_SRR1,r4
1073 ld r4,_CCR(r1)
1074 mtcr r4
1111 mtsrr0 r4
1115 0: mflr r4
1116 addi r4,r4,(1f - 0b)
1117 mtlr r4
1150 ld r4,_CCR(r1)
1151 mtcr r4
1170 ld r4, 16(r11)
1194 ld r4, 16(r11)
1218 /* load r4 with local address */
1219 ld r4, 128(r1)
1220 subi r4, r4, MCOUNT_INSN_SIZE
1243 std r4, -32(r1)
1264 ld r4, -32(r1)
H A Depapr_hcalls.S24 PPC_LL r4, TI_LOCAL_FLAGS(r3) /* set napping bit */
25 ori r4, r4,_TLF_NAPPING /* so when we take an exception */
26 PPC_STL r4, TI_LOCAL_FLAGS(r3) /* it will return to our caller */
H A Dhead_32.S88 * r4: virtual address of boot_infos_t
96 * r4: initrd_start or if no initrd then 0
97 * r5: initrd_end - unused if r4 is 0
192 addis r4,r3,KERNELBASE@h /* current address of _start */
194 cmplw 0,r4,r5 /* already running at PHYSICAL_START? */
225 100: lwz r4,0(0)
227 cmpw 0,r4,r3
375 mfspr r4,SPRN_SPRG_RTAS
376 cmpwi cr1,r4,0
393 mfspr r4,SPRN_DAR /* into the hash table */
397 mfspr r4,SPRN_DAR
409 mr r4,r12 /* SRR0 is fault address */
411 1: mr r4,r12
423 mfspr r4,SPRN_DAR
424 stw r4,_DAR(r11)
783 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
784 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
792 lwzx r0,r6,r4
839 mr r4,r24
863 tophys(r4,r2)
864 addi r4,r4,THREAD /* phys address of our thread_struct */
865 CLR_TOP32(r4)
866 mtspr SPRN_SPRG_THREAD,r4
871 li r4,MSR_KERNEL
872 FIX_SRR1(r4,r5)
876 mtspr SPRN_SRR1,r4
915 li r4,0
916 3: mtsrin r3,r4
918 addis r4,r4,0x1000 /* address of next segment */
929 LOAD_BAT(0,r3,r4,r5)
930 LOAD_BAT(1,r3,r4,r5)
931 LOAD_BAT(2,r3,r4,r5)
932 LOAD_BAT(3,r3,r4,r5)
934 LOAD_BAT(4,r3,r4,r5)
935 LOAD_BAT(5,r3,r4,r5)
936 LOAD_BAT(6,r3,r4,r5)
937 LOAD_BAT(7,r3,r4,r5)
950 tophys(r4,r2)
951 addi r4,r4,THREAD /* init task's THREAD */
952 CLR_TOP32(r4)
953 mtspr SPRN_SPRG_THREAD,r4
967 mr r4,r31
977 lis r4,2f@h
978 ori r4,r4,2f@l
979 tophys(r4,r4)
982 mtspr SPRN_SRR0,r4
1004 li r4,MSR_KERNEL
1005 FIX_SRR1(r4,r5)
1009 mtspr SPRN_SRR1,r4
1019 lwz r3,MMCONTEXTID(r4)
1032 lwz r4,MM_PGD(r4)
1035 stw r4, 0x4(r5)
1037 li r4,0
1040 mtsrin r3,r4
1043 addis r4,r4,0x1000 /* address of next segment */
1119 addi r4, r3, __after_mmu_off - _start
1124 mtspr SPRN_SRR0,r4
1235 * r3 is the board info structure, r4 is the location for starting.
1262 mtlr r4
H A Dcpu_setup_fsl_booke.S127 mflr r4
137 mtlr r4
157 lwz r3, CPU_SPEC_FEATURES(r4)
166 stw r3, CPU_SPEC_FEATURES(r4)
191 mflr r4
207 mtlr r4
228 ld r10,CPU_SPEC_FEATURES(r4)
231 std r10,CPU_SPEC_FEATURES(r4)
H A Dhead_44x.S50 * r4 - Starting address of the init RAM disk
86 lis r4,KERNELBASE@h
87 ori r4,r4,KERNELBASE@l
89 rlwinm r5,r4,0,4,31 /* r5 = KERNELBASE % 256M */
91 add r3,r4,r3 /* Required Virutal Address */
107 addi r4,r2,THREAD /* init task's THREAD */
108 mtspr SPRN_SPRG_THREAD,r4
157 /* KERNELBASE&~0xfffffff => (r4,r5) */
158 li r4, 0 /* higer 32bit */
166 subfe r4,r6,r4
172 stw r4,0(r3)
187 lis r4,KERNELBASE@h
188 ori r4,r4,KERNELBASE@l
191 subf r4,r5,r4
195 add r7,r7,r4
205 mr r4,r31
214 lis r4, KERNELBASE@h
215 ori r4, r4, KERNELBASE@l
216 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
224 lis r4,start_kernel@h
225 ori r4,r4,start_kernel@l
228 mtspr SPRN_SRR0,r4
795 stw r4, 0x4(r5)
859 mfmsr r4 /* Get MSR */
860 andi. r4,r4,MSR_IS@l /* TS=1? */
869 li r4,0 /* Start at TLB entry 0 */
871 1: cmpw r23,r4 /* Is this our entry? */
873 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
874 skpinv: addi r4,r4,1 /* Increment */
875 cmpwi r4,64 /* Are we done? */
896 mr r4,r25
903 li r4, 0 /* Load the kernel physical address */
921 clrrwi r4,r4,10 /* Mask off the real page number */
932 tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
960 lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
961 ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
968 tlbwe r4,r0,PPC44x_TLB_XLAT
1033 addi r4,r2,THREAD /* init task's THREAD */
1034 mtspr SPRN_SPRG3,r4
1050 mfmsr r4 /* Get MSR */
1051 andi. r4,r4,MSR_IS@l /* TS=1? */
1079 addi r4,0,0
1089 tlbwe r4,r3,0
1096 addis r4,r4,0x100
1097 cmpwi r4,0
1174 lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
1175 ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
1186 tlbwe r4,r0,1
1232 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
1233 mtspr SPRN_IVPR,r4
/linux-4.1.27/arch/sh/lib/
H A Dashiftrt.S78 rotcl r4
80 subc r4,r4
82 shar r4
84 shar r4
86 shar r4
88 shar r4
90 shar r4
92 shar r4
94 shlr16 r4
95 shlr8 r4
97 exts.b r4,r4
99 shar r4
101 shar r4
103 shar r4
105 shar r4
107 shar r4
109 shar r4
111 shar r4
113 shlr16 r4
115 exts.w r4,r4
117 shar r4
119 shar r4
121 shar r4
123 shar r4
125 shar r4
127 shar r4
129 shar r4
131 shar r4
133 shar r4
135 shar r4
137 shar r4
139 shar r4
141 shar r4
143 shar r4
146 shar r4
H A Dcopy_page.S20 * r0, r1, r2, r3, r4, r5, r6, r7 --- scratch
30 mov r4,r10
42 mov.l @r11+,r4
55 mov.l r4,@-r10
86 mov r4,r3
107 EX( mov.b r1,@r4 )
109 add #1,r4
114 and r4,r1
144 EX_NO_POP( mov.b r0,@r4 )
146 add #1,r4
157 sub r4,r0
174 neg r4,r0
185 EX( mov.l r1,@r4 )
187 add #4,r4
199 EX( movca.l r0,@r4 )
201 EX( mov.l r0,@r4 )
204 EX( mov.l r1,@(4,r4) )
206 EX( mov.l r2,@(8,r4) )
208 EX( mov.l r7,@(12,r4) )
209 EX( mov.l r8,@(16,r4) )
210 EX( mov.l r9,@(20,r4) )
211 EX( mov.l r10,@(24,r4) )
212 EX( mov.l r11,@(28,r4) )
214 add #32,r4
223 EX( mov.l r1,@r4 )
225 add #4,r4
248 EX( mov.w r0,@r4 )
249 add #2,r4
255 EX( mov.l r0,@r4 )
256 EX( mov.l r1,@(4,r4) )
257 EX( mov.l r8,@(8,r4) )
258 EX( mov.l r9,@(12,r4) )
267 EX( mov.l r10,@(16,r4) )
268 EX( mov.l r1,@(20,r4) )
269 EX( mov.l r8,@(24,r4) )
270 EX( mov.w r0,@(28,r4) )
272 add #30,r4
278 EX( mov.w r0,@(30,r4) )
279 add #-2,r4
283 EX( mov.l r0,@(28,r4) )
284 EX( mov.l r8,@(24,r4) )
285 EX( mov.l r9,@(20,r4) )
291 mov.l r10,@(16,r4)
296 EX( mov.l r0,@(12,r4) )
297 EX( mov.l r8,@(8,r4) )
299 EX( mov.l r9,@(4,r4) )
300 EX( mov.w r0,@(2,r4) )
304 add #34,r4
313 EX( mov.w r0,@r4 )
315 EX( mov.w r0,@(2,r4) )
317 EX( mov.w r0,@(2,r4) )
319 EX( mov.w r0,@r4 )
322 add #4,r4
335 EX( mov.b r0,@r4 )
337 add #1,r4
338 EX( mov.w r0,@r4 )
340 EX( mov.b r0,@(2,r4) )
342 add #3,r4
344 EX( mov.b r0,@(3,r4) )
347 EX( mov.b r7,@r4 )
348 add #1,r4
349 EX( mov.w r0,@r4 )
351 add #3,r4
365 EX( mov.b r0,@r4 )
367 add #1,r4
380 sub r4,r0
H A Dmemmove.S17 cmp/hi r5,r4
25 sub r5,r4 ! From here, r4 has the distance to r0
33 add #-1,r4
34 add #1,r4
39 ! r0+r4--> [ ... ] r0 --> [ ... ]
44 mov r4,r1
65 mov.b r1,@(r0,r4)
66 add #1,r4
68 add r4,r0
74 add #-1,r4
85 add #-1,r4
91 mov.b r1,@(r0,r4)
94 add #-3,r4
99 mov.l r1,@(r0,r4)
105 add #4,r4
107 add #-1,r4
118 add #-1,r4
124 mov.b r1,@(r0,r4)
127 add #-2,r4
128 mov.l @(r0,r4),r1
130 add #-4,r4
143 mov.l r3,@(r0,r4)
155 mov.l r3,@(r0,r4)
162 add #7,r4
165 add #-1,r4
174 add #-1,r4
176 mov.b r1,@(r0,r4)
179 add #-1,r4
185 mov.w r1,@(r0,r4)
191 add #2,r4
193 mov.b r1,@(r0,r4)
206 add #-1,r4
212 mov.b r1,@(r0,r4)
215 mov.l @(r0,r4),r1
217 add #-4,r4
231 mov.l r3,@(r0,r4)
244 mov.l r3,@(r0,r4)
251 add #5,r4
254 add #-1,r4
H A Dudivsi3_i4i-Os.S49 mov.l r4,@-r15
52 swap.w r4,r0
53 shlr16 r4
59 div1 r5,r4
61 div1 r5,r4
62 div1 r5,r4
64 div1 r5,r4
65 xtrct r4,r0
66 xtrct r0,r4
68 swap.w r4,r4
69 div1 r5,r4
71 div1 r5,r4
72 xtrct r4,r0
75 mov.l @r15+,r4
79 div1 r5,r4
81 div1 r5,r4; div1 r5,r4; div1 r5,r4
82 div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
86 div1 r5,r4
88 div1 r5,r4
91 div1 r5,r4
96 xor r4,r0
100 div1 r5,r4
103 mov.l @r15+,r4
113 mov.l r4,@-r15
117 cmp/pz r4
122 neg r4,r4
124 swap.w r4,r0
131 neg r4,r4
136 swap.w r4,r0
140 shlr16 r4
H A Dudivsi3.S37 div1 r5,r4
39 div1 r5,r4; div1 r5,r4; div1 r5,r4
40 div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
43 div1 r5,r4; rotcl r0
44 div1 r5,r4; rotcl r0
45 div1 r5,r4; rotcl r0
46 rts; div1 r5,r4
54 swap.w r4,r0
55 shlr16 r4
59 div1 r5,r4
60 xtrct r4,r0
61 xtrct r0,r4
63 swap.w r4,r4
65 div1 r5,r4
67 xtrct r4,r0
75 xtrct r4,r0
76 xtrct r0,r4
H A Dmovmem.S57 mov.l r0,@(60,r4)
61 mov.l r0,@(56,r4)
65 mov.l r0,@(52,r4)
66 add #64,r4
75 mov.l r0,@(56,r4)
78 mov.l r0,@(52,r4)
86 mov.l r0,@(60,r4)
92 mov.l r0,@(56,r4)
98 mov.l r0,@(52,r4)
104 mov.l r0,@(48,r4)
110 mov.l r0,@(44,r4)
116 mov.l r0,@(40,r4)
122 mov.l r0,@(36,r4)
128 mov.l r0,@(32,r4)
134 mov.l r0,@(28,r4)
140 mov.l r0,@(24,r4)
146 mov.l r0,@(20,r4)
152 mov.l r0,@(16,r4)
158 mov.l r0,@(12,r4)
164 mov.l r0,@(8,r4)
170 mov.l r0,@(4,r4)
177 mov.l r0,@(0,r4)
193 mov.l r0,@(16,r4)
195 mov.l r1,@(20,r4)
206 add #-4,r4
209 mov.l r1,@(4,r4)
210 mov.l r2,@(8,r4)
213 mov.l r3,@(12,r4)
218 add #16,r4
222 mov.l r0,@r4
224 mov.l r1,@(4,r4)
226 mov.l r2,@(8,r4)
228 mov.l r3,@(12,r4)
235 mov.l r0,@r4
236 mov.l r1,@(4,r4)
238 mov.l r2,@(8,r4)
H A Dudivsi3_i4i.S65 mov r4,r0
75 mov.l r4,@-r15
88 mov.l r4,@-r15
98 dmulu.l r1,r4
101 mov r4,r0
105 addc r4,r0
106 mov.l @r15+,r4
112 neg r4,r0
116 mov.l @r15+,r4
129 mov.l r4,@-r15
143 xor r4,r0
146 xor r4,r0
149 shll16 r4
151 shll8 r4
153 mov.l r4,@-r15
154 shll16 r4
156 shll8 r4
159 rotcl r4
162 mov r4,r0
164 mov r5,r4
171 div1 r4,r1
172 mov.l @r15+,r4
185 mov.l r4,@-r15
189 cmp/pz r4
194 neg r4,r4
199 mov r4,r0
217 xtrct r4,r0
227 mov.l @r15+,r4 ! zero-extension and swap using LS unit.
230 or r4,r0
231 mov.l @r15+,r4
243 dmulu.l r1,r4
248 addc r4,r0
249 mov.l @r15+,r4
259 neg r4,r4
264 mov r4,r0
277 xtrct r4,r0
287 mov.l @r15+,r4 ! zero-extension and swap using LS unit.
290 or r4,r1
292 mov.l @r15+,r4
310 xor r4,r0
313 xor r4,r0
320 shll16 r4
321 mov r4,r1
323 mov r5,r4
330 div1 r4,r0
H A Dchecksum.S51 mov r4, r0
54 mov r4, r7 ! Keep a copy to check for alignment
63 mov.b @r4+, r0
71 mov r4, r0
83 mov.w @r4+, r0
98 mov.l @r4+, r0
99 mov.l @r4+, r2
100 mov.l @r4+, r3
102 mov.l @r4+, r0
104 mov.l @r4+, r2
106 mov.l @r4+, r3
108 mov.l @r4+, r0
110 mov.l @r4+, r2
131 mov.l @r4+, r2
147 mov.w @r4+, r0
155 mov.b @r4+, r0
207 ! r4: const char *SRC
221 mov r4,r1
249 SRC( mov.b @r4+,r1 )
250 SRC( mov.b @r4+,r0 )
282 SRC( mov.w @r4+,r0 )
298 SRC( mov.l @r4+,r0 )
299 SRC( mov.l @r4+,r1 )
305 SRC( mov.l @r4+,r0 )
306 SRC( mov.l @r4+,r1 )
312 SRC( mov.l @r4+,r0 )
313 SRC( mov.l @r4+,r1 )
319 SRC( mov.l @r4+,r0 )
320 SRC( mov.l @r4+,r1 )
341 SRC( mov.l @r4+,r0 )
359 SRC( mov.w @r4+,r0 )
369 SRC( mov.b @r4+,r0 )
H A Dmemcpy.S18 mov r4,r0
19 sub r4,r5 ! From here, r5 has the distance to r0
28 ! r4 --> [ ... ] DST [ ... ] SRC
52 7: mov r4,r2
81 mov r4,r2
89 cmp/eq r4,r0
113 mov r4,r2
141 cmp/eq r4,r0
160 mov r4,r2
169 cmp/eq r4,r0
195 mov r4,r2
223 cmp/eq r4,r0
/linux-4.1.27/arch/powerpc/boot/
H A Dstring.S18 addi r4,r4,-1
19 1: lbzu r0,1(r4)
31 addi r4,r4,-1
32 1: lbzu r0,1(r4)
41 addi r4,r4,-1
46 1: lbzu r0,1(r4)
56 cmpw 0,r0,r4
66 addi r4,r4,-1
69 lbzu r0,1(r4)
79 addi r4,r4,-1
82 lbzu r0,1(r4)
90 addi r4,r3,-1
91 1: lbzu r0,1(r4)
94 subf r3,r3,r4
99 rlwimi r4,r4,8,16,23
100 rlwimi r4,r4,16,0,15
104 stwu r4,4(r6)
112 1: stwu r4,4(r6)
119 8: stbu r4,1(r6)
125 cmplw 0,r3,r4
133 addi r4,r4,-4
138 andi. r0,r4,3 /* check src word aligned too */
140 1: lwz r7,4(r4)
141 lwzu r8,8(r4)
148 lwzu r0,4(r4)
154 addi r4,r4,3
156 4: lbzu r0,1(r4)
162 add r7,r0,r4
167 6: lbz r7,4(r4)
168 addi r4,r4,1
182 add r4,r4,r5
187 andi. r0,r4,3
189 1: lwz r7,-4(r4)
190 lwzu r8,-8(r4)
197 lwzu r0,-4(r4)
203 4: lbzu r0,-1(r4)
208 subf r7,r0,r4
213 6: lbzu r7,-1(r4)
229 cmpw r0,r4
241 addi r4,r4,-1
243 lbzu r0,1(r4)
H A Depapr-wrapper.c1 extern void epapr_platform_init(unsigned long r3, unsigned long r4,
5 void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, platform_init() argument
8 epapr_platform_init(r3, r4, r5, r6, r7); platform_init()
H A Ddiv64.S6 * the 64-bit quotient, and r4 contains the divisor.
22 cmplw r5,r4
26 divwu r7,r5,r4 # if dividend.hi >= divisor,
27 mullw r0,r7,r4 # quotient.hi = dividend.hi / divisor
36 addc r9,r4,r10 # rounding up (so the estimate cannot
44 2: mullw r10,r11,r4 # to get an estimate of the quotient,
45 mulhwu r9,r11,r4 # multiply the estimate by the divisor,
50 3: cmplw r6,r4
52 divwu r0,r6,r4 # perform the remaining 32-bit division
53 mullw r10,r0,r4 # and get the remainder
78 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
83 or r4,r4,r6 # LSW |= t1
86 or r4,r4,r7 # LSW |= t2
94 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
95 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
97 slw r4,r4,r5 # LSW = LSW << count
104 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
108 or r4,r4,r6 # LSW |= t1
110 or r4,r4,r7 # LSW |= t2
H A Dutil.S45 mfspr r4,SPRN_PVR
46 srwi r4,r4,16
47 cmpwi 0,r4,1 /* 601 ? */
58 mulli r4,r3,1000 /* nanoseconds */
59 /* Change r4 to be the number of ticks using:
71 add r4,r4,r5
72 addi r4,r4,-1
73 divw r4,r4,r5 /* BUS ticks */
85 addc r9,r6,r4 /* Compute end time */
H A Dcuboot.h4 void cuboot_init(unsigned long r4, unsigned long r5,
11 cuboot_init(r4, r5, r6, r7, bd.bi_memstart + bd.bi_memsize); \
H A Dcuboot.c20 void cuboot_init(unsigned long r4, unsigned long r5, cuboot_init() argument
26 loader_info.initrd_addr = r4; cuboot_init()
27 loader_info.initrd_size = r4 ? r5 - r4 : 0; cuboot_init()
H A Dps3-head.S55 li r4, 0x60
56 mtctr r4
62 li r4, 0
63 lwz r3, 0(r4)
70 lis r4, _zimage_start@ha
71 addi r4, r4, _zimage_start@l
72 mtctr r4
H A Dps3-hvcall.S33 * 1: r3,r4 <-> r3
34 * 2: r5,r6 <-> r4
82 LOAD_64_REG r3,r3,r4
86 LOAD_64_REG r4,r5,r6
139 std r4, 0(r11)
140 mr r4, r3
147 std r4, 0(r11)
154 std r4, 0(r11)
H A Dmvme5100.c19 void platform_init(unsigned long r3, unsigned long r4, unsigned long r5) platform_init() argument
H A Dof.c29 void epapr_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
88 void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, platform_init() argument
93 of_platform_init(r3, r4, (void *)r5); platform_init()
95 epapr_platform_init(r3, r4, r5, r6, r7); platform_init()
/linux-4.1.27/drivers/scsi/arm/
H A Dacornscsi-io.S25 stmfd sp!, {r4 - r7, lr}
32 ldmia r0!, {r3, r4, r5, r6}
34 orr r3, r3, r4, lsl #16
35 and r4, r5, lr
36 orr r4, r4, r6, lsl #16
44 LOADREGS(fd, sp!, {r4 - r7, pc})
48 ldmia r0!, {r3, r4, r5, r6}
50 orr r3, r3, r4, lsl #16
51 and r4, r5, lr
52 orr r4, r4, r6, lsl #16
53 stmia r1!, {r3 - r4}
54 LOADREGS(eqfd, sp!, {r4 - r7, pc})
59 ldmia r0!, {r3, r4}
61 orr r3, r3, r4, lsl #16
63 LOADREGS(eqfd, sp!, {r4 - r7, pc})
72 LOADREGS(fd, sp!, {r4 - r7, pc})
79 stmfd sp!, {r4 - r6, lr}
84 ldmia r1!, {r4, r6, ip, lr}
85 mov r3, r4, lsl #16
87 mov r4, r4, lsr #16
88 orr r4, r4, r4, lsl #16
93 stmia r0!, {r3, r4, r5, r6}
96 mov r4, ip, lsr #16
97 orr r4, r4, r4, lsl #16
102 stmia r0!, {r3, r4, ip, lr}
104 LOADREGS(fd, sp!, {r4 - r6, pc})
108 ldmia r1!, {r4, r6}
109 mov r3, r4, lsl #16
111 mov r4, r4, lsr #16
112 orr r4, r4, r4, lsl #16
117 stmia r0!, {r3, r4, r5, r6}
118 LOADREGS(eqfd, sp!, {r4 - r6, pc})
123 ldr r4, [r1], #4
124 mov r3, r4, lsl #16
126 mov r4, r4, lsr #16
127 orr r4, r4, r4, lsl #16
128 stmia r0!, {r3, r4}
129 LOADREGS(eqfd, sp!, {r4 - r6, pc})
137 LOADREGS(fd, sp!, {r4 - r6, pc})
/linux-4.1.27/arch/m32r/lib/
H A Dmemset.S23 mv r4, r0 || cmpz r2
30 and3 r3, r4, #3
35 stb r1, @r4 || addi r4, #1
43 or r1, r3 || addi r4, #-4
47 st r1, @+r4 || addi r2, #-4
50 st r1, @+r4
54 and3 r3, r4, #15
59 or r1, r3 || addi r4, #-4
63 ld r3, @(4,r4) /* cache line allocate */
64 st r1, @+r4 || addi r2, #-16
65 st r1, @+r4 || cmpu r2, r5
66 st r1, @+r4
67 st r1, @+r4
81 addi r4, #4
84 addi r2, #-1 || stb r1, @r4+
88 addi r2, #-1 || stb r1, @r4
89 addi r4, #1
101 mv r4, r0
108 and3 r3, r4, #3
113 stb r1, @r4
114 addi r4, #1
127 addi r4, #-4
129 st r1, @+r4
133 st r1, @+r4
137 and3 r3, r4, #15
145 addi r4, #-4
147 ld r3, @(4,r4) /* cache line allocate */
149 st r1, @+r4
150 st r1, @+r4
152 st r1, @+r4
153 st r1, @+r4
167 addi r4, #4
170 stb r1, @r4
171 addi r4, #1
H A Dmemcpy.S23 mv r4, r0 || mv r7, r0
33 addi r4, #-4
36 st r7, @+r4 || cmpz r2
38 addi r4, #4 || jc r14 ; return if r2=0
42 addi r2, #-1 || stb r7, @r4+
47 addi r2, #-1 || stb r7, @r4
48 addi r4, #1
61 mv r4, r0
72 addi r4, #-4
76 st r7, @+r4
79 addi r4, #4
84 stb r7, @r4
85 addi r4, #1
H A Dstrlen.S28 ld r1, @r6+ || not r4, r0
29 sub r0, r5 || and r4, r7
30 and r4, r0
31 bnez r4, strlen_last_bytes
32 ld r0, @r6+ || not r4, r1
33 sub r1, r5 || and r4, r7
34 and r4, r1 || addi r2, #4
35 bnez r4, strlen_last_bytes
76 not r4, r0 ; NOTE: If a null char. exists, return 0.
78 and r4, r7 ; return 0;
79 and r4, r0
80 bnez r4, strlen_last_bytes
84 not r4, r1 ; NOTE: If a null char. exists, return 0.
86 and r4, r7 ; return 0;
87 and r4, r1
88 bnez r4, strlen_last_bytes
H A Ddelay.c90 "and3 r4, %0, #0xffff \n\t" __const_udelay()
92 "mul r4, r5 \n\t" __const_udelay()
94 "srli r4, #16 \n\t" __const_udelay()
96 "add r4, r5 \n\t" __const_udelay()
100 "add r4, r5 \n\t" __const_udelay()
102 "srli r4, #16 \n\t" __const_udelay()
104 "add r4, r5 \n\t" __const_udelay()
105 "mv %0, r4 \n\t" __const_udelay()
108 : "r4", "r5", "r6" __const_udelay()
/linux-4.1.27/arch/powerpc/platforms/52xx/
H A Dlite5200_sleep.S21 /* helpers... beware: r10 and r4 are overwritten */
24 stw r10, ((addr)*4)(r4);
27 lwz r10, ((addr)*4)(r4); \
45 mr r8, r4 /* save MBAR va */
49 lis r4, lite5200_wakeup@h
50 ori r4, r4, lite5200_wakeup@l
51 sub r4, r4, r3
52 stw r4, 0(r3)
62 lis r4, registers@h
63 ori r4, r4, registers@l
65 stw r10, (0x1d*4)(r4)
67 /* save registers to r4 [destroys r10] */
71 /* flush caches [destroys r3, r4] */
76 mr r4, r7
83 stw r5, 0(r4)
85 addi r4, r4, 4
108 lwz r4, SDRAM_CTRL(r8)
111 oris r4, r4, SC_MODE_EN@h /* mode_en */
112 stw r4, SDRAM_CTRL(r8)
115 ori r4, r4, SC_SOFT_PRE /* soft_pre */
116 stw r4, SDRAM_CTRL(r8)
118 xori r4, r4, SC_SOFT_PRE
120 xoris r4, r4, SC_MODE_EN@h /* !mode_en */
121 stw r4, SDRAM_CTRL(r8)
132 oris r4, r4, (SC_REF_EN | SC_CKE)@h
133 xoris r4, r4, (SC_CKE)@h /* ref_en !cke */
134 stw r4, SDRAM_CTRL(r8)
142 lwz r4, CDM_CE(r8)
143 ori r4, r4, CDM_SDRAM
144 xori r4, r4, CDM_SDRAM
145 stw r4, CDM_CE(r8)
154 li r4, 0x02
155 stb r4, GPIOW_GPIOE(r8) /* enable gpio_wkup1 */
158 stb r4, GPIOW_DVO(r8) /* "output" high */
160 stb r4, GPIOW_DDR(r8) /* output */
162 stb r4, GPIOW_DVO(r8) /* output high */
170 li r4, 0
171 stb r4, GPIOW_DVO(r8) /* output low */
216 /* kernel offset (r4 is still set from restore_registers) */
217 addis r4, r4, CONFIG_KERNEL_START@h
221 lwz r10, (4*0x1b)(r4)
234 lwz r10, (4*0x18)(r4)
243 lwz r10, (0x1d*4)(r4)
264 stw r10, ((addr)*4)(r4);
273 stw r0, 0(r4)
274 stw r1, 0x4(r4)
275 stw r2, 0x8(r4)
276 stmw r11, 0xc(r4) /* 0xc -> 0x5f, (0x18*4-1) */
282 stw r10, (4*0x1b)(r4)
328 lwz r10, ((addr)*4)(r4); \
338 lis r4, registers@h
339 ori r4, r4, registers@l
342 subis r4, r4, CONFIG_KERNEL_START@h
344 lwz r0, 0(r4)
345 lwz r1, 0x4(r4)
346 lwz r2, 0x8(r4)
347 lmw r11, 0xc(r4)
406 li r4,NUM_CACHE_LINES
407 mtctr r4
409 lwz r4,0(r3)
H A Dmpc52xx_sleep.S68 lwz r8, 0x4(r4) /* sdram->ctrl */
71 stw r8, 0x4(r4)
75 stw r8, 0x4(r4)
80 stw r8, 0x4(r4)
85 stw r8, 0x4(r4)
111 lwz r8, 0x4(r4)
113 stw r8, 0x4(r4)
/linux-4.1.27/arch/powerpc/lib/
H A Dcopypage_64.S35 dcbt r9,r4
46 ld r5,0(r4)
47 ld r6,8(r4)
48 ld r7,16(r4)
49 ldu r8,24(r4)
52 ld r9,8(r4)
53 ld r10,16(r4)
56 ld r11,24(r4)
57 ld r12,32(r4)
60 ld r5,40(r4)
61 ld r6,48(r4)
64 ld r7,56(r4)
65 ld r8,64(r4)
68 ld r9,72(r4)
69 ld r10,80(r4)
72 ld r11,88(r4)
73 ld r12,96(r4)
76 ld r5,104(r4)
77 ld r6,112(r4)
80 ld r7,120(r4)
81 ldu r8,128(r4)
86 ld r9,8(r4)
87 ld r10,16(r4)
90 ld r11,24(r4)
91 ld r12,32(r4)
94 ld r5,40(r4)
95 ld r6,48(r4)
98 ld r7,56(r4)
99 ld r8,64(r4)
102 ld r9,72(r4)
103 ld r10,80(r4)
106 ld r11,88(r4)
107 ld r12,96(r4)
H A Dcopyuser_power7.S89 ld r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
100 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
109 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
117 neg r6,r4
122 err1; lbz r0,0(r4)
123 addi r4,r4,1
128 err1; lhz r0,0(r4)
129 addi r4,r4,2
134 err1; lwz r0,0(r4)
135 addi r4,r4,4
162 err2; ld r0,0(r4)
163 err2; ld r6,8(r4)
164 err2; ld r7,16(r4)
165 err2; ld r8,24(r4)
166 err2; ld r9,32(r4)
167 err2; ld r10,40(r4)
168 err2; ld r11,48(r4)
169 err2; ld r12,56(r4)
170 err2; ld r14,64(r4)
171 err2; ld r15,72(r4)
172 err2; ld r16,80(r4)
173 err2; ld r17,88(r4)
174 err2; ld r18,96(r4)
175 err2; ld r19,104(r4)
176 err2; ld r20,112(r4)
177 err2; ld r21,120(r4)
178 addi r4,r4,128
216 err1; ld r0,0(r4)
217 err1; ld r6,8(r4)
218 err1; ld r7,16(r4)
219 err1; ld r8,24(r4)
220 err1; ld r9,32(r4)
221 err1; ld r10,40(r4)
222 err1; ld r11,48(r4)
223 err1; ld r12,56(r4)
224 addi r4,r4,64
237 err1; ld r0,0(r4)
238 err1; ld r6,8(r4)
239 err1; ld r7,16(r4)
240 err1; ld r8,24(r4)
241 addi r4,r4,32
250 err1; ld r0,0(r4)
251 err1; ld r6,8(r4)
252 addi r4,r4,16
263 err1; lwz r0,0(r4) /* Less chance of a reject with word ops */
264 err1; lwz r6,4(r4)
265 addi r4,r4,8
271 err1; lwz r0,0(r4)
272 addi r4,r4,4
277 err1; lhz r0,0(r4)
278 addi r4,r4,2
283 err1; lbz r0,0(r4)
302 ld r4,STK_REG(R30)(r1)
311 clrrdi r6,r4,7
345 xor r6,r4,r3
355 err3; lbz r0,0(r4)
356 addi r4,r4,1
361 err3; lhz r0,0(r4)
362 addi r4,r4,2
367 err3; lwz r0,0(r4)
368 addi r4,r4,4
373 err3; ld r0,0(r4)
374 addi r4,r4,8
391 err3; lvx v1,r0,r4
392 addi r4,r4,16
397 err3; lvx v1,r0,r4
398 err3; lvx v0,r4,r9
399 addi r4,r4,32
405 err3; lvx v3,r0,r4
406 err3; lvx v2,r4,r9
407 err3; lvx v1,r4,r10
408 err3; lvx v0,r4,r11
409 addi r4,r4,64
436 err4; lvx v7,r0,r4
437 err4; lvx v6,r4,r9
438 err4; lvx v5,r4,r10
439 err4; lvx v4,r4,r11
440 err4; lvx v3,r4,r12
441 err4; lvx v2,r4,r14
442 err4; lvx v1,r4,r15
443 err4; lvx v0,r4,r16
444 addi r4,r4,128
466 err3; lvx v3,r0,r4
467 err3; lvx v2,r4,r9
468 err3; lvx v1,r4,r10
469 err3; lvx v0,r4,r11
470 addi r4,r4,64
478 err3; lvx v1,r0,r4
479 err3; lvx v0,r4,r9
480 addi r4,r4,32
486 err3; lvx v1,r0,r4
487 addi r4,r4,16
495 err3; ld r0,0(r4)
496 addi r4,r4,8
501 err3; lwz r0,0(r4)
502 addi r4,r4,4
507 err3; lhz r0,0(r4)
508 addi r4,r4,2
513 err3; lbz r0,0(r4)
526 err3; lbz r0,0(r4)
527 addi r4,r4,1
532 err3; lhz r0,0(r4)
533 addi r4,r4,2
538 err3; lwz r0,0(r4)
539 addi r4,r4,4
544 err3; lwz r0,0(r4) /* Less chance of a reject with word ops */
545 err3; lwz r7,4(r4)
546 addi r4,r4,8
563 LVS(v16,0,r4) /* Setup permute control vector */
564 err3; lvx v0,0,r4
565 addi r4,r4,16
568 err3; lvx v1,r0,r4
570 addi r4,r4,16
576 err3; lvx v1,r0,r4
578 err3; lvx v0,r4,r9
580 addi r4,r4,32
586 err3; lvx v3,r0,r4
588 err3; lvx v2,r4,r9
590 err3; lvx v1,r4,r10
592 err3; lvx v0,r4,r11
594 addi r4,r4,64
621 err4; lvx v7,r0,r4
623 err4; lvx v6,r4,r9
625 err4; lvx v5,r4,r10
627 err4; lvx v4,r4,r11
629 err4; lvx v3,r4,r12
631 err4; lvx v2,r4,r14
633 err4; lvx v1,r4,r15
635 err4; lvx v0,r4,r16
637 addi r4,r4,128
659 err3; lvx v3,r0,r4
661 err3; lvx v2,r4,r9
663 err3; lvx v1,r4,r10
665 err3; lvx v0,r4,r11
667 addi r4,r4,64
675 err3; lvx v1,r0,r4
677 err3; lvx v0,r4,r9
679 addi r4,r4,32
685 err3; lvx v1,r0,r4
687 addi r4,r4,16
693 addi r4,r4,-16 /* Unwind the +16 load offset */
696 err3; lwz r0,0(r4) /* Less chance of a reject with word ops */
697 err3; lwz r6,4(r4)
698 addi r4,r4,8
704 err3; lwz r0,0(r4)
705 addi r4,r4,4
710 err3; lhz r0,0(r4)
711 addi r4,r4,2
716 err3; lbz r0,0(r4)
H A Dmemcpy_power7.S50 neg r6,r4
55 lbz r0,0(r4)
56 addi r4,r4,1
61 lhz r0,0(r4)
62 addi r4,r4,2
67 lwz r0,0(r4)
68 addi r4,r4,4
95 ld r0,0(r4)
96 ld r6,8(r4)
97 ld r7,16(r4)
98 ld r8,24(r4)
99 ld r9,32(r4)
100 ld r10,40(r4)
101 ld r11,48(r4)
102 ld r12,56(r4)
103 ld r14,64(r4)
104 ld r15,72(r4)
105 ld r16,80(r4)
106 ld r17,88(r4)
107 ld r18,96(r4)
108 ld r19,104(r4)
109 ld r20,112(r4)
110 ld r21,120(r4)
111 addi r4,r4,128
149 ld r0,0(r4)
150 ld r6,8(r4)
151 ld r7,16(r4)
152 ld r8,24(r4)
153 ld r9,32(r4)
154 ld r10,40(r4)
155 ld r11,48(r4)
156 ld r12,56(r4)
157 addi r4,r4,64
170 ld r0,0(r4)
171 ld r6,8(r4)
172 ld r7,16(r4)
173 ld r8,24(r4)
174 addi r4,r4,32
183 ld r0,0(r4)
184 ld r6,8(r4)
185 addi r4,r4,16
196 lwz r0,0(r4) /* Less chance of a reject with word ops */
197 lwz r6,4(r4)
198 addi r4,r4,8
204 lwz r0,0(r4)
205 addi r4,r4,4
210 lhz r0,0(r4)
211 addi r4,r4,2
216 lbz r0,0(r4)
229 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
237 ld r4,STK_REG(R30)(r1)
246 clrrdi r6,r4,7
278 xor r6,r4,r3
288 lbz r0,0(r4)
289 addi r4,r4,1
294 lhz r0,0(r4)
295 addi r4,r4,2
300 lwz r0,0(r4)
301 addi r4,r4,4
306 ld r0,0(r4)
307 addi r4,r4,8
324 lvx v1,r0,r4
325 addi r4,r4,16
330 lvx v1,r0,r4
331 lvx v0,r4,r9
332 addi r4,r4,32
338 lvx v3,r0,r4
339 lvx v2,r4,r9
340 lvx v1,r4,r10
341 lvx v0,r4,r11
342 addi r4,r4,64
369 lvx v7,r0,r4
370 lvx v6,r4,r9
371 lvx v5,r4,r10
372 lvx v4,r4,r11
373 lvx v3,r4,r12
374 lvx v2,r4,r14
375 lvx v1,r4,r15
376 lvx v0,r4,r16
377 addi r4,r4,128
399 lvx v3,r0,r4
400 lvx v2,r4,r9
401 lvx v1,r4,r10
402 lvx v0,r4,r11
403 addi r4,r4,64
411 lvx v1,r0,r4
412 lvx v0,r4,r9
413 addi r4,r4,32
419 lvx v1,r0,r4
420 addi r4,r4,16
428 ld r0,0(r4)
429 addi r4,r4,8
434 lwz r0,0(r4)
435 addi r4,r4,4
440 lhz r0,0(r4)
441 addi r4,r4,2
446 lbz r0,0(r4)
460 lbz r0,0(r4)
461 addi r4,r4,1
466 lhz r0,0(r4)
467 addi r4,r4,2
472 lwz r0,0(r4)
473 addi r4,r4,4
478 lwz r0,0(r4) /* Less chance of a reject with word ops */
479 lwz r7,4(r4)
480 addi r4,r4,8
497 LVS(v16,0,r4) /* Setup permute control vector */
498 lvx v0,0,r4
499 addi r4,r4,16
502 lvx v1,r0,r4
504 addi r4,r4,16
510 lvx v1,r0,r4
512 lvx v0,r4,r9
514 addi r4,r4,32
520 lvx v3,r0,r4
522 lvx v2,r4,r9
524 lvx v1,r4,r10
526 lvx v0,r4,r11
528 addi r4,r4,64
555 lvx v7,r0,r4
557 lvx v6,r4,r9
559 lvx v5,r4,r10
561 lvx v4,r4,r11
563 lvx v3,r4,r12
565 lvx v2,r4,r14
567 lvx v1,r4,r15
569 lvx v0,r4,r16
571 addi r4,r4,128
593 lvx v3,r0,r4
595 lvx v2,r4,r9
597 lvx v1,r4,r10
599 lvx v0,r4,r11
601 addi r4,r4,64
609 lvx v1,r0,r4
611 lvx v0,r4,r9
613 addi r4,r4,32
619 lvx v1,r0,r4
621 addi r4,r4,16
627 addi r4,r4,-16 /* Unwind the +16 load offset */
630 lwz r0,0(r4) /* Less chance of a reject with word ops */
631 lwz r6,4(r4)
632 addi r4,r4,8
638 lwz r0,0(r4)
639 addi r4,r4,4
644 lhz r0,0(r4)
645 addi r4,r4,2
650 lbz r0,0(r4)
H A Dcopy_32.S17 lwz r7,4(r4); \
18 lwz r8,8(r4); \
19 lwz r9,12(r4); \
20 lwzu r10,16(r4); \
28 lwz r7,4(r4); \
30 lwz r8,8(r4); \
32 lwz r9,12(r4); \
34 lwzu r10,16(r4); \
73 rlwimi r4,r4,8,16,23
74 rlwimi r4,r4,16,0,15
78 stwu r4,4(r6)
86 1: stwu r4,4(r6)
93 8: stbu r4,1(r6)
98 cmplw 0,r3,r4
105 addi r4,r4,-4
110 1: lwz r7,4(r4)
111 lwzu r8,8(r4)
118 lwzu r0,4(r4)
124 addi r4,r4,3
126 4: lbzu r0,1(r4)
132 6: lbz r7,4(r4)
133 addi r4,r4,1
146 add r4,r4,r5
151 1: lwz r7,-4(r4)
152 lwzu r8,-8(r4)
159 lwzu r0,-4(r4)
165 4: lbzu r0,-1(r4)
170 6: lbzu r7,-1(r4)
180 addi r4,r4,-4
191 70: lbz r9,4(r4) /* do some bytes */
193 addi r4,r4,1
200 72: lwzu r9,4(r4) /* do some words */
231 111: dcbt r3,r4
235 dcbt r3,r4
243 53: dcbt r3,r4
273 30: lwzu r0,4(r4)
280 40: lbz r0,4(r4)
282 addi r4,r4,1
360 130: lbz r0,4(r4)
362 addi r4,r4,1
H A Dmemcpy_64.S28 addi r4,r4,-1
31 1: lbzu r10,1(r4)
40 dcbt 0,r4
56 andi. r0,r4,7
60 ld r9,0(r4)
61 addi r4,r4,-8
66 addi r4,r4,8
69 1: ld r9,8(r4)
71 2: ldu r8,16(r4)
79 lwz r9,8(r4)
80 addi r4,r4,4
84 lhz r9,8(r4)
85 addi r4,r4,2
89 lbz r9,8(r4)
97 subf r4,r0,r4
108 ld r9,0(r4) # 3+2n loads, 2+2n stores
109 ld r0,8(r4)
111 ldu r9,16(r4)
116 ld r0,8(r4)
120 0: ld r0,0(r4) # 4+2n loads, 3+2n stores
121 ldu r9,8(r4)
125 ld r0,8(r4)
128 ldu r9,16(r4)
137 ld r0,8(r4)
141 ldu r9,16(r4)
159 ld r0,8(r4)
183 lbz r0,0(r4)
187 lhzx r0,r7,r4
191 lwzx r0,r7,r4
194 add r4,r6,r4
200 lwz r0,0(r4)
201 lwz r9,4(r4)
202 addi r4,r4,8
207 lwz r0,0(r4)
208 addi r4,r4,4
212 lhz r0,0(r4)
213 addi r4,r4,2
217 lbz r0,0(r4)
H A Dcopyuser_64.S31 or r0,r3,r4
36 std r4,-16(r1)
38 dcbt 0,r4
58 andi. r0,r4,7
64 20: ld r7,0(r4)
65 220: ld r6,8(r4)
66 addi r4,r4,16
71 addi r4,r4,-16
75 21: ld r7,16(r4)
76 221: ld r6,24(r4)
77 addi r4,r4,32
80 22: ld r9,0(r4)
81 222: ld r8,8(r4)
90 addi r4,r4,16
94 244: ld r9,0(r4)
95 addi r4,r4,8
99 23: lwz r9,0(r4)
100 addi r4,r4,4
104 44: lhz r9,0(r4)
105 addi r4,r4,2
109 45: lbz r9,0(r4)
117 subf r4,r0,r4
127 24: ld r9,0(r4) /* 3+2n loads, 2+2n stores */
128 25: ld r0,8(r4)
130 26: ldu r9,16(r4)
135 27: ld r0,8(r4)
138 28: ld r0,0(r4) /* 4+2n loads, 3+2n stores */
139 29: ldu r9,8(r4)
143 30: ld r0,8(r4)
146 31: ldu r9,16(r4)
154 32: ld r0,8(r4)
158 33: ldu r9,16(r4)
178 34: ld r0,8(r4)
217 35: lbz r0,0(r4)
221 36: lhzx r0,r7,r4
225 37: lwzx r0,r7,r4
228 add r4,r6,r4
234 38: lwz r0,0(r4)
235 39: lwz r9,4(r4)
236 addi r4,r4,8
241 40: lwz r0,0(r4)
242 addi r4,r4,4
246 41: lhz r0,0(r4)
247 addi r4,r4,2
251 42: lbz r0,0(r4)
302 ld r4,-16(r1)
305 add r4,r4,r6
312 43: lbz r0,0(r4)
313 addi r4,r4,1
325 mr r4,r3
327 1: andi. r9,r4,7
329 90: stb r0,0(r4)
331 addi r4,r4,1
339 91: std r0,0(r4)
340 addi r4,r4,8
344 92: stb r0,0(r4)
345 addi r4,r4,1
541 74: addi r4,r4,640
596 ld r4,-16(r1)
H A Dstring_64.S69 mtctr r4
73 addi r4,r4,-1
77 mr r3,r4
81 cmpdi r4,32
102 3: sub r4,r4,r6
104 cmpdi r4,32
105 cmpdi cr1,r4,512
110 srdi r6,r4,5
120 addi r4,r4,-32
125 cmpdi r4,16
130 addi r4,r4,-16
134 clrldi r4,r4,(64-4)
135 mtocrf 0x01,r4
160 addi r4,r4,-8
171 cmpd r4,r10
188 sub r4,r4,r5
190 13: srd r6,r4,r7
198 and r4,r4,r10
200 cmpdi r4,32
H A Dmemcmp_64.S35 or r6,r3,r4
49 lbz rB,0(r4)
55 lbz rB,1(r4)
61 lbz rB,2(r4)
67 lbz rB,3(r4)
72 addi r4,r4,4
100 LD rB,0,r4
103 LD rD,off8,r4
106 LD rF,off16,r4
109 LD rH,off24,r4
113 addi r4,r4,32
118 LD rB,0,r4
122 LD rD,off8,r4
126 LD rF,off16,r4
131 LD rH,off24,r4
136 addi r4,r4,32
143 LD rB,0,r4
148 LD rD,off8,r4
153 LD rF,off16,r4
158 LD rH,off24,r4
163 addi r4,r4,32
H A Dchecksum_32.S29 addic. r4,r4,-2
31 mtctr r4
33 1: lwzu r4,4(r3)
34 adde r0,r0,r4
49 addc r0,r3,r4 /* add 4 32-bit words together */
68 srwi. r6,r4,2
74 subi r4,r4,2
76 srwi. r6,r4,2 /* # words to do */
82 andi. r4,r4,3
83 3: cmpwi 0,r4,2
87 subi r4,r4,2
89 4: cmpwi 0,r4,1
109 subi r4,r4,4
112 andi. r9,r4,2 /* Align dst to longword boundary */
117 91: sth r6,4(r4)
118 addi r4,r4,2
130 75: stw r6,4(r4)
132 76: stw r9,8(r4)
134 77: stw r10,12(r4)
136 78: stwu r11,16(r4)
142 92: stwu r9,4(r4)
151 93: sth r6,4(r4)
152 addi r4,r4,2
157 94: stb r6,4(r4)
173 95: sth r6,4(r4)
174 addi r4,r4,2
180 96: stwu r6,4(r4)
187 addi r4,r4,3
188 97: stbu r6,1(r4)
H A Dhweight_64.S46 srdi r4,r3,8
47 add r3,r4,r3
70 srdi r4,r3,16
71 add r3,r4,r3
72 srdi r4,r3,8
73 add r3,r4,r3
97 srdi r4,r3,32
98 add r3,r4,r3
99 srdi r4,r3,16
100 add r3,r4,r3
101 srdi r4,r3,8
102 add r3,r4,r3
H A Dldstfp.S33 20: \op reg,0,r4
78 /* Load FP reg N from float at *p. N is in r3, p in r4. */
91 2: lfs fr0,0(r4)
105 /* Load FP reg N from double at *p. N is in r3, p in r4. */
118 2: lfd fr0,0(r4)
132 /* Store FP reg N to float at *p. N is in r3, p in r4. */
146 2: stfs fr0,0(r4)
159 /* Store FP reg N to double at *p. N is in r3, p in r4. */
173 2: stfd fr0,0(r4)
225 /* Load vector reg N from *p. N is in r3, p in r4. */
239 2: lvx v0,0,r4
253 /* Store vector reg N to *p. N is in r3, p in r4. */
268 2: stvx v0,0,r4
321 /* Load VSX reg N from vector doubleword *p. N is in r3, p in r4. */
349 /* Store VSX reg N to vector doubleword *p. N is in r3, p in r4. */
/linux-4.1.27/tools/testing/selftests/powerpc/copyloops/
H A Dcopyuser_power7.S89 ld r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
100 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
109 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
117 neg r6,r4
122 err1; lbz r0,0(r4)
123 addi r4,r4,1
128 err1; lhz r0,0(r4)
129 addi r4,r4,2
134 err1; lwz r0,0(r4)
135 addi r4,r4,4
162 err2; ld r0,0(r4)
163 err2; ld r6,8(r4)
164 err2; ld r7,16(r4)
165 err2; ld r8,24(r4)
166 err2; ld r9,32(r4)
167 err2; ld r10,40(r4)
168 err2; ld r11,48(r4)
169 err2; ld r12,56(r4)
170 err2; ld r14,64(r4)
171 err2; ld r15,72(r4)
172 err2; ld r16,80(r4)
173 err2; ld r17,88(r4)
174 err2; ld r18,96(r4)
175 err2; ld r19,104(r4)
176 err2; ld r20,112(r4)
177 err2; ld r21,120(r4)
178 addi r4,r4,128
216 err1; ld r0,0(r4)
217 err1; ld r6,8(r4)
218 err1; ld r7,16(r4)
219 err1; ld r8,24(r4)
220 err1; ld r9,32(r4)
221 err1; ld r10,40(r4)
222 err1; ld r11,48(r4)
223 err1; ld r12,56(r4)
224 addi r4,r4,64
237 err1; ld r0,0(r4)
238 err1; ld r6,8(r4)
239 err1; ld r7,16(r4)
240 err1; ld r8,24(r4)
241 addi r4,r4,32
250 err1; ld r0,0(r4)
251 err1; ld r6,8(r4)
252 addi r4,r4,16
263 err1; lwz r0,0(r4) /* Less chance of a reject with word ops */
264 err1; lwz r6,4(r4)
265 addi r4,r4,8
271 err1; lwz r0,0(r4)
272 addi r4,r4,4
277 err1; lhz r0,0(r4)
278 addi r4,r4,2
283 err1; lbz r0,0(r4)
302 ld r4,STK_REG(R30)(r1)
311 clrrdi r6,r4,7
345 xor r6,r4,r3
355 err3; lbz r0,0(r4)
356 addi r4,r4,1
361 err3; lhz r0,0(r4)
362 addi r4,r4,2
367 err3; lwz r0,0(r4)
368 addi r4,r4,4
373 err3; ld r0,0(r4)
374 addi r4,r4,8
391 err3; lvx v1,r0,r4
392 addi r4,r4,16
397 err3; lvx v1,r0,r4
398 err3; lvx v0,r4,r9
399 addi r4,r4,32
405 err3; lvx v3,r0,r4
406 err3; lvx v2,r4,r9
407 err3; lvx v1,r4,r10
408 err3; lvx v0,r4,r11
409 addi r4,r4,64
436 err4; lvx v7,r0,r4
437 err4; lvx v6,r4,r9
438 err4; lvx v5,r4,r10
439 err4; lvx v4,r4,r11
440 err4; lvx v3,r4,r12
441 err4; lvx v2,r4,r14
442 err4; lvx v1,r4,r15
443 err4; lvx v0,r4,r16
444 addi r4,r4,128
466 err3; lvx v3,r0,r4
467 err3; lvx v2,r4,r9
468 err3; lvx v1,r4,r10
469 err3; lvx v0,r4,r11
470 addi r4,r4,64
478 err3; lvx v1,r0,r4
479 err3; lvx v0,r4,r9
480 addi r4,r4,32
486 err3; lvx v1,r0,r4
487 addi r4,r4,16
495 err3; ld r0,0(r4)
496 addi r4,r4,8
501 err3; lwz r0,0(r4)
502 addi r4,r4,4
507 err3; lhz r0,0(r4)
508 addi r4,r4,2
513 err3; lbz r0,0(r4)
526 err3; lbz r0,0(r4)
527 addi r4,r4,1
532 err3; lhz r0,0(r4)
533 addi r4,r4,2
538 err3; lwz r0,0(r4)
539 addi r4,r4,4
544 err3; lwz r0,0(r4) /* Less chance of a reject with word ops */
545 err3; lwz r7,4(r4)
546 addi r4,r4,8
563 LVS(v16,0,r4) /* Setup permute control vector */
564 err3; lvx v0,0,r4
565 addi r4,r4,16
568 err3; lvx v1,r0,r4
570 addi r4,r4,16
576 err3; lvx v1,r0,r4
578 err3; lvx v0,r4,r9
580 addi r4,r4,32
586 err3; lvx v3,r0,r4
588 err3; lvx v2,r4,r9
590 err3; lvx v1,r4,r10
592 err3; lvx v0,r4,r11
594 addi r4,r4,64
621 err4; lvx v7,r0,r4
623 err4; lvx v6,r4,r9
625 err4; lvx v5,r4,r10
627 err4; lvx v4,r4,r11
629 err4; lvx v3,r4,r12
631 err4; lvx v2,r4,r14
633 err4; lvx v1,r4,r15
635 err4; lvx v0,r4,r16
637 addi r4,r4,128
659 err3; lvx v3,r0,r4
661 err3; lvx v2,r4,r9
663 err3; lvx v1,r4,r10
665 err3; lvx v0,r4,r11
667 addi r4,r4,64
675 err3; lvx v1,r0,r4
677 err3; lvx v0,r4,r9
679 addi r4,r4,32
685 err3; lvx v1,r0,r4
687 addi r4,r4,16
693 addi r4,r4,-16 /* Unwind the +16 load offset */
696 err3; lwz r0,0(r4) /* Less chance of a reject with word ops */
697 err3; lwz r6,4(r4)
698 addi r4,r4,8
704 err3; lwz r0,0(r4)
705 addi r4,r4,4
710 err3; lhz r0,0(r4)
711 addi r4,r4,2
716 err3; lbz r0,0(r4)
H A Dmemcpy_power7.S50 neg r6,r4
55 lbz r0,0(r4)
56 addi r4,r4,1
61 lhz r0,0(r4)
62 addi r4,r4,2
67 lwz r0,0(r4)
68 addi r4,r4,4
95 ld r0,0(r4)
96 ld r6,8(r4)
97 ld r7,16(r4)
98 ld r8,24(r4)
99 ld r9,32(r4)
100 ld r10,40(r4)
101 ld r11,48(r4)
102 ld r12,56(r4)
103 ld r14,64(r4)
104 ld r15,72(r4)
105 ld r16,80(r4)
106 ld r17,88(r4)
107 ld r18,96(r4)
108 ld r19,104(r4)
109 ld r20,112(r4)
110 ld r21,120(r4)
111 addi r4,r4,128
149 ld r0,0(r4)
150 ld r6,8(r4)
151 ld r7,16(r4)
152 ld r8,24(r4)
153 ld r9,32(r4)
154 ld r10,40(r4)
155 ld r11,48(r4)
156 ld r12,56(r4)
157 addi r4,r4,64
170 ld r0,0(r4)
171 ld r6,8(r4)
172 ld r7,16(r4)
173 ld r8,24(r4)
174 addi r4,r4,32
183 ld r0,0(r4)
184 ld r6,8(r4)
185 addi r4,r4,16
196 lwz r0,0(r4) /* Less chance of a reject with word ops */
197 lwz r6,4(r4)
198 addi r4,r4,8
204 lwz r0,0(r4)
205 addi r4,r4,4
210 lhz r0,0(r4)
211 addi r4,r4,2
216 lbz r0,0(r4)
229 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
237 ld r4,STK_REG(R30)(r1)
246 clrrdi r6,r4,7
278 xor r6,r4,r3
288 lbz r0,0(r4)
289 addi r4,r4,1
294 lhz r0,0(r4)
295 addi r4,r4,2
300 lwz r0,0(r4)
301 addi r4,r4,4
306 ld r0,0(r4)
307 addi r4,r4,8
324 lvx v1,r0,r4
325 addi r4,r4,16
330 lvx v1,r0,r4
331 lvx v0,r4,r9
332 addi r4,r4,32
338 lvx v3,r0,r4
339 lvx v2,r4,r9
340 lvx v1,r4,r10
341 lvx v0,r4,r11
342 addi r4,r4,64
369 lvx v7,r0,r4
370 lvx v6,r4,r9
371 lvx v5,r4,r10
372 lvx v4,r4,r11
373 lvx v3,r4,r12
374 lvx v2,r4,r14
375 lvx v1,r4,r15
376 lvx v0,r4,r16
377 addi r4,r4,128
399 lvx v3,r0,r4
400 lvx v2,r4,r9
401 lvx v1,r4,r10
402 lvx v0,r4,r11
403 addi r4,r4,64
411 lvx v1,r0,r4
412 lvx v0,r4,r9
413 addi r4,r4,32
419 lvx v1,r0,r4
420 addi r4,r4,16
428 ld r0,0(r4)
429 addi r4,r4,8
434 lwz r0,0(r4)
435 addi r4,r4,4
440 lhz r0,0(r4)
441 addi r4,r4,2
446 lbz r0,0(r4)
460 lbz r0,0(r4)
461 addi r4,r4,1
466 lhz r0,0(r4)
467 addi r4,r4,2
472 lwz r0,0(r4)
473 addi r4,r4,4
478 lwz r0,0(r4) /* Less chance of a reject with word ops */
479 lwz r7,4(r4)
480 addi r4,r4,8
497 LVS(v16,0,r4) /* Setup permute control vector */
498 lvx v0,0,r4
499 addi r4,r4,16
502 lvx v1,r0,r4
504 addi r4,r4,16
510 lvx v1,r0,r4
512 lvx v0,r4,r9
514 addi r4,r4,32
520 lvx v3,r0,r4
522 lvx v2,r4,r9
524 lvx v1,r4,r10
526 lvx v0,r4,r11
528 addi r4,r4,64
555 lvx v7,r0,r4
557 lvx v6,r4,r9
559 lvx v5,r4,r10
561 lvx v4,r4,r11
563 lvx v3,r4,r12
565 lvx v2,r4,r14
567 lvx v1,r4,r15
569 lvx v0,r4,r16
571 addi r4,r4,128
593 lvx v3,r0,r4
595 lvx v2,r4,r9
597 lvx v1,r4,r10
599 lvx v0,r4,r11
601 addi r4,r4,64
609 lvx v1,r0,r4
611 lvx v0,r4,r9
613 addi r4,r4,32
619 lvx v1,r0,r4
621 addi r4,r4,16
627 addi r4,r4,-16 /* Unwind the +16 load offset */
630 lwz r0,0(r4) /* Less chance of a reject with word ops */
631 lwz r6,4(r4)
632 addi r4,r4,8
638 lwz r0,0(r4)
639 addi r4,r4,4
644 lhz r0,0(r4)
645 addi r4,r4,2
650 lbz r0,0(r4)
H A Dmemcpy_64.S28 addi r4,r4,-1
31 1: lbzu r10,1(r4)
40 dcbt 0,r4
56 andi. r0,r4,7
60 ld r9,0(r4)
61 addi r4,r4,-8
66 addi r4,r4,8
69 1: ld r9,8(r4)
71 2: ldu r8,16(r4)
79 lwz r9,8(r4)
80 addi r4,r4,4
84 lhz r9,8(r4)
85 addi r4,r4,2
89 lbz r9,8(r4)
97 subf r4,r0,r4
108 ld r9,0(r4) # 3+2n loads, 2+2n stores
109 ld r0,8(r4)
111 ldu r9,16(r4)
116 ld r0,8(r4)
120 0: ld r0,0(r4) # 4+2n loads, 3+2n stores
121 ldu r9,8(r4)
125 ld r0,8(r4)
128 ldu r9,16(r4)
137 ld r0,8(r4)
141 ldu r9,16(r4)
159 ld r0,8(r4)
183 lbz r0,0(r4)
187 lhzx r0,r7,r4
191 lwzx r0,r7,r4
194 add r4,r6,r4
200 lwz r0,0(r4)
201 lwz r9,4(r4)
202 addi r4,r4,8
207 lwz r0,0(r4)
208 addi r4,r4,4
212 lhz r0,0(r4)
213 addi r4,r4,2
217 lbz r0,0(r4)
H A Dcopyuser_64.S31 or r0,r3,r4
36 std r4,-16(r1)
38 dcbt 0,r4
58 andi. r0,r4,7
64 20: ld r7,0(r4)
65 220: ld r6,8(r4)
66 addi r4,r4,16
71 addi r4,r4,-16
75 21: ld r7,16(r4)
76 221: ld r6,24(r4)
77 addi r4,r4,32
80 22: ld r9,0(r4)
81 222: ld r8,8(r4)
90 addi r4,r4,16
94 244: ld r9,0(r4)
95 addi r4,r4,8
99 23: lwz r9,0(r4)
100 addi r4,r4,4
104 44: lhz r9,0(r4)
105 addi r4,r4,2
109 45: lbz r9,0(r4)
117 subf r4,r0,r4
127 24: ld r9,0(r4) /* 3+2n loads, 2+2n stores */
128 25: ld r0,8(r4)
130 26: ldu r9,16(r4)
135 27: ld r0,8(r4)
138 28: ld r0,0(r4) /* 4+2n loads, 3+2n stores */
139 29: ldu r9,8(r4)
143 30: ld r0,8(r4)
146 31: ldu r9,16(r4)
154 32: ld r0,8(r4)
158 33: ldu r9,16(r4)
178 34: ld r0,8(r4)
217 35: lbz r0,0(r4)
221 36: lhzx r0,r7,r4
225 37: lwzx r0,r7,r4
228 add r4,r6,r4
234 38: lwz r0,0(r4)
235 39: lwz r9,4(r4)
236 addi r4,r4,8
241 40: lwz r0,0(r4)
242 addi r4,r4,4
246 41: lhz r0,0(r4)
247 addi r4,r4,2
251 42: lbz r0,0(r4)
302 ld r4,-16(r1)
305 add r4,r4,r6
312 43: lbz r0,0(r4)
313 addi r4,r4,1
325 mr r4,r3
327 1: andi. r9,r4,7
329 90: stb r0,0(r4)
331 addi r4,r4,1
339 91: std r0,0(r4)
340 addi r4,r4,8
344 92: stb r0,0(r4)
345 addi r4,r4,1
541 74: addi r4,r4,640
596 ld r4,-16(r1)
/linux-4.1.27/crypto/
H A Dserpent_generic.c237 u32 r0, r1, r2, r3, r4; __serpent_setkey() local
255 r4 = le32_to_cpu(k[7]); __serpent_setkey()
257 keyiter(le32_to_cpu(k[0]), r0, r4, r2, 0, 0); __serpent_setkey() local
259 keyiter(le32_to_cpu(k[2]), r2, r1, r4, 2, 2); __serpent_setkey() local
261 keyiter(le32_to_cpu(k[4]), r4, r3, r1, 4, 4); __serpent_setkey() local
262 keyiter(le32_to_cpu(k[5]), r0, r4, r2, 5, 5); __serpent_setkey() local
264 keyiter(le32_to_cpu(k[7]), r2, r1, r4, 7, 7); __serpent_setkey() local
267 keyiter(k[1], r4, r3, r1, 9, 9); __serpent_setkey()
268 keyiter(k[2], r0, r4, r2, 10, 10); __serpent_setkey()
270 keyiter(k[4], r2, r1, r4, 12, 12); __serpent_setkey()
272 keyiter(k[6], r4, r3, r1, 14, 14); __serpent_setkey()
273 keyiter(k[7], r0, r4, r2, 15, 15); __serpent_setkey()
275 keyiter(k[9], r2, r1, r4, 17, 17); __serpent_setkey()
277 keyiter(k[11], r4, r3, r1, 19, 19); __serpent_setkey()
278 keyiter(k[12], r0, r4, r2, 20, 20); __serpent_setkey()
280 keyiter(k[14], r2, r1, r4, 22, 22); __serpent_setkey()
282 keyiter(k[16], r4, r3, r1, 24, 24); __serpent_setkey()
283 keyiter(k[17], r0, r4, r2, 25, 25); __serpent_setkey()
285 keyiter(k[19], r2, r1, r4, 27, 27); __serpent_setkey()
287 keyiter(k[21], r4, r3, r1, 29, 29); __serpent_setkey()
288 keyiter(k[22], r0, r4, r2, 30, 30); __serpent_setkey()
293 keyiter(k[-26], r2, r1, r4, 32, -18); __serpent_setkey()
295 keyiter(k[-24], r4, r3, r1, 34, -16); __serpent_setkey()
296 keyiter(k[-23], r0, r4, r2, 35, -15); __serpent_setkey()
298 keyiter(k[-21], r2, r1, r4, 37, -13); __serpent_setkey()
300 keyiter(k[-19], r4, r3, r1, 39, -11); __serpent_setkey()
301 keyiter(k[-18], r0, r4, r2, 40, -10); __serpent_setkey()
303 keyiter(k[-16], r2, r1, r4, 42, -8); __serpent_setkey()
305 keyiter(k[-14], r4, r3, r1, 44, -6); __serpent_setkey()
306 keyiter(k[-13], r0, r4, r2, 45, -5); __serpent_setkey()
308 keyiter(k[-11], r2, r1, r4, 47, -3); __serpent_setkey()
310 keyiter(k[-9], r4, r3, r1, 49, -1); __serpent_setkey()
311 keyiter(k[-8], r0, r4, r2, 50, 0); __serpent_setkey()
313 keyiter(k[-6], r2, r1, r4, 52, 2); __serpent_setkey()
315 keyiter(k[-4], r4, r3, r1, 54, 4); __serpent_setkey()
316 keyiter(k[-3], r0, r4, r2, 55, 5); __serpent_setkey()
318 keyiter(k[-1], r2, r1, r4, 57, 7); __serpent_setkey()
320 keyiter(k[1], r4, r3, r1, 59, 9); __serpent_setkey()
321 keyiter(k[2], r0, r4, r2, 60, 10); __serpent_setkey()
323 keyiter(k[4], r2, r1, r4, 62, 12); __serpent_setkey()
325 keyiter(k[6], r4, r3, r1, 64, 14); __serpent_setkey()
326 keyiter(k[7], r0, r4, r2, 65, 15); __serpent_setkey()
328 keyiter(k[9], r2, r1, r4, 67, 17); __serpent_setkey()
330 keyiter(k[11], r4, r3, r1, 69, 19); __serpent_setkey()
331 keyiter(k[12], r0, r4, r2, 70, 20); __serpent_setkey()
333 keyiter(k[14], r2, r1, r4, 72, 22); __serpent_setkey()
335 keyiter(k[16], r4, r3, r1, 74, 24); __serpent_setkey()
336 keyiter(k[17], r0, r4, r2, 75, 25); __serpent_setkey()
338 keyiter(k[19], r2, r1, r4, 77, 27); __serpent_setkey()
340 keyiter(k[21], r4, r3, r1, 79, 29); __serpent_setkey()
341 keyiter(k[22], r0, r4, r2, 80, 30); __serpent_setkey()
346 keyiter(k[-26], r2, r1, r4, 82, -18); __serpent_setkey()
348 keyiter(k[-24], r4, r3, r1, 84, -16); __serpent_setkey()
349 keyiter(k[-23], r0, r4, r2, 85, -15); __serpent_setkey()
351 keyiter(k[-21], r2, r1, r4, 87, -13); __serpent_setkey()
353 keyiter(k[-19], r4, r3, r1, 89, -11); __serpent_setkey()
354 keyiter(k[-18], r0, r4, r2, 90, -10); __serpent_setkey()
356 keyiter(k[-16], r2, r1, r4, 92, -8); __serpent_setkey()
358 keyiter(k[-14], r4, r3, r1, 94, -6); __serpent_setkey()
359 keyiter(k[-13], r0, r4, r2, 95, -5); __serpent_setkey()
361 keyiter(k[-11], r2, r1, r4, 97, -3); __serpent_setkey()
363 keyiter(k[-9], r4, r3, r1, 99, -1); __serpent_setkey()
364 keyiter(k[-8], r0, r4, r2, 100, 0); __serpent_setkey()
366 keyiter(k[-6], r2, r1, r4, 102, 2); __serpent_setkey()
368 keyiter(k[-4], r4, r3, r1, 104, 4); __serpent_setkey()
369 keyiter(k[-3], r0, r4, r2, 105, 5); __serpent_setkey()
371 keyiter(k[-1], r2, r1, r4, 107, 7); __serpent_setkey()
373 keyiter(k[1], r4, r3, r1, 109, 9); __serpent_setkey()
374 keyiter(k[2], r0, r4, r2, 110, 10); __serpent_setkey()
376 keyiter(k[4], r2, r1, r4, 112, 12); __serpent_setkey()
378 keyiter(k[6], r4, r3, r1, 114, 14); __serpent_setkey()
379 keyiter(k[7], r0, r4, r2, 115, 15); __serpent_setkey()
381 keyiter(k[9], r2, r1, r4, 117, 17); __serpent_setkey()
383 keyiter(k[11], r4, r3, r1, 119, 19); __serpent_setkey()
384 keyiter(k[12], r0, r4, r2, 120, 20); __serpent_setkey()
386 keyiter(k[14], r2, r1, r4, 122, 22); __serpent_setkey()
388 keyiter(k[16], r4, r3, r1, 124, 24); __serpent_setkey()
389 keyiter(k[17], r0, r4, r2, 125, 25); __serpent_setkey()
391 keyiter(k[19], r2, r1, r4, 127, 27); __serpent_setkey()
393 keyiter(k[21], r4, r3, r1, 129, 29); __serpent_setkey()
394 keyiter(k[22], r0, r4, r2, 130, 30); __serpent_setkey()
399 S3(r3, r4, r0, r1, r2); store_and_load_keys(r1, r2, r4, r3, 28, 24); __serpent_setkey()
400 S4(r1, r2, r4, r3, r0); store_and_load_keys(r2, r4, r3, r0, 24, 20); __serpent_setkey()
401 S5(r2, r4, r3, r0, r1); store_and_load_keys(r1, r2, r4, r0, 20, 16); __serpent_setkey()
402 S6(r1, r2, r4, r0, r3); store_and_load_keys(r4, r3, r2, r0, 16, 12); __serpent_setkey()
403 S7(r4, r3, r2, r0, r1); store_and_load_keys(r1, r2, r0, r4, 12, 8); __serpent_setkey()
404 S0(r1, r2, r0, r4, r3); store_and_load_keys(r0, r2, r4, r1, 8, 4); __serpent_setkey()
405 S1(r0, r2, r4, r1, r3); store_and_load_keys(r3, r4, r1, r0, 4, 0); __serpent_setkey()
406 S2(r3, r4, r1, r0, r2); store_and_load_keys(r2, r4, r3, r0, 0, -4); __serpent_setkey()
407 S3(r2, r4, r3, r0, r1); store_and_load_keys(r0, r1, r4, r2, -4, -8); __serpent_setkey()
408 S4(r0, r1, r4, r2, r3); store_and_load_keys(r1, r4, r2, r3, -8, -12); __serpent_setkey()
409 S5(r1, r4, r2, r3, r0); store_and_load_keys(r0, r1, r4, r3, -12, -16); __serpent_setkey()
410 S6(r0, r1, r4, r3, r2); store_and_load_keys(r4, r2, r1, r3, -16, -20); __serpent_setkey()
411 S7(r4, r2, r1, r3, r0); store_and_load_keys(r0, r1, r3, r4, -20, -24); __serpent_setkey()
412 S0(r0, r1, r3, r4, r2); store_and_load_keys(r3, r1, r4, r0, -24, -28); __serpent_setkey()
414 S1(r3, r1, r4, r0, r2); store_and_load_keys(r2, r4, r0, r3, 22, 18); __serpent_setkey()
415 S2(r2, r4, r0, r3, r1); store_and_load_keys(r1, r4, r2, r3, 18, 14); __serpent_setkey()
416 S3(r1, r4, r2, r3, r0); store_and_load_keys(r3, r0, r4, r1, 14, 10); __serpent_setkey()
417 S4(r3, r0, r4, r1, r2); store_and_load_keys(r0, r4, r1, r2, 10, 6); __serpent_setkey()
418 S5(r0, r4, r1, r2, r3); store_and_load_keys(r3, r0, r4, r2, 6, 2); __serpent_setkey()
419 S6(r3, r0, r4, r2, r1); store_and_load_keys(r4, r1, r0, r2, 2, -2); __serpent_setkey()
420 S7(r4, r1, r0, r2, r3); store_and_load_keys(r3, r0, r2, r4, -2, -6); __serpent_setkey()
421 S0(r3, r0, r2, r4, r1); store_and_load_keys(r2, r0, r4, r3, -6, -10); __serpent_setkey()
422 S1(r2, r0, r4, r3, r1); store_and_load_keys(r1, r4, r3, r2, -10, -14); __serpent_setkey()
423 S2(r1, r4, r3, r2, r0); store_and_load_keys(r0, r4, r1, r2, -14, -18); __serpent_setkey()
424 S3(r0, r4, r1, r2, r3); store_and_load_keys(r2, r3, r4, r0, -18, -22); __serpent_setkey()
426 S4(r2, r3, r4, r0, r1); store_and_load_keys(r3, r4, r0, r1, 28, 24); __serpent_setkey()
427 S5(r3, r4, r0, r1, r2); store_and_load_keys(r2, r3, r4, r1, 24, 20); __serpent_setkey()
428 S6(r2, r3, r4, r1, r0); store_and_load_keys(r4, r0, r3, r1, 20, 16); __serpent_setkey()
429 S7(r4, r0, r3, r1, r2); store_and_load_keys(r2, r3, r1, r4, 16, 12); __serpent_setkey()
430 S0(r2, r3, r1, r4, r0); store_and_load_keys(r1, r3, r4, r2, 12, 8); __serpent_setkey()
431 S1(r1, r3, r4, r2, r0); store_and_load_keys(r0, r4, r2, r1, 8, 4); __serpent_setkey()
432 S2(r0, r4, r2, r1, r3); store_and_load_keys(r3, r4, r0, r1, 4, 0); __serpent_setkey()
433 S3(r3, r4, r0, r1, r2); storekeys(r1, r2, r4, r3, 0); __serpent_setkey()
450 u32 r0, r1, r2, r3, r4; __serpent_encrypt() local
463 S0(r0, r1, r2, r3, r4); LK(r2, r1, r3, r0, r4, 1); __serpent_encrypt()
464 S1(r2, r1, r3, r0, r4); LK(r4, r3, r0, r2, r1, 2); __serpent_encrypt()
465 S2(r4, r3, r0, r2, r1); LK(r1, r3, r4, r2, r0, 3); __serpent_encrypt()
466 S3(r1, r3, r4, r2, r0); LK(r2, r0, r3, r1, r4, 4); __serpent_encrypt()
467 S4(r2, r0, r3, r1, r4); LK(r0, r3, r1, r4, r2, 5); __serpent_encrypt()
468 S5(r0, r3, r1, r4, r2); LK(r2, r0, r3, r4, r1, 6); __serpent_encrypt()
469 S6(r2, r0, r3, r4, r1); LK(r3, r1, r0, r4, r2, 7); __serpent_encrypt()
470 S7(r3, r1, r0, r4, r2); LK(r2, r0, r4, r3, r1, 8); __serpent_encrypt()
471 S0(r2, r0, r4, r3, r1); LK(r4, r0, r3, r2, r1, 9); __serpent_encrypt()
472 S1(r4, r0, r3, r2, r1); LK(r1, r3, r2, r4, r0, 10); __serpent_encrypt()
473 S2(r1, r3, r2, r4, r0); LK(r0, r3, r1, r4, r2, 11); __serpent_encrypt()
474 S3(r0, r3, r1, r4, r2); LK(r4, r2, r3, r0, r1, 12); __serpent_encrypt()
475 S4(r4, r2, r3, r0, r1); LK(r2, r3, r0, r1, r4, 13); __serpent_encrypt()
476 S5(r2, r3, r0, r1, r4); LK(r4, r2, r3, r1, r0, 14); __serpent_encrypt()
477 S6(r4, r2, r3, r1, r0); LK(r3, r0, r2, r1, r4, 15); __serpent_encrypt()
478 S7(r3, r0, r2, r1, r4); LK(r4, r2, r1, r3, r0, 16); __serpent_encrypt()
479 S0(r4, r2, r1, r3, r0); LK(r1, r2, r3, r4, r0, 17); __serpent_encrypt()
480 S1(r1, r2, r3, r4, r0); LK(r0, r3, r4, r1, r2, 18); __serpent_encrypt()
481 S2(r0, r3, r4, r1, r2); LK(r2, r3, r0, r1, r4, 19); __serpent_encrypt()
482 S3(r2, r3, r0, r1, r4); LK(r1, r4, r3, r2, r0, 20); __serpent_encrypt()
483 S4(r1, r4, r3, r2, r0); LK(r4, r3, r2, r0, r1, 21); __serpent_encrypt()
484 S5(r4, r3, r2, r0, r1); LK(r1, r4, r3, r0, r2, 22); __serpent_encrypt()
485 S6(r1, r4, r3, r0, r2); LK(r3, r2, r4, r0, r1, 23); __serpent_encrypt()
486 S7(r3, r2, r4, r0, r1); LK(r1, r4, r0, r3, r2, 24); __serpent_encrypt()
487 S0(r1, r4, r0, r3, r2); LK(r0, r4, r3, r1, r2, 25); __serpent_encrypt()
488 S1(r0, r4, r3, r1, r2); LK(r2, r3, r1, r0, r4, 26); __serpent_encrypt()
489 S2(r2, r3, r1, r0, r4); LK(r4, r3, r2, r0, r1, 27); __serpent_encrypt()
490 S3(r4, r3, r2, r0, r1); LK(r0, r1, r3, r4, r2, 28); __serpent_encrypt()
491 S4(r0, r1, r3, r4, r2); LK(r1, r3, r4, r2, r0, 29); __serpent_encrypt()
492 S5(r1, r3, r4, r2, r0); LK(r0, r1, r3, r2, r4, 30); __serpent_encrypt()
493 S6(r0, r1, r3, r2, r4); LK(r3, r4, r1, r2, r0, 31); __serpent_encrypt()
494 S7(r3, r4, r1, r2, r0); K(r0, r1, r2, r3, 32); __serpent_encrypt()
515 u32 r0, r1, r2, r3, r4; __serpent_decrypt() local
523 SI7(r0, r1, r2, r3, r4); KL(r1, r3, r0, r4, r2, 31); __serpent_decrypt()
524 SI6(r1, r3, r0, r4, r2); KL(r0, r2, r4, r1, r3, 30); __serpent_decrypt()
525 SI5(r0, r2, r4, r1, r3); KL(r2, r3, r0, r4, r1, 29); __serpent_decrypt()
526 SI4(r2, r3, r0, r4, r1); KL(r2, r0, r1, r4, r3, 28); __serpent_decrypt()
527 SI3(r2, r0, r1, r4, r3); KL(r1, r2, r3, r4, r0, 27); __serpent_decrypt()
528 SI2(r1, r2, r3, r4, r0); KL(r2, r0, r4, r3, r1, 26); __serpent_decrypt()
529 SI1(r2, r0, r4, r3, r1); KL(r1, r0, r4, r3, r2, 25); __serpent_decrypt()
530 SI0(r1, r0, r4, r3, r2); KL(r4, r2, r0, r1, r3, 24); __serpent_decrypt()
531 SI7(r4, r2, r0, r1, r3); KL(r2, r1, r4, r3, r0, 23); __serpent_decrypt()
532 SI6(r2, r1, r4, r3, r0); KL(r4, r0, r3, r2, r1, 22); __serpent_decrypt()
533 SI5(r4, r0, r3, r2, r1); KL(r0, r1, r4, r3, r2, 21); __serpent_decrypt()
534 SI4(r0, r1, r4, r3, r2); KL(r0, r4, r2, r3, r1, 20); __serpent_decrypt()
535 SI3(r0, r4, r2, r3, r1); KL(r2, r0, r1, r3, r4, 19); __serpent_decrypt()
536 SI2(r2, r0, r1, r3, r4); KL(r0, r4, r3, r1, r2, 18); __serpent_decrypt()
537 SI1(r0, r4, r3, r1, r2); KL(r2, r4, r3, r1, r0, 17); __serpent_decrypt()
538 SI0(r2, r4, r3, r1, r0); KL(r3, r0, r4, r2, r1, 16); __serpent_decrypt()
539 SI7(r3, r0, r4, r2, r1); KL(r0, r2, r3, r1, r4, 15); __serpent_decrypt()
540 SI6(r0, r2, r3, r1, r4); KL(r3, r4, r1, r0, r2, 14); __serpent_decrypt()
541 SI5(r3, r4, r1, r0, r2); KL(r4, r2, r3, r1, r0, 13); __serpent_decrypt()
542 SI4(r4, r2, r3, r1, r0); KL(r4, r3, r0, r1, r2, 12); __serpent_decrypt()
543 SI3(r4, r3, r0, r1, r2); KL(r0, r4, r2, r1, r3, 11); __serpent_decrypt()
544 SI2(r0, r4, r2, r1, r3); KL(r4, r3, r1, r2, r0, 10); __serpent_decrypt()
545 SI1(r4, r3, r1, r2, r0); KL(r0, r3, r1, r2, r4, 9); __serpent_decrypt()
546 SI0(r0, r3, r1, r2, r4); KL(r1, r4, r3, r0, r2, 8); __serpent_decrypt()
547 SI7(r1, r4, r3, r0, r2); KL(r4, r0, r1, r2, r3, 7); __serpent_decrypt()
548 SI6(r4, r0, r1, r2, r3); KL(r1, r3, r2, r4, r0, 6); __serpent_decrypt()
549 SI5(r1, r3, r2, r4, r0); KL(r3, r0, r1, r2, r4, 5); __serpent_decrypt()
550 SI4(r3, r0, r1, r2, r4); KL(r3, r1, r4, r2, r0, 4); __serpent_decrypt()
551 SI3(r3, r1, r4, r2, r0); KL(r4, r3, r0, r2, r1, 3); __serpent_decrypt()
552 SI2(r4, r3, r0, r2, r1); KL(r3, r1, r2, r0, r4, 2); __serpent_decrypt()
553 SI1(r3, r1, r2, r0, r4); KL(r4, r1, r2, r0, r3, 1); __serpent_decrypt()
554 SI0(r4, r1, r2, r0, r3); K(r2, r3, r1, r4, 0); __serpent_decrypt()
559 d[3] = cpu_to_le32(r4); __serpent_decrypt()
/linux-4.1.27/arch/powerpc/platforms/83xx/
H A Dsuspend-asm.S50 lis r4, immrbase@ha
51 stw r3, immrbase@l(r4)
65 lis r4, KERNELBASE@h
66 lwz r5, 0(r4)
67 lwz r6, 4(r4)
80 mfspr r4, SPRN_IABR
87 stw r4, SS_IABR+0(r3)
94 mfspr r4, SPRN_SPRG0
100 stw r4, SS_SPRG+0(r3)
106 mfspr r4, SPRN_DBAT0U
111 stw r4, SS_DBAT+0x00(r3)
116 mfspr r4, SPRN_DBAT2U
121 stw r4, SS_DBAT+0x10(r3)
126 mfspr r4, SPRN_DBAT4U
131 stw r4, SS_DBAT+0x20(r3)
136 mfspr r4, SPRN_DBAT6U
141 stw r4, SS_DBAT+0x30(r3)
146 mfspr r4, SPRN_IBAT0U
151 stw r4, SS_IBAT+0x00(r3)
156 mfspr r4, SPRN_IBAT2U
161 stw r4, SS_IBAT+0x10(r3)
166 mfspr r4, SPRN_IBAT4U
171 stw r4, SS_IBAT+0x20(r3)
176 mfspr r4, SPRN_IBAT6U
181 stw r4, SS_IBAT+0x30(r3)
186 mfmsr r4
190 stw r4, SS_MSR(r3)
196 1: mftbu r4
199 cmpw r4, r6
202 stw r4, SS_TB+0(r3)
207 li r4, 0
209 1: mfsrin r5, r4
211 addis r4, r4, 0x1000
212 cmpwi r4, 0
216 mfmsr r4
217 rlwinm r4, r4, 0, ~MSR_CE
218 rlwinm r4, r4, 0, ~MSR_ME
219 mtmsr r4
226 lis r4, immrbase@ha
227 lwz r4, immrbase@l(r4)
231 ori r4, r4, 0x002a
232 mtspr SPRN_DBAT0L, r4
234 ori r4, r8, 0x001e /* 1 MByte accessible from Kernel Space only */
235 mtspr SPRN_DBAT0U, r4
240 lis r4, DEFAULT_IMMR_VALUE@h
241 ori r4, r4, 0x002a
242 mtspr SPRN_DBAT1L, r4
244 ori r4, r9, 0x001e /* 1 MByte accessible from Kernel Space only */
245 mtspr SPRN_DBAT1U, r4
253 li r4, 0x0002
254 mtspr SPRN_DBAT2L, r4
255 lis r4, KERNELBASE@h
256 ori r4, r4, 0x001e /* 1 MByte accessible from Kernel Space only */
257 mtspr SPRN_DBAT2U, r4
288 li r4, 0
289 stw r4, 0x0024(r8)
290 stw r4, 0x002c(r8)
291 stw r4, 0x0034(r8)
292 stw r4, 0x003c(r8)
293 stw r4, 0x0064(r8)
294 stw r4, 0x006c(r8)
312 lwz r4, IMMRBAR_BASE(r8)
314 lis r4, DEFAULT_IMMR_VALUE@h
315 stw r4, IMMRBAR_BASE(r8)
316 lis r4, KERNELBASE@h
317 lwz r4, 0(r4)
319 lwz r4, IMMRBAR_BASE(r9)
327 lwz r4, 0x0904(r8)
328 andis. r4, r4, 0x0400
329 li r4, 0
331 lis r4, 0xff80
333 stw r4, 0x0020(r8)
362 lis r4, 1f@h
363 ori r4, r4, 1f@l
364 tophys(r4, r4)
365 mtsrr0 r4
367 mfmsr r4
368 rlwinm r4, r4, 0, ~(MSR_IR | MSR_DR)
369 mtsrr1 r4
394 lwz r4, SS_IABR+0(r3)
401 mtspr SPRN_IABR, r4
408 li r4, 0
411 mtsrin r5, r4
412 addis r4, r4, 0x1000
413 cmpwi r4, 0
416 lwz r4, SS_DBAT+0x00(r3)
421 mtspr SPRN_DBAT0U, r4
426 lwz r4, SS_DBAT+0x10(r3)
431 mtspr SPRN_DBAT2U, r4
436 lwz r4, SS_DBAT+0x20(r3)
441 mtspr SPRN_DBAT4U, r4
446 lwz r4, SS_DBAT+0x30(r3)
451 mtspr SPRN_DBAT6U, r4
456 lwz r4, SS_IBAT+0x00(r3)
461 mtspr SPRN_IBAT0U, r4
466 lwz r4, SS_IBAT+0x10(r3)
471 mtspr SPRN_IBAT2U, r4
476 lwz r4, SS_IBAT+0x20(r3)
481 mtspr SPRN_IBAT4U, r4
486 lwz r4, SS_IBAT+0x30(r3)
491 mtspr SPRN_IBAT6U, r4
496 lwz r4, SS_SPRG+0(r3)
502 mtspr SPRN_SPRG0, r4
508 lwz r4, SS_MSR(r3)
514 mtsrr1 r4
518 li r4, 0
519 mtspr SPRN_TBWL, r4
521 lwz r4, SS_TB+0(r3)
524 mtspr SPRN_TBWU, r4
/linux-4.1.27/arch/powerpc/kvm/
H A Dbooke_interrupts.S58 mtspr \scratch , r4
59 mfspr r4, SPRN_SPRG_THREAD
60 lwz r4, THREAD_KVM_VCPU(r4)
61 stw r3, VCPU_GPR(R3)(r4)
62 stw r5, VCPU_GPR(R5)(r4)
63 stw r6, VCPU_GPR(R6)(r4)
66 stw r3, VCPU_GPR(R4)(r4)
67 stw r5, VCPU_CTR(r4)
70 stw r3, VCPU_PC(r4)
84 mtspr \scratch, r4
85 mfspr r4, SPRN_SPRG_THREAD
86 lwz r4, THREAD_KVM_VCPU(r4)
87 stw r3, VCPU_CRIT_SAVE(r4)
89 mfspr r4, SPRN_CSRR1
90 andi. r4, r4, MSR_PR
93 mfspr r4, SPRN_CSRR1
94 rlwinm r4, r4, 0, ~MSR_DE
95 mtspr SPRN_CSRR1, r4
96 lis r4, 0xffff
97 ori r4, r4, 0xffff
98 mtspr SPRN_DBSR, r4
99 mfspr r4, SPRN_SPRG_THREAD
100 lwz r4, THREAD_KVM_VCPU(r4)
102 lwz r3, VCPU_CRIT_SAVE(r4)
103 mfspr r4, \scratch
107 mfspr r4, SPRN_SPRG_THREAD
108 lwz r4, THREAD_KVM_VCPU(r4)
109 lwz r3, VCPU_CRIT_SAVE(r4)
110 mfspr r4, \scratch
145 * SPRG_SCRATCH0: guest r4
146 * r4: vcpu pointer
151 stw r3, VCPU_CR(r4)
152 stw r7, VCPU_GPR(R7)(r4)
153 stw r8, VCPU_GPR(R8)(r4)
154 stw r9, VCPU_GPR(R9)(r4)
167 stw r8, VCPU_TIMING_EXIT_TBL(r4)
168 stw r9, VCPU_TIMING_EXIT_TBU(r4)
182 stw r9, VCPU_LAST_INST(r4)
184 stw r15, VCPU_GPR(R15)(r4)
185 stw r16, VCPU_GPR(R16)(r4)
186 stw r17, VCPU_GPR(R17)(r4)
187 stw r18, VCPU_GPR(R18)(r4)
188 stw r19, VCPU_GPR(R19)(r4)
189 stw r20, VCPU_GPR(R20)(r4)
190 stw r21, VCPU_GPR(R21)(r4)
191 stw r22, VCPU_GPR(R22)(r4)
192 stw r23, VCPU_GPR(R23)(r4)
193 stw r24, VCPU_GPR(R24)(r4)
194 stw r25, VCPU_GPR(R25)(r4)
195 stw r26, VCPU_GPR(R26)(r4)
196 stw r27, VCPU_GPR(R27)(r4)
197 stw r28, VCPU_GPR(R28)(r4)
198 stw r29, VCPU_GPR(R29)(r4)
199 stw r30, VCPU_GPR(R30)(r4)
200 stw r31, VCPU_GPR(R31)(r4)
208 stw r9, VCPU_FAULT_DEAR(r4)
214 stw r9, VCPU_FAULT_ESR(r4)
218 stw r0, VCPU_GPR(R0)(r4)
219 stw r1, VCPU_GPR(R1)(r4)
220 stw r2, VCPU_GPR(R2)(r4)
221 stw r10, VCPU_GPR(R10)(r4)
222 stw r11, VCPU_GPR(R11)(r4)
223 stw r12, VCPU_GPR(R12)(r4)
224 stw r13, VCPU_GPR(R13)(r4)
225 stw r14, VCPU_GPR(R14)(r4) /* We need a NV GPR below. */
227 stw r3, VCPU_LR(r4)
229 stw r3, VCPU_XER(r4)
233 lwz r1, VCPU_HOST_STACK(r4)
234 lwz r3, VCPU_HOST_PID(r4)
253 mr r14, r4 /* Save vcpu pointer. */
258 mr r4, r14
259 lwz r14, VCPU_GPR(R14)(r4)
264 lwz r15, VCPU_GPR(R15)(r4)
265 lwz r16, VCPU_GPR(R16)(r4)
266 lwz r17, VCPU_GPR(R17)(r4)
267 lwz r18, VCPU_GPR(R18)(r4)
268 lwz r19, VCPU_GPR(R19)(r4)
269 lwz r20, VCPU_GPR(R20)(r4)
270 lwz r21, VCPU_GPR(R21)(r4)
271 lwz r22, VCPU_GPR(R22)(r4)
272 lwz r23, VCPU_GPR(R23)(r4)
273 lwz r24, VCPU_GPR(R24)(r4)
274 lwz r25, VCPU_GPR(R25)(r4)
275 lwz r26, VCPU_GPR(R26)(r4)
276 lwz r27, VCPU_GPR(R27)(r4)
277 lwz r28, VCPU_GPR(R28)(r4)
278 lwz r29, VCPU_GPR(R29)(r4)
279 lwz r30, VCPU_GPR(R30)(r4)
280 lwz r31, VCPU_GPR(R31)(r4)
295 stw r9, VCPU_SPEFSCR(r4)
296 lwz r9, VCPU_HOST_SPEFSCR(r4)
302 stw r15, VCPU_GPR(R15)(r4)
303 stw r16, VCPU_GPR(R16)(r4)
304 stw r17, VCPU_GPR(R17)(r4)
305 stw r18, VCPU_GPR(R18)(r4)
306 stw r19, VCPU_GPR(R19)(r4)
307 stw r20, VCPU_GPR(R20)(r4)
308 stw r21, VCPU_GPR(R21)(r4)
309 stw r22, VCPU_GPR(R22)(r4)
310 stw r23, VCPU_GPR(R23)(r4)
311 stw r24, VCPU_GPR(R24)(r4)
312 stw r25, VCPU_GPR(R25)(r4)
313 stw r26, VCPU_GPR(R26)(r4)
314 stw r27, VCPU_GPR(R27)(r4)
315 stw r28, VCPU_GPR(R28)(r4)
316 stw r29, VCPU_GPR(R29)(r4)
317 stw r30, VCPU_GPR(R30)(r4)
318 stw r31, VCPU_GPR(R31)(r4)
341 lwz r4, HOST_STACK_LR(r1)
344 mtlr r4
352 * r4: vcpu pointer
356 stw r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */
386 lwz r14, VCPU_GPR(R14)(r4)
387 lwz r15, VCPU_GPR(R15)(r4)
388 lwz r16, VCPU_GPR(R16)(r4)
389 lwz r17, VCPU_GPR(R17)(r4)
390 lwz r18, VCPU_GPR(R18)(r4)
391 lwz r19, VCPU_GPR(R19)(r4)
392 lwz r20, VCPU_GPR(R20)(r4)
393 lwz r21, VCPU_GPR(R21)(r4)
394 lwz r22, VCPU_GPR(R22)(r4)
395 lwz r23, VCPU_GPR(R23)(r4)
396 lwz r24, VCPU_GPR(R24)(r4)
397 lwz r25, VCPU_GPR(R25)(r4)
398 lwz r26, VCPU_GPR(R26)(r4)
399 lwz r27, VCPU_GPR(R27)(r4)
400 lwz r28, VCPU_GPR(R28)(r4)
401 lwz r29, VCPU_GPR(R29)(r4)
402 lwz r30, VCPU_GPR(R30)(r4)
403 lwz r31, VCPU_GPR(R31)(r4)
408 stw r3, VCPU_HOST_SPEFSCR(r4)
409 lwz r3, VCPU_SPEFSCR(r4)
417 stw r3, VCPU_HOST_PID(r4)
418 lwz r3, VCPU_SHADOW_PID(r4)
422 lwz r3, VCPU_SHADOW_PID1(r4)
427 lwz r0, VCPU_GPR(R0)(r4)
428 lwz r2, VCPU_GPR(R2)(r4)
429 lwz r9, VCPU_GPR(R9)(r4)
430 lwz r10, VCPU_GPR(R10)(r4)
431 lwz r11, VCPU_GPR(R11)(r4)
432 lwz r12, VCPU_GPR(R12)(r4)
433 lwz r13, VCPU_GPR(R13)(r4)
434 lwz r3, VCPU_LR(r4)
436 lwz r3, VCPU_XER(r4)
445 lwz r5, VCPU_SHARED(r4)
449 lwz r1, VCPU_GPR(R1)(r4)
474 stw r7, VCPU_TIMING_LAST_ENTER_TBL(r4)
475 stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
479 lwz r3, VCPU_CTR(r4)
480 lwz r5, VCPU_CR(r4)
481 lwz r6, VCPU_PC(r4)
482 lwz r7, VCPU_SHADOW_MSR(r4)
487 lwz r5, VCPU_GPR(R5)(r4)
488 lwz r6, VCPU_GPR(R6)(r4)
489 lwz r7, VCPU_GPR(R7)(r4)
490 lwz r8, VCPU_GPR(R8)(r4)
499 lwz r3, VCPU_GPR(R3)(r4)
500 lwz r4, VCPU_GPR(R4)(r4)
532 SAVE_32EVRS(0, r4, r3, VCPU_EVR)
535 li r4,VCPU_ACC
536 evstddx evr6, r4, r3 /* save acc */
542 li r4,VCPU_ACC
543 evlddx evr6,r4,r3
545 REST_32EVRS(0, r4, r3, VCPU_EVR)
H A Dbookehv_interrupts.S68 * r4 = vcpu, r5 = srr0, r6 = srr1
73 PPC_STL r1, VCPU_GPR(R1)(r4)
74 PPC_STL r2, VCPU_GPR(R2)(r4)
75 PPC_LL r1, VCPU_HOST_STACK(r4)
79 lwz r8, VCPU_HOST_PID(r4)
80 PPC_LL r11, VCPU_SHARED(r4)
81 PPC_STL r14, VCPU_GPR(R14)(r4) /* We need a non-volatile GPR. */
84 stw r10, VCPU_GUEST_PID(r4)
93 stw r8, VCPU_TIMING_EXIT_TBL(r4)
95 stw r9, VCPU_TIMING_EXIT_TBU(r4)
101 PPC_STL r5, VCPU_PC(r4)
123 PPC_STL r15, VCPU_GPR(R15)(r4)
124 PPC_STL r16, VCPU_GPR(R16)(r4)
125 PPC_STL r17, VCPU_GPR(R17)(r4)
126 PPC_STL r18, VCPU_GPR(R18)(r4)
127 PPC_STL r19, VCPU_GPR(R19)(r4)
128 PPC_STL r20, VCPU_GPR(R20)(r4)
129 PPC_STL r21, VCPU_GPR(R21)(r4)
130 PPC_STL r22, VCPU_GPR(R22)(r4)
131 PPC_STL r23, VCPU_GPR(R23)(r4)
132 PPC_STL r24, VCPU_GPR(R24)(r4)
133 PPC_STL r25, VCPU_GPR(R25)(r4)
134 PPC_STL r26, VCPU_GPR(R26)(r4)
135 PPC_STL r27, VCPU_GPR(R27)(r4)
136 PPC_STL r28, VCPU_GPR(R28)(r4)
137 PPC_STL r29, VCPU_GPR(R29)(r4)
138 PPC_STL r30, VCPU_GPR(R30)(r4)
139 PPC_STL r31, VCPU_GPR(R31)(r4)
149 stw r9, VCPU_LAST_INST(r4)
154 PPC_STL r8, VCPU_FAULT_ESR(r4)
159 PPC_STL r9, VCPU_FAULT_DEAR(r4)
179 mr r11, r4
183 PPC_LL r4, PACACURRENT(r13)
184 PPC_LL r4, (THREAD + THREAD_KVM_VCPU)(r4)
185 stw r10, VCPU_CR(r4)
186 PPC_STL r11, VCPU_GPR(R4)(r4)
187 PPC_STL r5, VCPU_GPR(R5)(r4)
188 PPC_STL r6, VCPU_GPR(R6)(r4)
189 PPC_STL r8, VCPU_GPR(R8)(r4)
190 PPC_STL r9, VCPU_GPR(R9)(r4)
201 PPC_STL r5, VCPU_GPR(R13)(r4)
202 PPC_STL r3, VCPU_GPR(R3)(r4)
203 PPC_STL r7, VCPU_GPR(R7)(r4)
204 PPC_STL r12, VCPU_GPR(R12)(r4)
205 PPC_STL r6, VCPU_GPR(R10)(r4)
206 PPC_STL r8, VCPU_GPR(R11)(r4)
208 PPC_STL r5, VCPU_CTR(r4)
292 PPC_STL r4, VCPU_GPR(R4)(r11)
293 PPC_LL r4, THREAD_NORMSAVE(0)(r10)
300 PPC_STL r4, VCPU_GPR(R11)(r11)
309 mr r4, r11
319 PPC_STL r4, VCPU_GPR(R4)(r11)
320 PPC_LL r4, GPR9(r8)
327 PPC_STL r4, VCPU_GPR(R9)(r11)
329 PPC_LL r4, GPR11(r8)
335 PPC_STL r4, VCPU_GPR(R11)(r11)
337 mr r4, r11
379 * r4: vcpu pointer
386 PPC_STL r0, VCPU_GPR(R0)(r4)
389 PPC_STL r5, VCPU_LR(r4)
391 stw r3, VCPU_VRSAVE(r4)
403 PPC_STD(r5, VCPU_SPRG9, r4)
410 PPC_STL r3, VCPU_XER(r4)
422 lwz r6, VCPU_HOST_MAS4(r4)
424 lwz r8, VCPU_HOST_MAS6(r4)
446 mr r14, r4 /* Save vcpu pointer. */
450 mr r4, r14
451 PPC_LL r14, VCPU_GPR(R14)(r4)
455 PPC_LL r15, VCPU_GPR(R15)(r4)
456 PPC_LL r16, VCPU_GPR(R16)(r4)
457 PPC_LL r17, VCPU_GPR(R17)(r4)
458 PPC_LL r18, VCPU_GPR(R18)(r4)
459 PPC_LL r19, VCPU_GPR(R19)(r4)
460 PPC_LL r20, VCPU_GPR(R20)(r4)
461 PPC_LL r21, VCPU_GPR(R21)(r4)
462 PPC_LL r22, VCPU_GPR(R22)(r4)
463 PPC_LL r23, VCPU_GPR(R23)(r4)
464 PPC_LL r24, VCPU_GPR(R24)(r4)
465 PPC_LL r25, VCPU_GPR(R25)(r4)
466 PPC_LL r26, VCPU_GPR(R26)(r4)
467 PPC_LL r27, VCPU_GPR(R27)(r4)
468 PPC_LL r28, VCPU_GPR(R28)(r4)
469 PPC_LL r29, VCPU_GPR(R29)(r4)
470 PPC_LL r30, VCPU_GPR(R30)(r4)
471 PPC_LL r31, VCPU_GPR(R31)(r4)
489 PPC_STL r15, VCPU_GPR(R15)(r4)
490 PPC_STL r16, VCPU_GPR(R16)(r4)
491 PPC_STL r17, VCPU_GPR(R17)(r4)
492 PPC_STL r18, VCPU_GPR(R18)(r4)
493 PPC_STL r19, VCPU_GPR(R19)(r4)
494 PPC_STL r20, VCPU_GPR(R20)(r4)
495 PPC_STL r21, VCPU_GPR(R21)(r4)
496 PPC_STL r22, VCPU_GPR(R22)(r4)
497 PPC_STL r23, VCPU_GPR(R23)(r4)
498 PPC_STL r24, VCPU_GPR(R24)(r4)
499 PPC_STL r25, VCPU_GPR(R25)(r4)
500 PPC_STL r26, VCPU_GPR(R26)(r4)
501 PPC_STL r27, VCPU_GPR(R27)(r4)
502 PPC_STL r28, VCPU_GPR(R28)(r4)
503 PPC_STL r29, VCPU_GPR(R29)(r4)
504 PPC_STL r30, VCPU_GPR(R30)(r4)
505 PPC_STL r31, VCPU_GPR(R31)(r4)
536 * r4: vcpu pointer
540 PPC_STL r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */
571 PPC_LL r14, VCPU_GPR(R14)(r4)
572 PPC_LL r15, VCPU_GPR(R15)(r4)
573 PPC_LL r16, VCPU_GPR(R16)(r4)
574 PPC_LL r17, VCPU_GPR(R17)(r4)
575 PPC_LL r18, VCPU_GPR(R18)(r4)
576 PPC_LL r19, VCPU_GPR(R19)(r4)
577 PPC_LL r20, VCPU_GPR(R20)(r4)
578 PPC_LL r21, VCPU_GPR(R21)(r4)
579 PPC_LL r22, VCPU_GPR(R22)(r4)
580 PPC_LL r23, VCPU_GPR(R23)(r4)
581 PPC_LL r24, VCPU_GPR(R24)(r4)
582 PPC_LL r25, VCPU_GPR(R25)(r4)
583 PPC_LL r26, VCPU_GPR(R26)(r4)
584 PPC_LL r27, VCPU_GPR(R27)(r4)
585 PPC_LL r28, VCPU_GPR(R28)(r4)
586 PPC_LL r29, VCPU_GPR(R29)(r4)
587 PPC_LL r30, VCPU_GPR(R30)(r4)
588 PPC_LL r31, VCPU_GPR(R31)(r4)
595 stw r3, VCPU_HOST_PID(r4)
596 lwz r3, VCPU_GUEST_PID(r4)
599 PPC_LL r11, VCPU_SHARED(r4)
607 stw r3, VCPU_HOST_MAS4(r4)
609 stw r3, VCPU_HOST_MAS6(r4)
629 lwz r3, VCPU_VRSAVE(r4)
638 PPC_LD(r5, VCPU_SPRG9, r4)
643 PPC_LL r3, VCPU_LR(r4)
644 PPC_LL r5, VCPU_XER(r4)
645 PPC_LL r6, VCPU_CTR(r4)
646 lwz r7, VCPU_CR(r4)
647 PPC_LL r8, VCPU_PC(r4)
649 PPC_LL r0, VCPU_GPR(R0)(r4)
650 PPC_LL r1, VCPU_GPR(R1)(r4)
651 PPC_LL r2, VCPU_GPR(R2)(r4)
652 PPC_LL r10, VCPU_GPR(R10)(r4)
653 PPC_LL r11, VCPU_GPR(R11)(r4)
654 PPC_LL r12, VCPU_GPR(R12)(r4)
655 PPC_LL r13, VCPU_GPR(R13)(r4)
669 stw r9, VCPU_TIMING_LAST_ENTER_TBL(r4)
671 stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
681 PPC_LL r5, VCPU_GPR(R5)(r4)
682 PPC_LL r6, VCPU_GPR(R6)(r4)
683 PPC_LL r7, VCPU_GPR(R7)(r4)
684 PPC_LL r8, VCPU_GPR(R8)(r4)
685 PPC_LL r9, VCPU_GPR(R9)(r4)
687 PPC_LL r3, VCPU_GPR(R3)(r4)
688 PPC_LL r4, VCPU_GPR(R4)(r4)
H A Dbook3s_hv_rmhandlers.S63 ld r4, HSTATE_KVM_VCPU(r13)
82 lbz r4, LPPACA_PMCINUSE(r3)
83 cmpwi r4, 0
87 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
88 cmpwi r4, MMCR0_PMAO
92 lwz r4, HSTATE_PMC2(r13)
98 mtspr SPRN_PMC2, r4
104 ld r4, HSTATE_MMCR1(r13)
108 mtspr SPRN_MMCR1, r4
127 mftb r4
128 subf r4, r4, r3
129 mtspr SPRN_DEC, r4
249 ld r4, HSTATE_KVM_VCPU(r13)
250 cmpdi r4, 0
254 addi r3, r4, VCPU_TB_RMENTRY
261 ld r4, HSTATE_KVM_VCPU(r13)
262 cmpdi r4, 0
264 addi r3, r4, VCPU_TB_RMEXIT
319 ld r4,HSTATE_KVM_VCPU(r13)
320 cmpdi r4,0
370 mfspr r4, SPRN_LPCR
371 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
372 mtspr SPRN_LPCR, r4
377 ld r4, HSTATE_KVM_VCPU(r13)
378 cmpdi r4, 0
417 cmpdi r4, 0
419 addi r3, r4, VCPU_TB_RMENTRY
523 10: cmpdi r4, 0
528 lwz r5,VCPU_SLB_MAX(r4)
532 addi r6,r4,VCPU_SLB
540 ld r3, VCPU_VPA(r4)
548 stb r6, VCPU_VPA_DIRTY(r4)
556 ld r7,VCPU_PURR(r4)
557 ld r8,VCPU_SPURR(r4)
564 lwz r5,VCPU_DABRX(r4)
565 ld r6,VCPU_DABR(r4)
589 ld r5, VCPU_TFHAR(r4)
590 ld r6, VCPU_TFIAR(r4)
591 ld r7, VCPU_TEXASR(r4)
596 ld r5, VCPU_MSR(r4)
614 mr r31, r4
619 mr r4, r31
620 lwz r7, VCPU_VRSAVE_TM(r4)
623 ld r5, VCPU_LR_TM(r4)
624 lwz r6, VCPU_CR_TM(r4)
625 ld r7, VCPU_CTR_TM(r4)
626 ld r8, VCPU_AMR_TM(r4)
627 ld r9, VCPU_TAR_TM(r4)
639 ld r29, VCPU_DSCR_TM(r4)
640 ld r30, VCPU_PPR_TM(r4)
671 ld r4, HSTATE_KVM_VCPU(r13)
688 ld r3, VCPU_MMCR(r4)
693 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
694 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
695 lwz r6, VCPU_PMC + 8(r4)
696 lwz r7, VCPU_PMC + 12(r4)
697 lwz r8, VCPU_PMC + 16(r4)
698 lwz r9, VCPU_PMC + 20(r4)
705 ld r3, VCPU_MMCR(r4)
706 ld r5, VCPU_MMCR + 8(r4)
707 ld r6, VCPU_MMCR + 16(r4)
708 ld r7, VCPU_SIAR(r4)
709 ld r8, VCPU_SDAR(r4)
715 ld r5, VCPU_MMCR + 24(r4)
716 ld r6, VCPU_SIER(r4)
717 lwz r7, VCPU_PMC + 24(r4)
718 lwz r8, VCPU_PMC + 28(r4)
719 ld r9, VCPU_MMCR + 32(r4)
732 ld r14, VCPU_GPR(R14)(r4)
733 ld r15, VCPU_GPR(R15)(r4)
734 ld r16, VCPU_GPR(R16)(r4)
735 ld r17, VCPU_GPR(R17)(r4)
736 ld r18, VCPU_GPR(R18)(r4)
737 ld r19, VCPU_GPR(R19)(r4)
738 ld r20, VCPU_GPR(R20)(r4)
739 ld r21, VCPU_GPR(R21)(r4)
740 ld r22, VCPU_GPR(R22)(r4)
741 ld r23, VCPU_GPR(R23)(r4)
742 ld r24, VCPU_GPR(R24)(r4)
743 ld r25, VCPU_GPR(R25)(r4)
744 ld r26, VCPU_GPR(R26)(r4)
745 ld r27, VCPU_GPR(R27)(r4)
746 ld r28, VCPU_GPR(R28)(r4)
747 ld r29, VCPU_GPR(R29)(r4)
748 ld r30, VCPU_GPR(R30)(r4)
749 ld r31, VCPU_GPR(R31)(r4)
752 ld r5, VCPU_DSCR(r4)
766 ld r5, VCPU_IAMR(r4)
767 lwz r6, VCPU_PSPB(r4)
768 ld r7, VCPU_FSCR(r4)
772 ld r5, VCPU_DAWR(r4)
773 ld r6, VCPU_DAWRX(r4)
774 ld r7, VCPU_CIABR(r4)
775 ld r8, VCPU_TAR(r4)
780 ld r5, VCPU_IC(r4)
781 ld r6, VCPU_VTB(r4)
784 ld r8, VCPU_EBBHR(r4)
786 ld r5, VCPU_EBBRR(r4)
787 ld r6, VCPU_BESCR(r4)
788 ld r7, VCPU_CSIGR(r4)
789 ld r8, VCPU_TACR(r4)
794 ld r5, VCPU_TCSCR(r4)
795 ld r6, VCPU_ACOP(r4)
796 lwz r7, VCPU_GUEST_PID(r4)
797 ld r8, VCPU_WORT(r4)
807 ld r8,VCPU_DEC_EXPIRES(r4)
815 stw r3,VCPU_DEC(r4)
817 ld r5, VCPU_SPRG0(r4)
818 ld r6, VCPU_SPRG1(r4)
819 ld r7, VCPU_SPRG2(r4)
820 ld r8, VCPU_SPRG3(r4)
827 ld r5, VCPU_DAR(r4)
828 lwz r6, VCPU_DSISR(r4)
833 ld r5,VCPU_AMR(r4)
834 ld r6,VCPU_UAMOR(r4)
841 lwz r5,VCPU_CTRL(r4)
872 ld r6, VCPU_CTR(r4)
873 lwz r7, VCPU_XER(r4)
878 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
879 ld r10, VCPU_PC(r4)
880 ld r11, VCPU_MSR(r4)
881 ld r6, VCPU_SRR0(r4)
882 ld r7, VCPU_SRR1(r4)
893 ld r0, VCPU_PENDING_EXC(r4)
913 mr r9, r4
926 stb r0,VCPU_CEDED(r4) /* cancel cede */
936 addi r3, r4, VCPU_TB_GUEST
943 ld r5, VCPU_CFAR(r4)
947 ld r0, VCPU_PPR(r4)
950 ld r5, VCPU_LR(r4)
951 lwz r6, VCPU_CR(r4)
955 ld r1, VCPU_GPR(R1)(r4)
956 ld r2, VCPU_GPR(R2)(r4)
957 ld r3, VCPU_GPR(R3)(r4)
958 ld r5, VCPU_GPR(R5)(r4)
959 ld r6, VCPU_GPR(R6)(r4)
960 ld r7, VCPU_GPR(R7)(r4)
961 ld r8, VCPU_GPR(R8)(r4)
962 ld r9, VCPU_GPR(R9)(r4)
963 ld r10, VCPU_GPR(R10)(r4)
964 ld r11, VCPU_GPR(R11)(r4)
965 ld r12, VCPU_GPR(R12)(r4)
966 ld r13, VCPU_GPR(R13)(r4)
971 ld r0, VCPU_GPR(R0)(r4)
972 ld r4, VCPU_GPR(R4)(r4)
979 cmpdi r4, 0
981 stw r12, VCPU_TRAP(r4)
983 addi r3, r4, VCPU_TB_RMEXIT
990 stw r12, VCPU_TRAP(r4)
991 mr r9, r4
993 addi r3, r4, VCPU_TB_RMEXIT
1038 std r4, VCPU_GPR(R4)(r9)
1048 lwz r4, HSTATE_SCRATCH1(r13)
1050 stw r4, VCPU_CR(r9)
1056 ld r4, HSTATE_PPR(r13)
1057 std r4, VCPU_PPR(r9)
1077 mflr r4
1079 std r4, VCPU_LR(r9)
1085 mr r4, r9
1104 mfxer r4
1106 stw r4, VCPU_XER(r9)
1119 mr r4,r9
1149 mr r4, r9
1170 mr r4, r9
1225 ld r4,HSTATE_SPURR(r13)
1227 add r4,r4,r6
1229 mtspr SPRN_SPURR,r4
1238 ld r4,VCORE_TB_OFFSET(r3)
1239 subf r5,r4,r5
1328 mfspr r4, SPRN_SPRG1
1332 std r4, VCPU_SPRG1(r9)
1390 GET_SCRATCH0(r4)
1391 std r4, VCPU_GPRS_TM(13)(r9)
1393 ld r4, PACATMSCRATCH(r13)
1394 std r4, VCPU_GPRS_TM(9)(r9)
1448 li r4, LPPACA_YIELDCOUNT
1449 LWZX_BE r3, r8, r4
1451 STWX_BE r3, r8, r4
1483 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1499 std r4, VCPU_MMCR(r9)
1508 mfspr r4, SPRN_PMC2
1514 stw r4, VCPU_PMC + 4(r9)
1528 lis r4, 0x8000
1529 mtspr SPRN_MMCRS, r4
1546 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1566 ld r6,KVM_HOST_SDR1(r4)
1567 lwz r7,KVM_HOST_LPID(r4)
1611 16: ld r8,KVM_HOST_LPCR(r4)
1631 ld r4, HSTATE_KVM_VCPU(r13)
1632 cmpdi r4, 0
1655 mfspr r4, SPRN_HDAR
1662 clrrdi r0, r4, 28
1665 4: std r4, VCPU_FAULT_DAR(r9)
1684 ld r4, VCPU_FAULT_DAR(r9)
1686 1: mtspr SPRN_DAR, r4
1697 mr r4, r9
1714 ori r4, r3, MSR_DR /* Enable paging for data */
1715 mtmsrd r4
1742 mr r4, r10
1785 ld r4, VCPU_KVM(r9)
1788 add r4, r4, r0
1789 ld r0, KVM_ENABLED_HCALLS(r4)
1790 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
1791 srd r0, r0, r4
1795 LOAD_REG_ADDR(r4, hcall_real_table)
1796 lwax r3,r3,r4
1799 add r12,r3,r4
1802 ld r4,VCPU_GPR(R4)(r9)
1806 ld r4,HSTATE_KVM_VCPU(r13)
1807 std r3,VCPU_GPR(R3)(r4)
1808 ld r10,VCPU_PC(r4)
1809 ld r11,VCPU_MSR(r4)
1817 mr r4,r9
2050 std r4,VCPU_DABR(r3)
2054 1: mtspr SPRN_DABR,r4
2056 cmpd r4, r5
2063 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2064 rlwimi r5, r4, 2, DAWRX_WT
2065 clrrdi r4, r4, 3
2066 std r4, VCPU_DAWR(r3)
2068 mtspr SPRN_DAWR, r4
2099 31: lwarx r4,0,r6
2100 or r4,r4,r0
2101 cmpw r4,r8
2103 stwcx. r4,0,r6
2148 mfspr r4, SPRN_HDEC
2150 cmpw r3, r4
2152 mtspr SPRN_DEC, r4
2157 ld r4, HSTATE_KVM_VCPU(r13)
2161 std r3, VCPU_DEC_EXPIRES(r4)
2164 ld r4, HSTATE_KVM_VCPU(r13)
2165 addi r3, r4, VCPU_TB_CEDE
2201 33: mr r4, r3
2208 ld r4, HSTATE_KVM_VCPU(r13)
2214 addi r3, r4, VCPU_TB_RMINTR
2222 ld r3, VCPU_DEC_EXPIRES(r4)
2231 ld r14, VCPU_GPR(R14)(r4)
2232 ld r15, VCPU_GPR(R15)(r4)
2233 ld r16, VCPU_GPR(R16)(r4)
2234 ld r17, VCPU_GPR(R17)(r4)
2235 ld r18, VCPU_GPR(R18)(r4)
2236 ld r19, VCPU_GPR(R19)(r4)
2237 ld r20, VCPU_GPR(R20)(r4)
2238 ld r21, VCPU_GPR(R21)(r4)
2239 ld r22, VCPU_GPR(R22)(r4)
2240 ld r23, VCPU_GPR(R23)(r4)
2241 ld r24, VCPU_GPR(R24)(r4)
2242 ld r25, VCPU_GPR(R25)(r4)
2243 ld r26, VCPU_GPR(R26)(r4)
2244 ld r27, VCPU_GPR(R27)(r4)
2245 ld r28, VCPU_GPR(R28)(r4)
2246 ld r29, VCPU_GPR(R29)(r4)
2247 ld r30, VCPU_GPR(R30)(r4)
2248 ld r31, VCPU_GPR(R31)(r4)
2267 stw r12, VCPU_TRAP(r4)
2268 mr r9, r4
2483 * r4 = vcpu pointer
2489 mr r31,r4
2503 addi r3,r4,VCPU_FPRS
2514 mr r4,r31
2563 * r3 = pointer to time accumulation struct, r4 = vcpu
2573 std r3, VCPU_CUR_ACTIVITY(r4)
2574 std r5, VCPU_ACTIVITY_START(r4)
2579 * r3 = pointer to new time accumulation struct, r4 = vcpu
2587 4: ld r5, VCPU_CUR_ACTIVITY(r4)
2588 ld r6, VCPU_ACTIVITY_START(r4)
2589 std r3, VCPU_CUR_ACTIVITY(r4)
2592 std r7, VCPU_ACTIVITY_START(r4)
H A Dbook3s_32_sr.S128 lis r4, 0xc000
129 3: mtsrin r3, r4
131 addis r4, r4, 0x1000 /* address of next segment */
136 /* 'current->mm' needs to be in r4 */
137 tophys(r4, r2)
138 lwz r4, MM(r4)
139 tophys(r4, r4)
140 /* This only clobbers r0, r3, r4 and r5 */
H A Dbook3s_interrupts.S69 * r4: vcpu pointer
81 /* Save r3 (kvm_run) and r4 (vcpu) */
95 VCPU_LOAD_NVGPRS(r4)
106 PPC_LL r3, VCPU_HFLAGS(r4)
111 lwz r3, VCPU_SHAREDBE(r4)
113 ld r5, VCPU_SHARED(r4)
135 PPC_LL r4, VCPU_SHADOW_MSR(r4) /* get shadow_msr */
170 GET_SHADOW_VCPU(r4)
208 /* Restore r3 (kvm_run) and r4 (vcpu) */
221 PPC_LL r4, _LINK(r1)
222 mtlr r4
235 PPC_LL r4, _LINK(r1)
236 PPC_STL r4, (PPC_LR_STKOFF + SWITCH_FRAME_SIZE)(r1)
242 VCPU_LOAD_NVGPRS(r4)
H A Dfpu.S40 stfs 0,0(r4); \
62 stfs 0,0(r4); \
86 stfs 0,0(r4); \
127 lwz r6, 0(r4) /* load cr */
144 stw r6,0(r4) /* save new cr value */
214 lwz r6, 0(r4); /* load cr */ \
221 stw r6,0(r4); /* save new cr value */ \
277 stfd 0,0(r4)
282 stfs 0,0(r4)
/linux-4.1.27/arch/m32r/kernel/
H A Dhead.S56 mv r4, r3 || ldi r1, #0
57 srli r4, #4 || addi r2, #-4
58 beqz r4, .Lendloop1
64 st r1, @+r2 || addi r4, #-1
67 st r1, @+r2 || cmpeq r1, r4 ; R4 = 0?
70 and3 r4, r3, #15
72 beqz r4, .Lendloop2
74 stb r1, @r2 || addi r4, #-1
76 bnez r4, .Lloop2
84 mv r4, r3
85 srli r4, #2 ; R4 = BSS size in longwords (rounded down)
88 beqz r4, .Lendloop1 ; any more to go?
91 addi r4, #-1 ; decrement count
92 bnez r4, .Lloop1 ; go do some more
94 and3 r4, r3, #3 ; get no. of remaining BSS bytes to clear
96 beqz r4, .Lendloop2 ; any more to go?
100 addi r4, #-1 ; decrement count
101 bnez r4, .Lloop2 ; go do some more
139 LDIMM (r4, eit_vector)
140 mvtc r4, cr5
145 seth r4, #high(MATM)
146 or3 r4, r4, #low(MATM)
148 st r5, @r4 ; Set MATM Reg(T bit ON)
149 ld r6, @r4 ; MATM Check
156 ld r6, @r4 ; MATM Check
157 seth r4, #high(M32R_ICU_ISTS_ADDR)
158 or3 r4, r4, #low(M32R_ICU_ISTS_ADDR)
159 ld r5, @r4 ; Read ISTSi reg.
163 seth r4, #high(M32R_ICU_IMASK_ADDR)
164 or3 r4, r4, #low(M32R_ICU_IMASK_ADDR)
165 st r5, @r4 ; Write IMASKi reg.
168 seth r4, #high(M32R_IRQ_IPI5)
169 or3 r4, r4, #low(M32R_IRQ_IPI5)
170 bne r4, r6, 2f ; if (ISN != CPU_BOOT_IPI) goto sleep;
173 LDIMM (r4, cpu_bootout_map)
174 ld r4, @r4
180 and r4, r6
181 beqz r4, 2f
182 LDIMM (r4, cpu_bootin_map)
183 ld r5, @r4
185 st r6, @r4
188 ldi r4, #0
189 mvtc r4, psw
192 LDIMM (r4, stack_start)
193 ld r4, @r4
194 mvtc r4, spi
197 LDIMM (r4, start_secondary)
198 mvtc r4, bpc
207 seth r4, #high(MATM)
208 or3 r4, r4, #low(MATM)
210 st r5, @r4 ; Set MATM Reg(T bit OFF)
211 ld r6, @r4 ; MATM Check
212 LDIMM (r4, 3f)
216 and r4, r5
217 jmp r4 ; disable MMU
222 LDIMM (r4, AP_loop)
226 and r4, r5
227 jmp r4
H A Dentry.S27 * @(sp) - r4
154 preempt_stop(r4)
156 ld r4, PSW(sp)
158 and3 r4, r4, #0x8800 ; check BSM and BPM bits
160 and3 r4, r4, #0x8000 ; check BSM bit
162 beqz r4, resume_kernel
164 DISABLE_INTERRUPTS(r4) ; make sure we don't miss an interrupt
169 and3 r4, r9, #_TIF_WORK_MASK ; is there any work to be done on
171 bnez r4, work_pending
181 and3 r4, r9, #_TIF_NEED_RESCHED
182 beqz r4, restore_all
183 ld r4, PSW(sp) ; interrupts off (exception path) ?
184 and3 r4, r4, #0x4000
185 beqz r4, restore_all
194 ENABLE_INTERRUPTS(r4) ; Enable interrupt
202 and3 r4, r9, #_TIF_SYSCALL_TRACE
203 bnez r4, syscall_trace_entry
206 LDIMM (r4, sys_call_table)
207 add r7, r4
212 DISABLE_INTERRUPTS(r4) ; make sure we don't miss an interrupt
216 and3 r4, r9, #_TIF_ALLWORK_MASK ; current->work
217 bnez r4, syscall_exit_work
225 and3 r4, r9, #_TIF_NEED_RESCHED
226 beqz r4, work_notifysig
229 DISABLE_INTERRUPTS(r4) ; make sure we don't miss an interrupt
233 and3 r4, r9, #_TIF_WORK_MASK ; is there any work to be done other
235 beqz r4, restore_all
236 and3 r4, r4, #_TIF_NEED_RESCHED
237 bnez r4, work_resched
249 ldi r4, #-ENOSYS
250 st r4, R0(sp)
256 ld r4, R4(sp)
268 and3 r4, r9, #_TIF_SYSCALL_TRACE
269 beqz r4, work_pending
270 ENABLE_INTERRUPTS(r4) ; could let do_syscall_trace() call
279 ldi r4, #-EFAULT
280 st r4, R0(sp)
285 ldi r4, #-ENOSYS
286 st r4, R0(sp)
431 ld r4, @(low(MESTS_offset),r2)
432 st r4, @(low(MESTS_offset),r2)
433 srl3 r1, r4, #4
444 and3 r1, r4, #2
532 push r4
542 pop r4
/linux-4.1.27/arch/sh/lib64/
H A Dstrcpy.S25 ldlo.q r3,0,r4
29 mcmpeq.b r4,r63,r6
49 mcmv r4, r8, r9
53 add r5, r63, r4
59 stlo.q r2, 0, r4
60 SHHI r4, r7, r4
61 sthi.q r0, -1, r4
64 add r5, r63, r4
69 byterev r4,r4
72 st.b r0,-8,r4
73 andi r4,0xff,r5
74 shlri r4,8,r4
82 ldx.q r0, r20, r4
85 mcmpeq.b r4, r63, r6
88 stlo.q r0, -8, r4
89 sthi.q r0, -1, r4
93 add r5, r63, r4
H A Dudivdi3.S5 shlri r3,1,r4
6 nsb r4,r22
11 mmulfx.w r1,r1,r4
14 mmulfx.w r5,r4,r4
17 msub.w r1,r4,r1
19 mmulfx.w r1,r1,r4
22 mmulfx.w r5,r4,r4
25 msub.w r1,r4,r1
27 mulu.l r1,r7,r4
30 sub r63,r4,r4 // Negate to make sure r1 ends up <= 1/r2
31 shlri r4,2,r4 /* chop off leading %0000000000000000 001.00000000000 - or, as
33 muls.l r1,r4,r4 /* leaving at least one sign bit. */
36 shari r4,26,r4
38 add r1,r4,r1 // 31 bit unsigned reciprocal now in r1 (msb equiv. 0.5)
69 mmulfx.w r5,r4,r4
72 msub.w r1,r4,r1
74 mulu.l r1,r7,r4
77 sub r63,r4,r4 // Negate to make sure r1 ends up <= 1/r2
78 shlri r4,2,r4 /* chop off leading %0000000000000000 001.00000000000 - or, as
80 muls.l r1,r4,r4 /* leaving at least one sign bit. */
84 shari r4,26,r4
85 add r1,r4,r1 // 31 bit unsigned reciprocal now in r1 (msb equiv. 0.5)
H A Dmemset.S31 add r4, r22, r23
37 beqi/u r4, 0, tr2 // Return with size 0 - ensures no mem accesses
39 shlli r4, 2, r4
41 SHHI r8, r4, r8
42 SHHI r8, r4, r8
51 add r2, r4, r5
H A Dudivsi3.S6 inputs: r4,r5
31 mulu.l r4,r21,r18
38 sub r4,r20,r25
/linux-4.1.27/arch/powerpc/platforms/powernv/
H A Dsubcore-asm.S20 * r4 = temp
28 li r4,0
29 ori r4,r4,MSR_EE|MSR_SE|MSR_BE|MSR_RI
30 andc r4,r12,r4
32 mtmsrd r4
36 andc r5, r4, r5
38 LOAD_REG_ADDR(r4, real_mode)
40 mtspr SPRN_SRR0,r4
57 li r4, SYNC_STEP_REAL_MODE
58 stb r4, 0(r3)
64 1: mfspr r4, SPRN_HID0
65 and. r4, r4, r5
74 li r4, 0
75 mtspr SPRN_LPID, r4
76 mtspr SPRN_PCR, r4
77 mtspr SPRN_HDEC, r4
/linux-4.1.27/arch/arm/lib/
H A Dcsumpartialcopygeneric.S114 1: load4l r4, r5, r6, r7
115 stmia dst!, {r4, r5, r6, r7}
116 adcs sum, sum, r4
128 load2l r4, r5
129 stmia dst!, {r4, r5}
130 adcs sum, sum, r4
135 3: load1l r4
136 str r4, [dst], #4
137 adcs sum, sum, r4
141 load1l r4
143 mov r5, r4, get_byte_0
145 adcs sum, sum, r4, lspush #16
147 mov r5, r4, get_byte_1
149 mov r5, r4, get_byte_2
175 mov r4, r5, lspull #8 @ C = 0
179 orr r4, r4, r5, lspush #24
186 stmia dst!, {r4, r5, r6, r7}
187 adcs sum, sum, r4
191 mov r4, r8, lspull #8
200 orr r4, r4, r5, lspush #24
203 stmia dst!, {r4, r5}
204 adcs sum, sum, r4
206 mov r4, r6, lspull #8
210 orr r4, r4, r5, lspush #24
211 str r4, [dst], #4
212 adcs sum, sum, r4
213 mov r4, r5, lspull #8
216 mov r5, r4, get_byte_0
219 adcs sum, sum, r4, lspush #16
221 mov r5, r4, get_byte_1
223 mov r5, r4, get_byte_2
226 .Lsrc2_aligned: mov r4, r5, lspull #16
231 orr r4, r4, r5, lspush #16
238 stmia dst!, {r4, r5, r6, r7}
239 adcs sum, sum, r4
243 mov r4, r8, lspull #16
252 orr r4, r4, r5, lspush #16
255 stmia dst!, {r4, r5}
256 adcs sum, sum, r4
258 mov r4, r6, lspull #16
262 orr r4, r4, r5, lspush #16
263 str r4, [dst], #4
264 adcs sum, sum, r4
265 mov r4, r5, lspull #16
268 mov r5, r4, get_byte_0
271 adcs sum, sum, r4
273 mov r5, r4, get_byte_1
280 .Lsrc3_aligned: mov r4, r5, lspull #24
285 orr r4, r4, r5, lspush #8
292 stmia dst!, {r4, r5, r6, r7}
293 adcs sum, sum, r4
297 mov r4, r8, lspull #24
306 orr r4, r4, r5, lspush #8
309 stmia dst!, {r4, r5}
310 adcs sum, sum, r4
312 mov r4, r6, lspull #24
316 orr r4, r4, r5, lspush #8
317 str r4, [dst], #4
318 adcs sum, sum, r4
319 mov r4, r5, lspull #24
322 mov r5, r4, get_byte_0
326 adcs sum, sum, r4
327 load1l r4
328 mov r5, r4, get_byte_0
330 adcs sum, sum, r4, lspush #24
331 mov r5, r4, get_byte_1
H A Dio-readsw-armv4.S33 stmfd sp!, {r4, r5, lr}
39 ldrh r4, [r0]
40 pack r3, r3, r4
42 ldrh r4, [r0]
44 pack r4, r4, r5
62 ldrh r4, [r0]
63 pack r3, r3, r4
65 ldrh r4, [r0]
67 pack r4, r4, ip
69 stmia r1!, {r3, r4}
82 ldmfd sp!, {r4, r5, pc}
96 .Linsw_noalign: stmfd sp!, {r4, lr}
112 ldrh r4, [r0]
115 orr ip, ip, r4, push_hbyte0
117 mov ip, r4, pull_hbyte1
130 ldmfd sp!, {r4, pc}
H A Dcopy_page.S28 stmfd sp!, {r4, lr} @ 2
32 ldmia r1!, {r3, r4, ip, lr} @ 4+1
37 stmia r0!, {r3, r4, ip, lr} @ 4
38 ldmia r1!, {r3, r4, ip, lr} @ 4
41 stmia r0!, {r3, r4, ip, lr} @ 4
42 ldmgtia r1!, {r3, r4, ip, lr} @ 4
44 PLD( ldmeqia r1!, {r3, r4, ip, lr} )
46 ldmfd sp!, {r4, pc} @ 3
H A Decard.S25 stmfd sp!, {r4 - r12, lr}
31 ldmfd sp!, {r4 - r12, pc}
38 stmfd sp!, {r4 - r12, lr}
43 ldmfd sp!, {r4 - r12, pc}
H A Dcsumpartialcopyuser.S21 stmfd sp!, {r1, r2, r4 - r8, lr}
25 ldmfd sp!, {r1, r2, r4 - r8, pc}
73 9001: mov r4, #-EFAULT
75 str r4, [r5]
H A Dio-writesw-armv4.S38 stmfd sp!, {r4, r5, lr}
43 .Loutsw_8_lp: ldmia r1!, {r3, r4, r5, ip}
46 outword r4
67 ldmfd sp!, {r4, r5, pc}
H A Ddiv64.S39 * r4 = divisor (preserved)
52 subs ip, r4, #1
54 tst ip, r4
58 cmp xh, r4
68 clz yl, r4
73 mov yl, r4, lsl yl
77 mov yl, r4
99 cmpeq xl, r4
110 cmpcc xh, r4
112 subcs xh, xh, r4
155 clz ip, r4
160 mov yl, r4
161 cmp r4, #(1 << 16)
H A Dcsumpartialcopy.S21 stmfd sp!, {r1, r4 - r8, lr}
25 ldmfd sp!, {r1, r4 - r8, pc}
/linux-4.1.27/arch/arm/boot/compressed/
H A Dll_char_wr.S36 stmfd sp!, {r4 - r7, lr}
38 @ Smashable regs: {r0 - r3}, [r4 - r7], (r8 - fp), [ip], (sp), [lr], (pc)
48 ldmia ip, {r3, r4, r5, r6, lr}
52 ldr r4, [r4, ip]
57 cmp r4, #4
62 teq r4, #8
65 @ Smashable regs: {r0 - r3}, [r4], {r5 - r7}, (r8 - fp), [ip], (sp), {lr}, (pc)
80 ldmfd sp!, {r4 - r7, pc}
83 @ Smashable regs: {r0 - r3}, [r4], {r5 - r7}, (r8 - fp), [ip], (sp), {lr}, (pc)
88 mul r4, r2, ip
89 and ip, r7, #15 @ avoid r4
90 ldr ip, [lr, ip, lsl #2] @ avoid r4
91 mul ip, r2, ip @ avoid r4
94 stmia r0, {r4, ip}
98 mul r4, r2, ip
99 and ip, r7, #15 @ avoid r4
100 ldr ip, [lr, ip, lsl #2] @ avoid r4
101 mul ip, r2, ip @ avoid r4
104 stmia r0, {r4, ip}
108 ldmfd sp!, {r4 - r7, pc}
111 @ Smashable regs: {r0 - r3}, [r4], {r5, r6}, [r7], (r8 - fp), [ip], (sp), [lr], (pc)
115 ldmia r6, {r4, r7}
116 strb r4, [r0], r5
117 mov r4, r4, lsr #8
118 strb r4, [r0], r5
119 mov r4, r4, lsr #8
120 strb r4, [r0], r5
121 mov r4, r4, lsr #8
122 strb r4, [r0], r5
130 ldmfd sp!, {r4 - r7, pc}
/linux-4.1.27/arch/sh/boot/romimage/
H A Dhead.S17 mov.l empty_zero_page_dst, r4
19 add r5, r4
23 mov r4, r15
25 mov.l empty_zero_page_dst, r4
27 add r5, r4
29 add r5, r4
30 jmp @r4
50 mov #(PAGE_SHIFT - 4), r4
52 shld r4, r3 /* r3 = PAGE_SIZE / 16 */
55 mov.l @r0, r4
60 mov.l r4, @r1
69 mov #PAGE_SHIFT, r4
71 shld r4, r1
/linux-4.1.27/arch/m32r/mm/
H A Dpage.S28 ld r4, @r1+
34 st r4, @r0
38 ld r4, @r1+
47 st r4, @r0
65 ldi r4, #0
69 st r4, @r0
70 st r4, @+r0
71 st r4, @+r0
72 st r4, @+r0
78 st r4, @r0
79 st r4, @+r0
80 st r4, @+r0
81 st r4, @+r0
H A Dmmu.S218 st r4, @-sp
232 ld r4, @(low(tlb_entry_i_dat),r3)
233 sll3 r2, r4, #3
237 addi r4, #1 ; tlb_entry_i++;
238 and3 r4, r4, #(NR_TLB_ENTRIES-1)
239 st r4, @(low(tlb_entry_i_dat),r3)
246 ld r4, @(low(tlb_entry_d_dat),r3)
247 sll3 r2, r4, #3
251 addi r4, #1 ; tlb_entry_d++;
252 and3 r4, r4, #(NR_TLB_ENTRIES-1)
253 st r4, @(low(tlb_entry_d_dat),r3)
258 ; r1,r3,r4: (free)
263 srl3 r4, r0, #22
264 sll3 r3, r4, #2
271 ldi r4, #0x163 ; _KERNPG_TABLE(=0x163)
272 bne r1, r4, 3f ; pmd_bad(*pmd) ?
277 ld r4, @r3 ; r4: pte
279 and r4, r3
282 add r4, r3
284 add r4, r3 ; r4: pte
286 ld r1, @r4 ; r1: pte_data
293 ; r3,r4: (free)
297 seth r4, #shigh(MASID)
298 ld r4, @(low(MASID),r4) ; r4: MASID
299 and3 r4, r4, #(MMU_CONTEXT_ASID_MASK)
300 or r3, r4
304 ld r4, @sp+
/linux-4.1.27/arch/microblaze/lib/
H A Dfastcopy.S47 addi r4, r0, 4 /* n = 4 */
48 cmpu r4, r4, r7 /* n = c - n (unsigned) */
49 blti r4, a_xfer_end /* if n < 0, less than one word to transfer */
52 andi r4, r5, 3 /* n = d & 3 */
54 beqi r4, a_dalign_done
56 rsubi r4, r4, 4
57 rsub r7, r4, r7 /* c = c - n adjust c */
61 beqi r4, a_dalign_done
67 addi r4, r4, -1 /* n-- (IN DELAY SLOT) */
70 addi r4, r0, 32 /* n = 32 */
71 cmpu r4, r4, r7 /* n = c - n (unsigned) */
73 blti r4, a_block_done
76 andi r4, r7, 0xffffffe0 /* n = c & ~31 */
77 rsub r7, r4, r7 /* c = c - n */
101 addi r4, r4, -32 /* n = n - 32 */
102 bneid r4, a_block_aligned /* while (n) loop */
108 add r6, r6, r4 /* s = s + n */
160 addi r4, r4, -32 /* n = n - 32 */
161 bneid r4, a_bu3_loop /* while (n) loop */
209 addi r4, r4, -32 /* n = n - 32 */
210 bneid r4, a_bu1_loop /* while (n) loop */
258 addi r4, r4, -32 /* n = n - 32 */
259 bneid r4, a_bu2_loop /* while (n) loop */
263 addi r4, r0, 4 /* n = 4 */
264 cmpu r4, r4, r7 /* n = c - n (unsigned) */
265 blti r4, a_xfer_end /* if n < 0, less than one word to transfer */
268 andi r4, r7, 0xfffffffc /* n = c & ~3 */
278 addi r4, r4,-4 /* n-- */
279 bneid r4, a_word_aligned /* loop */
302 addi r4, r4,-4 /* n = n - 4 */
303 bneid r4, a_wu3_loop /* while (n) loop */
316 addi r4, r4,-4 /* n = n - 4 */
317 bneid r4, a_wu1_loop /* while (n) loop */
330 addi r4, r4,-4 /* n = n - 4 */
331 bneid r4, a_wu2_loop /* while (n) loop */
361 cmpu r4, r5, r6 /* n = s - d */
362 bgei r4,fast_memcpy_ascending
371 addi r4, r0, 4 /* n = 4 */
372 cmpu r4, r4, r7 /* n = c - n (unsigned) */
373 blti r4,d_xfer_end /* if n < 0, less than one word to transfer */
376 andi r4, r5, 3 /* n = d & 3 */
378 beqi r4,d_dalign_done
379 rsub r7, r4, r7 /* c = c - n adjust c */
383 beqi r4,d_dalign_done
389 addi r4, r4, -1 /* n-- (IN DELAY SLOT) */
392 addi r4, r0, 32 /* n = 32 */
393 cmpu r4, r4, r7 /* n = c - n (unsigned) */
395 blti r4, d_block_done
398 andi r4, r7, 0xffffffe0 /* n = c & ~31 */
399 rsub r7, r4, r7 /* c = c - n */
423 addi r4, r4, -32 /* n = n - 32 */
424 bneid r4, d_block_aligned /* while (n) loop */
430 rsub r6, r4, r6 /* s = s - n */
482 addi r4, r4, -32 /* n = n - 32 */
483 bneid r4, d_bu3_loop /* while (n) loop */
531 addi r4, r4, -32 /* n = n - 32 */
532 bneid r4, d_bu1_loop /* while (n) loop */
580 addi r4, r4, -32 /* n = n - 32 */
581 bneid r4, d_bu2_loop /* while (n) loop */
585 addi r4, r0, 4 /* n = 4 */
586 cmpu r4, r4, r7 /* n = c - n (unsigned) */
587 blti r4,d_xfer_end /* if n < 0, less than one word to transfer */
590 andi r4, r7, 0xfffffffc /* n = c & ~3 */
591 rsub r5, r4, r5 /* d = d - n */
592 rsub r6, r4, r6 /* s = s - n */
593 rsub r7, r4, r7 /* c = c - n */
600 addi r4, r4,-4 /* n-- */
601 lw r9, r6, r4 /* t1 = *(s+n) */
602 bneid r4, d_word_aligned /* loop */
603 sw r9, r5, r4 /* *(d+n) = t1 (IN DELAY SLOT) */
609 lw r11, r8, r4 /* h = *(as + n) */
619 addi r4, r4,-4 /* n = n - 4 */
620 lw r12, r8, r4 /* v = *(as + n) */
623 sw r9, r5, r4 /* *(d + n) = t1 */
624 bneid r4, d_wu3_loop /* while (n) loop */
632 addi r4, r4,-4 /* n = n - 4 */
633 lw r12, r8, r4 /* v = *(as + n) */
636 sw r9, r5, r4 /* *(d + n) = t1 */
637 bneid r4, d_wu1_loop /* while (n) loop */
645 addi r4, r4,-4 /* n = n - 4 */
646 lw r12, r8, r4 /* v = *(as + n) */
649 sw r9, r5, r4 /* *(d + n) = t1 */
650 bneid r4, d_wu2_loop /* while (n) loop */
H A Duaccess_old.S35 * r4 - temp val
40 lbu r4,r6,r0
41 beqid r4,2f
42 sb r4,r5,r0
82 lbu r4,r5,r0
83 beqid r4,2f /* break on NUL */
107 1: lwi r4 , r6, 0x0000 + offset; \
115 9: swi r4 , r5, 0x0000 + offset; \
163 * r4 - tempval
176 w1: lw r4, r6, r3 /* at least one 4 byte copy */
177 w2: sw r4, r5, r3
203 loop: /* r4, r19, r20, r21, r22, r23, r24, r25 are used for storing values */
252 bu1: lbu r4,r6,r3
253 bu2: sb r4,r5,r3
H A Dmulsi3.S20 xor r4, r5, r6 /* get the sign of the result */
35 blti r4, negateresult
/linux-4.1.27/arch/powerpc/crypto/
H A Daes-spe-keys.S81 LOAD_KEY(r5,r4,0)
82 LOAD_KEY(r6,r4,4)
83 LOAD_KEY(r7,r4,8)
84 LOAD_KEY(r8,r4,12)
95 LS_BOX(r14, r15, r4)
105 GF8_MUL(r0, r0, r4, r14) /* multiply RCO by 2 in GF */
123 LOAD_KEY(r5,r4,0)
124 LOAD_KEY(r6,r4,4)
125 LOAD_KEY(r7,r4,8)
126 LOAD_KEY(r8,r4,12)
127 LOAD_KEY(r9,r4,16)
128 LOAD_KEY(r10,r4,20)
141 LS_BOX(r14, r15, r4)
158 GF8_MUL(r0, r0, r4, r14) /* multiply RCO GF8 */
173 LOAD_KEY(r5,r4,0)
174 LOAD_KEY(r6,r4,4)
175 LOAD_KEY(r7,r4,8)
176 LOAD_KEY(r8,r4,12)
177 LOAD_KEY(r9,r4,16)
178 LOAD_KEY(r10,r4,20)
179 LOAD_KEY(r11,r4,24)
180 LOAD_KEY(r12,r4,28)
195 LS_BOX(r14, r15, r4)
202 LS_BOX(r14, r15, r4) /* apply LS_BOX to 4th temp */
218 GF8_MUL(r0, r0, r4, r14)
232 lwzx r7,r4,r6 /* first/last 4 words are same */
234 lwz r7,0(r4)
237 lwzx r7,r4,r6
239 lwz r7,4(r4)
242 lwzx r7,r4,r6
244 lwz r7,8(r4)
247 lwzx r7,r4,r6
249 lwz r7,12(r4)
252 add r4,r4,r6
253 subi r4,r4,28
260 lwz r6,0(r4)
277 addi r4,r4,4
279 subi r4,r4,32
/linux-4.1.27/arch/powerpc/mm/
H A Dtlb_nohash_low.S50 mtspr SPRN_PID,r4
83 rlwimi r5,r4,0,16,31
112 clrrwi r4,r3,12 /* get an EPN for the hashing with V = 0 */
113 ori r4,r4,PPC47x_TLBE_SIZE
114 tlbwe r4,r7,0 /* write it */
132 lis r4,tlb_44x_hwater@ha
133 lwz r5,tlb_44x_hwater@l(r4)
157 li r4,0 /* Current way */
164 or r5,r3,r4 /* Make way|index for tlbre */
167 3: addis r4,r4,0x2000 /* Next way */
201 rlwimi r5,r4,0,16,31
273 mfspr r4,SPRN_MAS6 /* save MAS6 */
276 mtspr SPRN_MAS6,r4 /* restore MAS6 */
297 slwi r4,r4,16
298 ori r4,r4,(MAS6_ISIZE(BOOK3E_PAGESZ_4K))@l
299 mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
302 mfspr r4,SPRN_MAS1 /* check valid */
303 andis. r3,r4,MAS1_VALID@h
305 rlwinm r4,r4,0,1,31
306 mtspr SPRN_MAS1,r4
323 slwi r4,r3,MAS6_SPID_SHIFT
326 mtspr SPRN_MAS6,r4
334 slwi r4,r3,MAS6_SPID_SHIFT
336 ori r4,r4,MAS6_SIND
338 mtspr SPRN_MAS6,r4
355 slwi r4,r4,MAS6_SPID_SHIFT
356 rlwimi r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
358 rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
359 1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
370 slwi r4,r4,MAS6_SPID_SHIFT
371 rlwimi r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
373 rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
374 1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
389 stw r4, 0x4(r5)
406 LOAD_REG_ADDR_PIC(r4, TLBCAM)
409 add r3,r5,r4
410 lwz r4,TLBCAM_MAS0(r3)
411 mtspr SPRN_MAS0,r4
412 lwz r4,TLBCAM_MAS1(r3)
413 mtspr SPRN_MAS1,r4
414 PPC_LL r4,TLBCAM_MAS2(r3)
415 mtspr SPRN_MAS2,r4
416 lwz r4,TLBCAM_MAS3(r3)
417 mtspr SPRN_MAS3,r4
419 lwz r4,TLBCAM_MAS7(r3)
420 mtspr SPRN_MAS7,r4
H A Dhash_low_32.S40 * The address is in r4, and r3 contains an access flag:
70 cmplw 0,r4,r0
80 rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
84 rlwinm r8,r4,13,19,29 /* Compute pgdir/pmd offset */
98 rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */
100 rlwimi r8,r4,23,20,28 /* compute pte address */
138 mfsrin r3,r4 /* get segment reg for segment */
182 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
233 rlwimi r8,r4,22,20,29
235 rlwimi r8,r4,23,20,28
277 * r3 contains the VSID, r4 contains the virtual address,
336 rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */
343 rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
353 tlbie r4
355 addis r4,r7,htab_hash_searches@ha
356 lwz r6,htab_hash_searches@l(r4)
358 stw r6,htab_hash_searches@l(r4)
362 addi r4,r3,-HPTE_SIZE
363 1: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */
371 xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
372 xori r4,r4,(-PTEG_SIZE & 0xffff)
373 addi r4,r4,-HPTE_SIZE
375 2: LDPTEu r6,HPTE_SIZE(r4)
383 addi r4,r3,-HPTE_SIZE /* search primary PTEG */
384 1: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */
390 addis r4,r7,primary_pteg_full@ha
391 lwz r6,primary_pteg_full@l(r4)
393 stw r6,primary_pteg_full@l(r4)
398 xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
399 xori r4,r4,(-PTEG_SIZE & 0xffff)
400 addi r4,r4,-HPTE_SIZE
402 2: LDPTEu r6,HPTE_SIZE(r4)
427 1: addis r4,r7,next_slot@ha /* get next evict slot */
428 lwz r6,next_slot@l(r4)
431 stw r6,next_slot@l(r4)
432 add r4,r3,r6
433 LDPTE r0,HPTE_SIZE/2(r4) /* get PTE second word */
444 STPTE r5,0(r4)
446 STPTE r8,HPTE_SIZE/2(r4)
469 STPTE r5,0(r4)
472 STPTE r8,HPTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */
475 STPTE r5,0(r4) /* finally set V bit in PTE */
520 rlwimi r5,r4,22,20,29
522 rlwimi r5,r4,23,20,28
529 addi r4,r4,0x1000
536 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
542 rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */
583 rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
612 tlbie r4 /* in hw tlb too */
618 addi r4,r4,0x1000
H A Dhash_low_64.S85 andc. r0,r4,r31
97 rlwinm r30,r4,32-9+7,31-7,31-7 /* _PAGE_RW -> _PAGE_DIRTY */
108 * r4 (access) is re-useable, we use it for the new HPTE flags
148 rlwinm r4,r30,32-7+1,30,30 /* _PAGE_DIRTY -> _PAGE_USER (r4) */
149 and r0,r0,r4 /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
161 mr r4,r30
172 ld r4,htab_hash_mask@got(2)
173 ld r27,0(r4) /* htab_hash_mask -> r27 */
200 mr r4,r29 /* Retrieve vpn */
225 mr r4,r29 /* Retrieve vpn */
282 /* Keep PP bits in r4 and slot idx from the PTE around in r3 */
283 mr r4,r3
383 andc. r0,r4,r31
394 rlwinm r30,r4,32-9+7,31-7,31-7 /* _PAGE_RW -> _PAGE_DIRTY */
406 * r4 (access) is re-useable, we use it for the new HPTE flags
464 rlwinm r4,r30,32-7+1,30,30 /* _PAGE_DIRTY -> _PAGE_USER (r4) */
465 and r0,r0,r4 /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
477 mr r4,r30
488 ld r4,htab_hash_mask@got(2)
489 ld r27,0(r4) /* htab_hash_mask -> r27 */
529 mr r4,r29 /* Retrieve vpn */
558 mr r4,r29 /* Retrieve vpn */
594 mr r4,r31 /* PTE.pte */
625 li r4,0xf
626 sld r4,r4,r5
627 andc r26,r26,r4
648 /* Keep PP bits in r4 and slot idx from the PTE around in r3 */
649 mr r4,r3
742 andc. r0,r4,r31
759 rlwinm r30,r4,32-9+7,31-7,31-7 /* _PAGE_RW -> _PAGE_DIRTY */
770 * r4 (access) is re-useable, we use it for the new HPTE flags
809 rlwinm r4,r30,32-7+1,30,30 /* _PAGE_DIRTY -> _PAGE_USER (r4) */
810 and r0,r0,r4 /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
822 mr r4,r30
833 ld r4,htab_hash_mask@got(2)
834 ld r27,0(r4) /* htab_hash_mask -> r27 */
864 mr r4,r29 /* Retrieve vpn */
889 mr r4,r29 /* Retrieve vpn */
946 /* Keep PP bits in r4 and slot idx from the PTE around in r3 */
947 mr r4,r3
/linux-4.1.27/arch/powerpc/kernel/vdso32/
H A Dgettimeofday.S41 mr r11,r4 /* r11 saves tz */
47 addi r7,r7,1000000@l /* so we get microseconds in r4 */
50 stw r4,TVAL32_TV_USEC(r10)
54 lwz r4,CFG_TZ_MINUTEWEST(r9)/* fill tz */
56 stw r4,TZONE_TZ_MINWEST(r11)
82 mr r11,r4 /* r11 saves tp */
97 * At this point, r3,r4 contain our sec/nsec values, r5 and r6
119 add r4,r4,r6
120 cmpw cr0,r4,r7
121 cmpwi cr1,r4,0
123 subf r4,r7,r4
127 add r4,r4,r7
130 stw r4,TSPC32_TV_NSEC(r11)
163 cmpli cr0,r4,0
168 stw r3,TSPC32_TV_SEC(r4)
169 stw r5,TSPC32_TV_NSEC(r4)
211 * it returns the current time in r3 (seconds) and r4.
212 * On entry, r7 gives the resolution of r4, either USEC_PER_SEC
213 * or NSEC_PER_SEC, giving r4 in microseconds or nanoseconds.
237 mftbl r4
241 mfspr r4, SPRN_TBRL
249 subfc r4,r6,r4
252 rlwimi. r0,r4,12,20,31
253 slwi r4,r4,12
267 mulhwu r4,r4,r5
273 addc r4,r4,r5
277 * as a 32.32 fixed-point number in r3 and r4.
282 addc r4,r4,r6
285 /* We create a fake dependency on the result in r3/r4
288 or r6,r4,r3
295 mulhwu r4,r4,r7 /* convert to micro or nanoseconds */
H A Ddatapage.S56 mr r4,r3
60 cmpli cr0,r4,0
63 stw r0,0(r4)
79 lwz r4,(CFG_TB_TICKS_PER_SEC + 4)(r3)
/linux-4.1.27/tools/testing/selftests/powerpc/stringloops/
H A Dmemcmp_64.S35 or r6,r3,r4
49 lbz rB,0(r4)
55 lbz rB,1(r4)
61 lbz rB,2(r4)
67 lbz rB,3(r4)
72 addi r4,r4,4
100 LD rB,0,r4
103 LD rD,off8,r4
106 LD rF,off16,r4
109 LD rH,off24,r4
113 addi r4,r4,32
118 LD rB,0,r4
122 LD rD,off8,r4
126 LD rF,off16,r4
131 LD rH,off24,r4
136 addi r4,r4,32
143 LD rB,0,r4
148 LD rD,off8,r4
153 LD rF,off16,r4
158 LD rH,off24,r4
163 addi r4,r4,32
/linux-4.1.27/arch/score/kernel/
H A Dentry.S106 mfcr r4, cr2
111 srli r4, r4, 18 # get ecr.ip[7:2], interrupt No.
117 mv r4, r0
128 mv r4, r0
131 mv r4, r0
137 mv r4, r0
140 mv r4, r0
146 mv r4, r0
149 mv r4, r0
155 mv r4, r0
158 mv r4, r0
164 mv r4, r0
167 mv r4, r0
173 mv r4, r0
176 mv r4, r0
186 mv r4, r0
189 mv r4, r0
195 mv r4, r0
198 mv r4, r0
204 mv r4, r0
207 mv r4, r0
213 mv r4, r0
216 mv r4, r0
222 mv r4, r0
225 mv r4, r0
282 bl schedule_tail # r4=struct task_struct *prev
284 mv r4, r13
289 bl schedule_tail # r4=struct task_struct *prev
318 mv r4, r0
331 mv r4, r0
379 sw r9, [r4, THREAD_PSR]
380 save_context r4
381 sw r3, [r4, THREAD_REG3]
409 sw r4, [r0, PT_ORIG_R4] #for restart syscall
435 cmpi.c r4, 0
441 cmpi.c r4, -MAX_ERRNO - 1
445 neg r4, r4
447 sw r4, [r0, PT_R4] # save result
462 mv r4, r0
467 lw r4, [r0, PT_R4] # Restore argument registers
476 neg r4, r4 # error
477 sw r4, [r0, PT_R0] # set flag for syscall
479 1: sw r4, [r0, PT_R2] # result
483 ldi r4, -ENOSYS # error
484 sw r4, [r0, PT_ORIG_R4]
485 sw r4, [r0, PT_R4]
491 mv r4, r0
H A Dhead.S65 xor r4, r4, r4
/linux-4.1.27/arch/s390/kernel/
H A Dbase.S86 larl %r4,.Lctlregs # Save control registers
87 stctg %c0,%c15,0(%r4)
88 larl %r4,.Lfpctl # Floating point control register
89 stfpc 0(%r4)
90 larl %r4,.Lcontinue_psw # Save PSW flags
92 stm %r2,%r3,0(%r4)
93 larl %r4,.Lrestart_psw # Setup restart PSW at absolute 0
95 lg %r4,0(%r4) # Save PSW
96 sturg %r4,%r3 # Use sturg, because of large pages
105 larl %r4,.Lctlregs # Restore control registers
106 lctlg %c0,%c15,0(%r4)
107 larl %r4,.Lfpctl # Restore floating point ctl register
108 lfpc 0(%r4)
109 larl %r4,.Lcontinue_psw # Restore PSW flags
110 lpswe 0(%r4)
H A Dmcount.S40 lgrl %r4,function_trace_op
45 larl %r4,function_trace_op
46 lg %r4,0(%r4)
/linux-4.1.27/arch/arm/crypto/
H A Daes-ce-core.S167 push {r4, lr}
168 ldr r4, [sp, #8]
171 subs r4, r4, #3
180 adds r4, r4, #3
186 subs r4, r4, #1
189 pop {r4, pc}
193 push {r4, lr}
194 ldr r4, [sp, #8]
197 subs r4, r4, #3
206 adds r4, r4, #3
212 subs r4, r4, #1
215 pop {r4, pc}
225 push {r4-r6, lr}
226 ldrd r4, r5, [sp, #16]
234 subs r4, r4, #1
237 pop {r4-r6, pc}
241 push {r4-r6, lr}
242 ldrd r4, r5, [sp, #16]
246 subs r4, r4, #3
262 adds r4, r4, #3
271 subs r4, r4, #1
275 pop {r4-r6, pc}
283 push {r4-r6, lr}
284 ldrd r4, r5, [sp, #16]
289 cmn r6, r4 @ 32 bit overflow?
292 subs r4, r4, #3
316 adds r4, r4, #3
321 subs r4, r4, #1
331 teq r4, #0
335 pop {r4-r6, pc}
341 pop {r4-r6, pc}
352 0: teq r4, #0
380 ldrd r4, r5, [sp, #16] @ load args
395 push {r4-r6, lr}
407 subs r4, r4, #3
423 teq r4, #0
427 adds r4, r4, #3
435 subs r4, r4, #1
441 pop {r4-r6, pc}
446 push {r4-r6, lr}
458 subs r4, r4, #3
474 teq r4, #0
478 adds r4, r4, #3
487 subs r4, r4, #1
493 pop {r4-r6, pc}
H A Dsha1-armv4-large.S60 stmdb sp!,{r4-r12,lr}
62 ldmia r0,{r3,r4,r5,r6,r7}
91 and r10,r4,r10,ror#2
103 eor r10,r4,r5 @ F_xx_xx
110 eor r10,r4,r5 @ F_xx_xx
128 eor r10,r3,r4 @ F_xx_xx
135 eor r10,r3,r4 @ F_xx_xx
143 eor r10,r10,r4,ror#2 @ F_00_19(B,C,D)
150 add r4,r8,r4,ror#2 @ E+=K_00_19
155 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
159 add r4,r8,r4,ror#2 @ E+=K_00_19
161 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
167 add r4,r4,r9 @ E+=X[i]
170 add r4,r4,r10 @ E+=F_00_19(B,C,D)
180 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
186 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
219 and r10,r4,r10,ror#2
231 eor r10,r4,r5 @ F_xx_xx
248 eor r10,r3,r4 @ F_xx_xx
256 eor r10,r10,r4,ror#2 @ F_00_19(B,C,D)
261 add r4,r8,r4,ror#2 @ E+=K_xx_xx
267 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
272 add r4,r4,r9 @ E+=X[i]
274 add r4,r4,r10 @ E+=F_00_19(B,C,D)
284 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
308 eor r10,r4,r10,ror#2 @ F_xx_xx
319 eor r10,r4,r5 @ F_xx_xx
335 eor r10,r3,r4 @ F_xx_xx
347 add r4,r8,r4,ror#2 @ E+=K_xx_xx
353 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
358 add r4,r4,r9 @ E+=X[i]
359 add r4,r4,r10 @ E+=F_20_39(B,C,D)
369 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
397 and r10,r4,r10,ror#2 @ F_xx_xx
409 eor r10,r4,r5 @ F_xx_xx
415 and r11,r4,r5 @ F_xx_xx
426 eor r10,r3,r4 @ F_xx_xx
432 and r11,r3,r4 @ F_xx_xx
439 add r4,r8,r4,ror#2 @ E+=K_xx_xx
445 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
450 add r4,r4,r9 @ E+=X[i]
451 add r4,r4,r10 @ E+=F_40_59(B,C,D)
452 add r4,r4,r11,ror#2
462 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
481 add r4,r9,r4
485 stmia r0,{r3,r4,r5,r6,r7}
489 ldmia sp!,{r4-r12,pc}
H A Daes-armv4.S153 stmdb sp!,{r1,r4-r12,lr}
159 ldrb r4,[r12,#2] @ manner...
162 orr r0,r0,r4,lsl#8
165 ldrb r4,[r12,#6]
169 orr r1,r1,r4,lsl#8
172 ldrb r4,[r12,#10]
176 orr r2,r2,r4,lsl#8
179 ldrb r4,[r12,#14]
183 orr r3,r3,r4,lsl#8
213 mov r4,r0,lsr#24 @ write output in endian-neutral
216 strb r4,[r12,#0]
218 mov r4,r1,lsr#24
223 strb r4,[r12,#4]
225 mov r4,r2,lsr#24
230 strb r4,[r12,#8]
232 mov r4,r3,lsr#24
237 strb r4,[r12,#12]
242 ldmia sp!,{r4-r12,pc}
249 ldmia r11!,{r4-r7}
250 eor r0,r0,r4
263 ldr r4,[r10,r7,lsl#2] @ Te3[s0>>0]
283 eor r1,r1,r4,ror#24
306 ldr r4,[r11,#-12]
313 eor r1,r1,r4
325 ldrb r4,[r10,r7,lsl#2] @ Te4[s0>>0]
345 eor r1,r4,r1,lsl#24
367 ldr r4,[r11,#4]
374 eor r1,r1,r4
401 .Lok: stmdb sp!,{r4-r12,lr}
410 ldrb r4,[r12,#2] @ manner...
413 orr r0,r0,r4,lsl#8
416 ldrb r4,[r12,#6]
420 orr r1,r1,r4,lsl#8
423 ldrb r4,[r12,#10]
427 orr r2,r2,r4,lsl#8
430 ldrb r4,[r12,#14]
434 orr r3,r3,r4,lsl#8
476 ldr r4,[r6],#4 @ rcon[i++]
478 eor r5,r5,r4
495 ldrb r4,[r12,#18]
498 orr r8,r8,r4,lsl#8
501 ldrb r4,[r12,#22]
505 orr r9,r9,r4,lsl#8
540 ldr r4,[r6],#4 @ rcon[i++]
542 eor r9,r5,r4
566 ldrb r4,[r12,#26]
569 orr r8,r8,r4,lsl#8
572 ldrb r4,[r12,#30]
576 orr r9,r9,r4,lsl#8
609 ldr r4,[r6],#4 @ rcon[i++]
611 eor r9,r5,r4
634 ldr r4,[r11,#-48]
639 eor r4,r4,r5 @ rk[12]=rk[4]^...
641 eor r7,r7,r4 @ rk[13]=rk[5]^rk[12]
642 str r4,[r11,#-16]
651 ldmia sp!,{r4-r12,lr}
669 stmdb sp!,{r4-r12}
680 ldr r4,[r8]
688 str r4,[r7],#16
705 .Lmix: and r4,r0,r7
707 sub r4,r4,r4,lsr#7
708 and r4,r4,r8
709 eor r1,r4,r1,lsl#1 @ tp2
711 and r4,r1,r7
713 sub r4,r4,r4,lsr#7
714 and r4,r4,r8
715 eor r2,r4,r2,lsl#1 @ tp4
717 and r4,r2,r7
719 sub r4,r4,r4,lsr#7
720 and r4,r4,r8
721 eor r3,r4,r3,lsl#1 @ tp8
723 eor r4,r1,r2
725 eor r4,r4,r3 @ tpe
726 eor r4,r4,r1,ror#24
727 eor r4,r4,r5,ror#24 @ ^= ROTATE(tpb=tp9^tp2,8)
728 eor r4,r4,r2,ror#16
729 eor r4,r4,r5,ror#16 @ ^= ROTATE(tpd=tp9^tp4,16)
730 eor r4,r4,r5,ror#8 @ ^= ROTATE(tp9,24)
733 str r4,[r11],#4
738 ldmia sp!,{r4-r12,pc}
848 stmdb sp!,{r1,r4-r12,lr}
854 ldrb r4,[r12,#2] @ manner...
857 orr r0,r0,r4,lsl#8
860 ldrb r4,[r12,#6]
864 orr r1,r1,r4,lsl#8
867 ldrb r4,[r12,#10]
871 orr r2,r2,r4,lsl#8
874 ldrb r4,[r12,#14]
878 orr r3,r3,r4,lsl#8
908 mov r4,r0,lsr#24 @ write output in endian-neutral
911 strb r4,[r12,#0]
913 mov r4,r1,lsr#24
918 strb r4,[r12,#4]
920 mov r4,r2,lsr#24
925 strb r4,[r12,#8]
927 mov r4,r3,lsr#24
932 strb r4,[r12,#12]
937 ldmia sp!,{r4-r12,pc}
944 ldmia r11!,{r4-r7}
945 eor r0,r0,r4
958 ldr r4,[r10,r7,lsl#2] @ Td1[s0>>16]
978 eor r1,r1,r4,ror#8
1002 ldr r4,[r11,#-12]
1008 eor r1,r1,r4
1022 ldr r4,[r10,#64]
1025 ldr r4,[r10,#160]
1030 ldrb r4,[r10,r7] @ Td4[s0>>16]
1044 eor r1,r4,r1,lsl#8
1074 ldr r4,[r11,#4]
1081 eor r1,r1,r4
H A Dbsaes-armv7.pl57 my ($key,$rounds,$const)=("r4","r5","r6");
896 my ($out,$inp,$rounds,$const)=("r12","r4","r5","r6");
988 stmdb sp!,{r4-r6,lr}
992 mov r4,$inp @ pass key
999 ldmia sp!,{r4-r6,pc}
1006 stmdb sp!,{r4-r6,lr}
1011 mov r4,$key @ pass the key
1029 ldmia sp!,{r4-r6,pc}
1036 stmdb sp!,{r4-r6,lr}
1040 mov r4,$inp @ pass key
1049 ldmia sp!,{r4-r6,pc}
1056 stmdb sp!,{r4-r6,lr}
1061 mov r4,$key @ pass the key
1079 ldmia sp!,{r4-r6,pc}
1109 stmdb sp!, {r4-r10, lr}
1123 mov r4, $key @ pass key
1138 mov r4, $key @ pass key
1142 add r4, $key, #248
1143 vldmia r4, {@XMM[6]}
1146 vstmia r4, {@XMM[7]}
1163 mov r4, $keysched @ pass the key
1165 add r4, $key, #248
1207 mov r4, $keysched @ pass the key
1209 add r4, $key, #248
1355 ldmia sp!, {r4-r10, pc}
1374 stmdb sp!, {r4-r10, lr}
1387 mov r4, $key @ pass key
1404 mov r4, $key @ pass key
1445 add r4, $keysched, #0x10 @ pass next round key
1447 add r4, $key, #`248+16`
1536 ldmia sp!, {r4-r10, pc} @ return
1541 stmdb sp!, {r4-r8, lr}
1543 mov r4, $inp @ copy arguments
1563 vld1.8 {@XMM[0]}, [r4]! @ load input
1581 ldmia sp!, {r4-r8, pc}
1602 stmdb sp!, {r4-r10, lr} @ 0x20
1635 mov r4, $key @ pass key
1648 mov r4, $key @ pass key
1701 add r4, sp, #0x90 @ pass key schedule
1703 add r4, $key, #248 @ pass key schedule
1770 add r4, sp, #0x90 @ pass key schedule
1772 add r4, $key, #248 @ pass key schedule
1804 add r4, sp, #0x90 @ pass key schedule
1806 add r4, $key, #248 @ pass key schedule
1841 add r4, sp, #0x90 @ pass key schedule
1843 add r4, $key, #248 @ pass key schedule
1871 add r4, sp, #0x90 @ pass key schedule
1873 add r4, $key, #248 @ pass key schedule
1898 add r4, sp, #0x90 @ pass key schedule
1900 add r4, $key, #248 @ pass key schedule
1924 add r4, sp, #0x90 @ pass key schedule
1926 add r4, $key, #248 @ pass key schedule
1948 mov r4, $fp @ preserve fp
1955 mov $fp, r4
1980 mov r4, $fp @ preserve fp
1987 mov $fp, r4
2007 ldmia sp!, {r4-r10, pc} @ return
2016 stmdb sp!, {r4-r10, lr} @ 0x20
2049 mov r4, $key @ pass key
2054 add r4, sp, #0x90
2055 vldmia r4, {@XMM[6]}
2058 vstmia r4, {@XMM[7]}
2065 mov r4, $key @ pass key
2069 add r4, $key, #248
2070 vldmia r4, {@XMM[6]}
2073 vstmia r4, {@XMM[7]}
2126 add r4, sp, #0x90 @ pass key schedule
2128 add r4, $key, #248 @ pass key schedule
2195 add r4, sp, #0x90 @ pass key schedule
2197 add r4, $key, #248 @ pass key schedule
2229 add r4, sp, #0x90 @ pass key schedule
2231 add r4, $key, #248 @ pass key schedule
2260 add r4, sp, #0x90 @ pass key schedule
2262 add r4, $key, #248 @ pass key schedule
2290 add r4, sp, #0x90 @ pass key schedule
2292 add r4, $key, #248 @ pass key schedule
2317 add r4, sp, #0x90 @ pass key schedule
2319 add r4, $key, #248 @ pass key schedule
2343 add r4, sp, #0x90 @ pass key schedule
2345 add r4, $key, #248 @ pass key schedule
2367 mov r4, $fp @ preserve fp
2375 mov $fp, r4
2400 mov r4, $fp @ preserve fp
2430 mov $fp, r4
2450 ldmia sp!, {r4-r10, pc} @ return
/linux-4.1.27/arch/arc/lib/
H A Dmemcmp.S24 ld r4,[r0,0]
30 brne r4,r5,.Leven
31 ld.a r4,[r0,8]
37 brne r4,r5,.Leven
38 ld r4,[r0,4]
44 xor r0,r4,r5
52 xor r0,r4,r5
59 asl r2,r4,r1
82 lsr r4,r4,SHIFT
86 sub.f r0,r4,r5
100 ldb r4,[r0,0]
106 brne r4,r5,.Lbyte_even
107 ldb.a r4,[r0,2]
112 brne r4,r5,.Lbyte_even
120 sub r0,r4,r5
H A Dmemset.S14 mov_s r4,r0
29 stb.ab r1,[r4,1]
30 and r4,r4,-2
31 stw.ab r1,[r4,2]
32 and r4,r4,-4
38 st.ab r1,[r4,4]
46 stb.ab r1,[r4,1]
H A Dstrcpy-700.S34 mov_s r4,r3
38 st.ab r4,[r10,4]
40 ld.a r4,[r1,4]
46 sub r2,r4,r8
47 bic r2,r2,r4
50 mov_s r3,r4
/linux-4.1.27/arch/openrisc/lib/
H A Dstring.S39 l.sw 4(r1),r4
46 8: l.lbz r6,0(r4)
50 l.addi r4,r4,1
55 l.lwz r4,4(r1)
79 l.sw 0(r1),r4
82 2: l.sfeq r4,r0
84 l.addi r4,r4,-1
90 l.addi r11,r4,1
92 l.lwz r4,0(r1)
/linux-4.1.27/arch/arm/mm/
H A Dcopypage-v4wt.c27 stmfd sp!, {r4, lr} @ 2\n\ v4wt_copy_user_page()
29 ldmia r1!, {r3, r4, ip, lr} @ 4\n\ v4wt_copy_user_page()
30 1: stmia r0!, {r3, r4, ip, lr} @ 4\n\ v4wt_copy_user_page()
31 ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\ v4wt_copy_user_page()
32 stmia r0!, {r3, r4, ip, lr} @ 4\n\ v4wt_copy_user_page()
33 ldmia r1!, {r3, r4, ip, lr} @ 4\n\ v4wt_copy_user_page()
34 stmia r0!, {r3, r4, ip, lr} @ 4\n\ v4wt_copy_user_page()
35 ldmia r1!, {r3, r4, ip, lr} @ 4\n\ v4wt_copy_user_page()
37 stmia r0!, {r3, r4, ip, lr} @ 4\n\ v4wt_copy_user_page()
38 ldmneia r1!, {r3, r4, ip, lr} @ 4\n\ v4wt_copy_user_page()
41 ldmfd sp!, {r4, pc} @ 3" v4wt_copy_user_page()
H A Dcopypage-xsc3.c36 stmfd sp!, {r4, r5, lr} \n\ xsc3_mc_copy_user_page()
46 ldrd r4, [r1], #8 \n\ xsc3_mc_copy_user_page()
50 strd r4, [r0], #8 \n\ xsc3_mc_copy_user_page()
51 ldrd r4, [r1], #8 \n\ xsc3_mc_copy_user_page()
53 strd r4, [r0], #8 \n\ xsc3_mc_copy_user_page()
56 ldrd r4, [r1], #8 \n\ xsc3_mc_copy_user_page()
61 strd r4, [r0], #8 \n\ xsc3_mc_copy_user_page()
62 ldrd r4, [r1], #8 \n\ xsc3_mc_copy_user_page()
64 strd r4, [r0], #8 \n\ xsc3_mc_copy_user_page()
68 ldmfd sp!, {r4, r5, pc}" xsc3_mc_copy_user_page()
H A Dcopypage-v4wb.c29 stmfd sp!, {r4, lr} @ 2\n\ v4wb_copy_user_page()
31 ldmia r1!, {r3, r4, ip, lr} @ 4\n\ v4wb_copy_user_page()
33 stmia r0!, {r3, r4, ip, lr} @ 4\n\ v4wb_copy_user_page()
34 ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\ v4wb_copy_user_page()
35 stmia r0!, {r3, r4, ip, lr} @ 4\n\ v4wb_copy_user_page()
36 ldmia r1!, {r3, r4, ip, lr} @ 4\n\ v4wb_copy_user_page()
38 stmia r0!, {r3, r4, ip, lr} @ 4\n\ v4wb_copy_user_page()
39 ldmia r1!, {r3, r4, ip, lr} @ 4\n\ v4wb_copy_user_page()
41 stmia r0!, {r3, r4, ip, lr} @ 4\n\ v4wb_copy_user_page()
42 ldmneia r1!, {r3, r4, ip, lr} @ 4\n\ v4wb_copy_user_page()
45 ldmfd sp!, {r4, pc} @ 3" v4wb_copy_user_page()
H A Dcopypage-xscale.c47 "stmfd sp!, {r4, r5, lr} \n\ mc_copy_user_page()
58 ldrd r4, [r0], #8 \n\ mc_copy_user_page()
62 strd r4, [r1], #8 \n\ mc_copy_user_page()
63 ldrd r4, [r0], #8 \n\ mc_copy_user_page()
65 strd r4, [r1], #8 \n\ mc_copy_user_page()
69 ldrd r4, [r0], #8 \n\ mc_copy_user_page()
73 strd r4, [r1], #8 \n\ mc_copy_user_page()
74 ldrd r4, [r0], #8 \n\ mc_copy_user_page()
76 strd r4, [r1], #8 \n\ mc_copy_user_page()
82 ldmfd sp!, {r4, r5, pc} " mc_copy_user_page()
H A Dcopypage-fa.c24 stmfd sp!, {r4, lr} @ 2\n\ fa_copy_user_page()
26 1: ldmia r1!, {r3, r4, ip, lr} @ 4\n\ fa_copy_user_page()
27 stmia r0, {r3, r4, ip, lr} @ 4\n\ fa_copy_user_page()
30 ldmia r1!, {r3, r4, ip, lr} @ 4\n\ fa_copy_user_page()
31 stmia r0, {r3, r4, ip, lr} @ 4\n\ fa_copy_user_page()
37 ldmfd sp!, {r4, pc} @ 3" fa_copy_user_page()
H A Dproc-arm740.S79 mov r4, #10 @ 11 is the minimum (4KB)
80 1: add r4, r4, #1 @ area size *= 2
83 orr r0, r0, r4, lsl #1 @ the area register value
92 mov r4, #10 @ 11 is the minimum (4KB)
93 1: add r4, r4, #1 @ area size *= 2
96 orr r0, r0, r4, lsl #1 @ the area register value
H A Dcopypage-v4mc.c47 "stmfd sp!, {r4, lr} @ 2\n\ mc_copy_user_page()
48 mov r4, %2 @ 1\n\ mc_copy_user_page()
58 subs r4, r4, #1 @ 1\n\ mc_copy_user_page()
62 ldmfd sp!, {r4, pc} @ 3" mc_copy_user_page()
/linux-4.1.27/arch/arm/mach-omap1/
H A Dsram.S46 mov r4, #0x0700 @ let the clocks settle
47 orr r4, r4, #0x00ff
48 delay: sub r4, r4, #1
49 cmp r4, #0
52 lock: ldrh r4, [r2], #0 @ read back dpll value
55 tst r4, #1 << 0 @ dpll rate locked?
H A Dsleep.S72 mov r4, #0
93 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
94 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
95 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
101 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
106 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
130 strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
131 strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
152 mov r4, #TCMIF_ASM_BASE & 0xff000000
153 orr r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
154 orr r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
158 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
160 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
164 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
167 ldr r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
170 str r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
173 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
175 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
178 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
179 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
180 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
185 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
190 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
209 strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
210 strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
227 mov r4, #0
248 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
249 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
250 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
256 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
261 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
358 strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
359 strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
/linux-4.1.27/arch/blackfin/kernel/
H A Dentry.S31 r4 = [p0]; define
32 bitset(r4, 0);
33 [p0] = r4;
43 r4 = [p0]; define
44 sti r4;
/linux-4.1.27/arch/arm/mach-prima2/
H A Dheadsmp.S20 adr r4, 1f
21 ldmia r4, {r5, r6}
22 sub r4, r4, r5
23 add r6, r6, r4
/linux-4.1.27/arch/arm/mach-spear/
H A Dheadsmp.S26 adr r4, 1f
27 ldmia r4, {r5, r6}
28 sub r4, r4, r5
29 add r6, r6, r4
/linux-4.1.27/arch/arm/mach-sti/
H A Dheadsmp.S27 adr r4, 1f
28 ldmia r4, {r5, r6}
29 sub r4, r4, r5
30 add r6, r6, r4
/linux-4.1.27/arch/arm/mach-ux500/
H A Dheadsmp.S20 adr r4, 1f
21 ldmia r4, {r5, r6}
22 sub r4, r4, r5
23 add r6, r6, r4
/linux-4.1.27/arch/arm/plat-versatile/
H A Dheadsmp.S24 adr r4, 1f
25 ldmia r4, {r5, r6}
26 sub r4, r4, r5
27 add r6, r6, r4
/linux-4.1.27/arch/arm/mach-exynos/
H A Dheadsmp.S23 adr r4, 1f
24 ldmia r4, {r5, r6}
25 sub r4, r4, r5
26 add r6, r6, r4
/linux-4.1.27/arch/x86/crypto/
H A Daes-x86_64-asm_64.S52 #define prologue(FUNC,KEY,B128,B192,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11) \
55 movq r3,r4; \
73 #define epilogue(FUNC,r1,r2,r3,r4,r5,r6,r7,r8,r9) \
75 movq r3,r4; \
83 #define round(TAB,OFFSET,r1,r2,r3,r4,r5,r6,r7,r8,ra,rb,rc,rd) \
87 movw r4 ## X,r2 ## X; \
90 shrl $16,r4 ## E; \
91 movzbl r4 ## H,r7 ## E; \
92 movzbl r4 ## L,r4 ## E; \
96 xorl TAB+2048(,r4,4),r6 ## E;\
98 movzbl r1 ## H,r4 ## E; \
99 movl TAB+1024(,r4,4),r4 ## E;\
106 xorl TAB+3072(,r7,4),r4 ## E;\
121 xorl TAB+2048(,r7,4),r4 ## E;\
127 xorl TAB(,r2,4),r4 ## E;
129 #define move_regs(r1,r2,r3,r4) \
131 movl r4 ## E,r2 ## E;
H A Daes-i586-asm_32.S60 #define r4 esi define
81 // output registers r0, r1, r4 or r5.
151 // the first previous round column values in r0,r1,r4,r5 and
156 // on entry: r0,r1,r4,r5
157 // on exit: r2,r1,r4,r5
163 do_fcol(table, r2,r5,r4,r1, r0,r3, arg); /* idx=r0 */ \
164 do_col (table, r4,r1,r2,r5, r0,r3); /* idx=r4 */ \
166 do_col (table, r1,r2,r5,r4, r0,r3); /* idx=r1 */ \
168 do_col (table, r5,r4,r1,r2, r0,r3); /* idx=r5 */
171 // on entry: r2,r1,r4,r5
172 // on exit: r0,r1,r4,r5
178 do_fcol(table, r0,r5,r4,r1, r2,r3, arg); /* idx=r2 */ \
179 do_col (table, r4,r1,r0,r5, r2,r3); /* idx=r4 */ \
181 do_col (table, r1,r0,r5,r4, r2,r3); /* idx=r1 */ \
183 do_col (table, r5,r4,r1,r0, r2,r3); /* idx=r5 */
186 // the first previous round column values in r0,r1,r4,r5 and
191 // on entry: r0,r1,r4,r5
192 // on exit: r2,r1,r4,r5
198 do_icol(table, r2,r1,r4,r5, r0,r3, arg); /* idx=r0 */ \
199 do_col (table, r4,r5,r2,r1, r0,r3); /* idx=r4 */ \
201 do_col (table, r1,r4,r5,r2, r0,r3); /* idx=r1 */ \
203 do_col (table, r5,r2,r1,r4, r0,r3); /* idx=r5 */
206 // on entry: r2,r1,r4,r5
207 // on exit: r0,r1,r4,r5
213 do_icol(table, r0,r1,r4,r5, r2,r3, arg); /* idx=r2 */ \
214 do_col (table, r4,r5,r0,r1, r2,r3); /* idx=r4 */ \
216 do_col (table, r1,r4,r5,r0, r2,r3); /* idx=r1 */ \
218 do_col (table, r5,r0,r1,r4, r2,r3); /* idx=r5 */
246 mov 8(%r2),%r4
250 xor 8(%ebp),%r4
283 mov %r4,8(%ebp)
318 mov 8(%r2),%r4
322 xor 8(%ebp),%r4
355 mov %r4,8(%ebp)
/linux-4.1.27/arch/s390/kernel/vdso64/
H A Dclock_gettime.S36 0: lg %r4,__VDSO_UPD_COUNT(%r5) /* load update counter */
37 tmll %r4,0x0001 /* pending update ? loop */
47 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */
62 3: lg %r4,__VDSO_UPD_COUNT(%r5) /* load update counter */
63 tmll %r4,0x0001 /* pending update ? loop */
67 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */
72 4: lg %r4,__VDSO_UPD_COUNT(%r5) /* load update counter */
73 tmll %r4,0x0001 /* pending update ? loop */
77 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */
82 5: lg %r4,__VDSO_UPD_COUNT(%r5) /* load update counter */
83 tmll %r4,0x0001 /* pending update ? loop */
93 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */
111 llilh %r4,0x0100
112 sar %a4,%r4
113 lghi %r4,0
128 lgr %r4,%r1
135 slgr %r4,%r0 /* r4 = tv_nsec */
136 stg %r4,8(%r3)
H A Dgettimeofday.S29 lg %r4,__VDSO_UPD_COUNT(%r5) /* load update counter */
30 tmll %r4,0x0001 /* pending update ? loop */
38 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */
/linux-4.1.27/arch/sh/kernel/cpu/sh3/
H A Dswsusp.S20 #define k4 r4
28 mov.l 2f, r4
29 mov.l @r4, r4
32 mov r4, r0
36 mov.l @(PBE_ADDRESS, r4), r2
37 mov.l @(PBE_ORIG_ADDRESS, r4), r5
59 mov.l @(PBE_NEXT, r4), r4
76 mov.l @r15+, r4
110 mov #0, r4
113 not r4, r4
/linux-4.1.27/arch/ia64/kernel/
H A Drelocate_kernel.S194 add loc1=4*8, in0 // save r4 and r5 first
200 st8 [loc1]=r4, 8
205 mov r4=ar.rnat
208 st8 [loc1]=r4, 8 // rnat
213 mov r4=b0
216 st8 [loc1]=r4, 8 // b0
221 mov r4=b2
224 st8 [loc1]=r4, 8 // b2
229 mov r4=b4
232 st8 [loc1]=r4, 8 // b4
237 mov r4=b6
245 mov r4=b0
248 st8 [loc1]=r4, 8 // ip
253 mov r4=r0 // user mask
259 st8 [loc1]=r4, 8 // user mask
264 mov r4=ar.bsp
267 st8 [loc1]=r4, 8 // ar.bsp
272 mov r4=ar.rnat
275 st8 [loc1]=r4, 8 // ar.rnat
280 mov r4=ar.unat
283 st8 [loc1]=r4, 8 // ar.unat
288 mov r4 = ar.unat
291 st8 [loc1]=r4, 8 // unat
296 mov r4 = ar.pfs
299 st8 [loc1]=r4, 8 // ar.pfs
304 mov r4 = ar.ec
307 st8 [loc1]=r4, 8 // ar.ec
312 mov r4 = ar.ssd
315 st8 [loc1]=r4, 8 // ar.ssd
/linux-4.1.27/arch/openrisc/kernel/
H A Dhead.S54 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
55 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
85 #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
86 #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
140 * r4 - EEAR exception EA
174 /* r1: KSP, r10: current, r4: EEAR, r31: __pa(KSP) */ ;\
193 /* save exception r4, set r4 = EA */ ;\
194 l.sw PT_GPR4(r30),r4 ;\
195 l.mfspr r4,r0,SPR_EEAR_BASE ;\
275 /* save exception r4, set r4 = EA */ ;\
276 l.sw PT_GPR4(r31),r4 ;\
277 l.mfspr r4,r0,SPR_EEAR_BASE ;\
458 CLEAR_GPR(r4)
494 l.ori r4,r0,0x0
574 l.movhi r4,hi(OF_DT_HEADER)
575 l.ori r4,r4,lo(OF_DT_HEADER)
576 l.sfeq r3,r4
594 CLEAR_GPR(r4)
811 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
816 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
826 l.or r6,r6,r4 // r6 <- r4
835 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
837 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
839 tophys(r3,r4) // r3 <- PA
898 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
903 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
913 l.or r6,r6,r4 // r6 <- r4
928 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
930 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
932 tophys(r3,r4) // r3 <- PA
984 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
985 l.slli r4,r4,0x2 // to get address << 2
986 l.add r5,r4,r3 // r4 is pgd_index(daddr)
991 tophys (r4,r5)
992 l.lwz r3,0x0(r4) // get *pmd value
1005 // l.sw 0x0(r4),r0 // clear pmd
1010 l.lwz r4,0x0(r4) // get **pmd value
1011 l.and r4,r4,r3 // & PAGE_MASK
1015 l.add r3,r3,r4
1020 l.andi r4,r2,0x1
1021 l.sfne r4,r0 // is pte present
1027 l.and r4,r2,r3 // apply the mask
1037 l.mtspr r5,r4,SPR_DTLBTR_BASE(0)
1043 l.and r4,r2,r3 // apply PAGE_MASK to EA (__PHX__ do we really need this?)
1044 l.ori r4,r4,0x1 // set hardware valid bit: DTBL_MR entry
1045 l.mtspr r5,r4,SPR_DTLBMR_BASE(0)
1087 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1088 l.slli r4,r4,0x2 // to get address << 2
1089 l.add r5,r4,r3 // r4 is pgd_index(daddr)
1094 tophys (r4,r5)
1095 l.lwz r3,0x0(r4) // get *pmd value
1109 // l.sw 0x0(r4),r0 // clear pmd
1116 l.lwz r4,0x0(r4) // get **pmd value
1117 l.and r4,r4,r3 // & PAGE_MASK
1121 l.add r3,r3,r4
1127 l.andi r4,r2,0x1
1128 l.sfne r4,r0 // is pte present
1134 l.and r4,r2,r3 // apply the mask
1156 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1158 l.mtspr r5,r4,SPR_ITLBTR_BASE(0)
1164 l.and r4,r2,r3 // apply PAGE_MASK to EA (__PHX__ do we really need this?)
1165 l.ori r4,r4,0x1 // set hardware valid bit: DTBL_MR entry
1166 l.mtspr r5,r4,SPR_ITLBMR_BASE(0)
1218 LOAD_SYMBOL_2_GPR(r4,0x15000000)
1219 l.sw TRAMP_SLOT_0(r3),r4
1220 l.sw TRAMP_SLOT_1(r3),r4
1221 l.sw TRAMP_SLOT_4(r3),r4
1222 l.sw TRAMP_SLOT_5(r3),r4
1225 l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address)
1226 l.sw TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data
1227 l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address)
1228 l.sw TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data
1230 l.srli r5,r4,26 // check opcode for write access
1250 // r4 is instruction
1281 l.slli r6,r4,6 // original offset shifted left 6 - 2
1284 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1285 // l.srli r4,r4,6 // old jump position: shifted right 2
1293 l.sub r5,r4,r5 // old_jump - new_jump
1343 l.slli r6,r4,6 // original offset shifted left 6 - 2
1346 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1347 // l.srli r4,r4,6 // old jump position: shifted right 2
1355 l.add r6,r6,r4 // (orig_off + old_jump)
1360 l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction
1361 l.srli r4,r4,16
1362 l.andi r4,r4,0xfc00 // get opcode part
1363 l.slli r4,r4,16
1364 l.or r6,r4,r6 // l.b(n)f new offset
1368 tophys (r4,r2) // may not be needed (due to shifts down_
1369 l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8)
1371 l.sub r4,r4,r5 // jump offset = target - new_position + 0x8
1373 l.slli r4,r4,4 // the amount of info in imediate of jump
1374 l.srli r4,r4,6 // jump instruction with offset
1375 l.sw TRAMP_SLOT_4(r3),r4 // write it to 4th slot
1429 l.movhi r4,hi(UART_BASE_ADD)
1432 1: l.lbz r5,5(r4)
1438 l.sb 0(r4),r7
1441 1: l.lbz r5,5(r4)
1497 l.movhi r4,hi(UART_BASE_ADD)
1500 1: l.lbz r5,5(r4)
1506 l.sb 0(r4),r7
1509 1: l.lbz r5,5(r4)
1553 l.addi r4,r0,0x7
1554 l.sb 0x2(r3),r4
1556 l.addi r4,r0,0x0
1557 l.sb 0x1(r3),r4
1559 l.addi r4,r0,0x3
1560 l.sb 0x3(r3),r4
1563 l.ori r4,r5,0x80
1564 l.sb 0x3(r3),r4
1565 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1566 l.sb UART_DLM(r3),r4
1567 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
1568 l.sb UART_DLL(r3),r4
H A Dentry.S53 DISABLE_INTERRUPTS(r3,r4) ;\
60 l.lwz r4,PT_GPR4(r1) ;\
98 /* r4 already save */ ;\
169 /* r4 is exception EA */ ;\
181 * of r4 (for SPR_EEAR). for details look at EXCEPTION_HANDLE()
196 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
214 /* r4 set be EXCEPTION_HANDLE */ // effective address of fault
294 /* r4 set be EXCEPTION_HANDLE */ // effective address of fault
316 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
326 l.addi r2,r4,0
331 l.srli r4,r3,26 /* Shift left to get the insn opcode */
333 l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */
335 l.sfeqi r4,0x01
337 l.sfeqi r4,0x03
339 l.sfeqi r4,0x04
341 l.sfeqi r4,0x11
343 l.sfeqi r4,0x12
350 l.slli r4,r3,6 /* Get the signed extended jump length */
351 l.srai r4,r4,4
355 l.add r5,r5,r4 /* Calculate jump target address */
358 l.srli r4,r3,26 /* Shift left to get the insn opcode */
361 l.slli r4,r3,9 /* Shift to get the reg nb */
362 l.andi r4,r4,0x7c
366 l.add r4,r4,r1 /* Load the jump register value from the stack */
367 l.lwz r5,0(r4)
369 l.srli r4,r3,26 /* Shift left to get the insn opcode */
376 l.sfeqi r4,0x26
378 l.sfeqi r4,0x25
380 l.sfeqi r4,0x22
382 l.sfeqi r4,0x21
384 l.sfeqi r4,0x37
386 l.sfeqi r4,0x35
397 l.srli r4,r3,19
398 l.andi r4,r4,0x7c
399 l.add r4,r4,r1
401 l.sw 0(r4),r5
407 l.srli r4,r3,19
408 l.andi r4,r4,0x7c
409 l.add r4,r4,r1
411 l.sw 0(r4),r5
423 l.srli r4,r3,19
424 l.andi r4,r4,0x7c
425 l.add r4,r4,r1
427 l.sw 0(r4),r5
439 l.srli r4,r3,19
440 l.andi r4,r4,0x7c
441 l.add r4,r4,r1
443 l.sw 0(r4),r5
446 l.srli r4,r3,9
447 l.andi r4,r4,0x7c
448 l.add r4,r4,r1
449 l.lwz r5,0(r4)
456 l.srli r4,r3,9
457 l.andi r4,r4,0x7c
458 l.add r4,r4,r1
459 l.lwz r5,0(r4)
477 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
488 l.lwz r4,PT_SR(r1) // were interrupts enabled ?
489 l.andi r4,r4,SPR_SR_IEE
490 l.sfeqi r4,0
499 l.sw 0x4(r1),r4
508 l.ori r4,r4,SPR_SR_IEE // fix the bug
509 // l.sw PT_SR(r1),r4
559 /* r4 already saved */
560 /* r4 holds the EEAR address of the fault, load the original r4 */
561 l.lwz r4,PT_GPR4(r1)
700 l.lwz r4,PT_GPR4(r1)
746 l.lwz r4,PT_GPR4(r1)
779 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
857 DISABLE_INTERRUPTS(r3,r4)
858 l.lwz r4,TI_FLAGS(r10)
859 l.andi r13,r4,_TIF_WORK_MASK
888 l.lwz r4,PT_GPR4(r1)
902 l.lwz r4,PT_SR(r1)
903 l.andi r3,r4,SPR_SR_SM
1023 l.or r10,r4,r0 /* Set up new current_thread_info */
1124 l.lwz r29,0(r4)
1126 l.sw 0(r4),r27
/linux-4.1.27/arch/s390/kernel/vdso32/
H A Dclock_gettime.S35 1: l %r4,__VDSO_UPD_COUNT+4(%r5) /* load update counter */
36 tml %r4,0x0001 /* pending update ? loop */
59 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
78 9: l %r4,__VDSO_UPD_COUNT+4(%r5) /* load update counter */
79 tml %r4,0x0001 /* pending update ? loop */
83 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
88 10: l %r4,__VDSO_UPD_COUNT+4(%r5) /* load update counter */
89 tml %r4,0x0001 /* pending update ? loop */
93 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
98 11: l %r4,__VDSO_UPD_COUNT+4(%r5) /* load update counter */
99 tml %r4,0x0001 /* pending update ? loop */
122 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
H A Dgettimeofday.S30 l %r4,__VDSO_UPD_COUNT+4(%r5) /* load update counter */
31 tml %r4,0x0001 /* pending update ? loop */
52 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
54 l %r4,__VDSO_TK_SHIFT(%r5) /* Timekeeper shift */
55 srdl %r0,0(%r4) /* >> tk->shift */
56 l %r4,0(%r15) /* get tv_sec from stack */
62 7: ahi %r4,1
67 8: st %r4,0(%r2) /* store tv->tv_sec */
/linux-4.1.27/arch/nios2/include/asm/
H A Dswitch_to.h21 "mov r4, %1\n" \
24 "mov %0,r4\n" \
27 : "r4", "r5", "r7", "r8", "ra"); \
/linux-4.1.27/arch/parisc/kernel/
H A Dhpmc.S93 * r4 scratch
116 mfctl %cr14, %r4
117 ldw 52(%r4),%r5
119 stw %r5,52(%r4)
134 ldo 8(%r0),%r4 /* PSW Q on, PSW M off */
135 mtctl %r4,ipsw
138 load32 PA(os_hpmc_1),%r4
139 mtctl %r4,pcoq
140 ldo 4(%r4),%r4
141 mtctl %r4,pcoq
159 load32 HPMC_PIM_DATA_SIZE,%r4
160 stw %r4,-52(sp)
200 ldo PDC_IODC_RI_INIT(%r0),%r4
201 stw %r4,-52(sp)
202 load32 PA(hpmc_iodc_buf),%r4
203 stw %r4,-56(sp)
204 load32 HPMC_IODC_BUF_SIZE,%r4
205 stw %r4,-60(sp)
221 load32 PA(hpmc_raddr),%r4
222 stw %r4, -52(sp)
243 load32 PA(swapper_pg_dir),%r4
244 mtctl %r4,%cr24 /* Initialize kernel root pointer */
245 mtctl %r4,%cr25 /* Initialize user root pointer */
292 ldil L%0xfffc0000,%r4 /* IO_BROADCAST */
294 stw %r5,48(%r4) /* CMD_RESET to IO_COMMAND offset */
H A Dhead.S60 load32 PA(__bss_stop),%r4
62 cmpb,<<,n %r3,%r4,$bss_loop
73 load32 PA(swapper_pg_dir),%r4
74 mtctl %r4,%cr24 /* Initialize kernel root pointer */
75 mtctl %r4,%cr25 /* Initialize user root pointer */
82 stw %r3,ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4)
83 ldo ASM_PMD_ENTRY*ASM_PMD_ENTRY_SIZE(%r5),%r4
86 ldo ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4),%r4
97 stw %r3,0(%r4)
101 ldo ASM_PMD_ENTRY_SIZE(%r4),%r4
103 ldo ASM_PGD_ENTRY_SIZE(%r4),%r4
326 load32 PA(swapper_pg_dir),%r4
327 mtctl %r4,%cr24 /* Initialize kernel root pointer */
328 mtctl %r4,%cr25 /* Initialize user root pointer */
/linux-4.1.27/arch/s390/boot/compressed/
H A Dhead.S25 lgr %r4,%r2
27 la %r4,0(%r2,%r4)
37 mvcle %r2,%r4,0
/linux-4.1.27/arch/arm/mach-omap2/
H A Domap-headsmp.S38 mrc p15, 0, r4, c0, c0, 5
39 and r4, r4, #0x0f
40 cmp r0, r4
54 mrc p15, 0, r4, c0, c0, 5
55 and r4, r4, #0x0f
56 cmp r0, r4
76 mrc p15, 0, r4, c0, c0, 5
77 and r4, r4, #0x0f
78 cmp r0, r4
93 mrc p15, 0, r4, c0, c0, 5
94 and r4, r4, #0x0f
95 cmp r0, r4
H A Dsleep34xx.S103 stmfd sp!, {r4 - r11, lr} @ save registers on stack
122 ldmfd sp!, {r4 - r11, pc}
161 stmfd sp!, {r4 - r11, lr} @ save registers on stack
175 ldr r4, omap3_do_wfi_sram_addr
176 ldr r5, [r4]
236 ldr r4, sdrc_power @ read the SDRC_POWER register
237 ldr r5, [r4] @ read the contents of SDRC_POWER
239 str r5, [r4] @ write back to SDRC_POWER register
282 ldr r4, cm_idlest_ckgen
284 ldr r5, [r4]
288 ldr r4, cm_idlest1_core
290 ldr r5, [r4]
294 ldr r4, sdrc_power
295 ldr r5, [r4]
297 str r5, [r4]
301 ldr r4, sdrc_dlla_ctrl
302 ldr r5, [r4]
307 ldr r4, sdrc_dlla_status
313 ldr r5, [r4]
321 ldr r4, sdrc_dlla_ctrl
322 ldr r5, [r4]
325 str r6, [r4]
328 str r6, [r4]
345 ldmfd sp!, {r4 - r11, pc} @ restore regs and return
382 ldr r4, [r5]
383 and r4, r4, #0x3
384 cmp r4, #0x0 @ Check if previous power state of CORE is OFF
456 ldr r4, scratchpad_base
457 ldr r3, [r4, #0xBC] @ r3 points to parameters
470 ldr r4, scratchpad_base
471 ldr r3, [r4, #0xBC]
487 ldr r4, scratchpad_base
488 ldr r3, [r4,#0xBC]
492 ldr r4, scratchpad_base
493 ldr r3, [r4,#0xBC]
551 ldr r4, sdrc_syscfg @ get config addr
552 ldr r5, [r4] @ get value
556 str r5, [r4] @ write back change
557 ldr r4, sdrc_mr_0 @ get config addr
558 ldr r5, [r4] @ get value
559 str r5, [r4] @ write back change
560 ldr r4, sdrc_emr2_0 @ get config addr
561 ldr r5, [r4] @ get value
562 str r5, [r4] @ write back change
563 ldr r4, sdrc_manual_0 @ get config addr
565 str r5, [r4] @ kick off refreshes
566 ldr r4, sdrc_mr_1 @ get config addr
567 ldr r5, [r4] @ get value
568 str r5, [r4] @ write back change
569 ldr r4, sdrc_emr2_1 @ get config addr
570 ldr r5, [r4] @ get value
571 str r5, [r4] @ write back change
572 ldr r4, sdrc_manual_1 @ get config addr
574 str r5, [r4] @ kick off refreshes
H A Dsram242x.S100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
102 subs r4, r4, #0x1
111 ldr r4, omap242x_sdi_prcm_voltctrl @ get addr of volt ctrl.
112 ldr r5, [r4] @ get value.
116 str r5, [r4] @ set up for change.
119 str r5, [r4] @ Force transition to L1
169 ldr r4, omap242x_srs_cm_clksel2_pll @ get address of out reg
170 ldr r3, [r4] @ get curr value
174 str r3, [r4] @ set new state (pll/x, x=1 or 2)
247 adr r4, pbegin @ addr of preload start
249 mcrr p15, 1, r8, r4, c12 @ preload into icache
258 ldr r4, omap242x_ssp_pll_stat @ addr of stat
261 ldr r8, [r4] @ stat value
267 ldr r4, omap242x_ssp_pll_div @ get addr
268 str r0, [r4] @ set dpll ctrl val
270 ldr r4, omap242x_ssp_set_config @ get addr
272 str r8, [r4] @ make dividers take
274 mov r4, #100 @ dead spin a bit
276 subs r4, r4, #1 @ dec loop
285 ldr r4, omap242x_ssp_pll_ctl @ get addr
287 str r8, [r4] @ set val
299 ldr r4, omap242x_ssp_sdrc_rfr @ get addr
300 str r1, [r4] @ update refresh timing
310 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
312 subs r4, r4, #0x1
H A Dsram243x.S100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
102 subs r4, r4, #0x1
111 ldr r4, omap243x_sdi_prcm_voltctrl @ get addr of volt ctrl.
112 ldr r5, [r4] @ get value.
116 str r5, [r4] @ set up for change.
119 str r5, [r4] @ Force transition to L1
169 ldr r4, omap243x_srs_cm_clksel2_pll @ get address of out reg
170 ldr r3, [r4] @ get curr value
174 str r3, [r4] @ set new state (pll/x, x=1 or 2)
247 adr r4, pbegin @ addr of preload start
249 mcrr p15, 1, r8, r4, c12 @ preload into icache
258 ldr r4, omap243x_ssp_pll_stat @ addr of stat
261 ldr r8, [r4] @ stat value
267 ldr r4, omap243x_ssp_pll_div @ get addr
268 str r0, [r4] @ set dpll ctrl val
270 ldr r4, omap243x_ssp_set_config @ get addr
272 str r8, [r4] @ make dividers take
274 mov r4, #100 @ dead spin a bit
276 subs r4, r4, #1 @ dec loop
285 ldr r4, omap243x_ssp_pll_ctl @ get addr
287 str r8, [r4] @ set val
299 ldr r4, omap243x_ssp_sdrc_rfr @ get addr
300 str r1, [r4] @ update refresh timing
310 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
312 subs r4, r4, #0x1
H A Dsleep24xx.S72 ldr r4, [r2] @ read SDRC_POWER
73 orr r4, r4, #0x40 @ enable self refresh on idle req
75 str r4, [r2] @ make it so
84 bic r4, r4, #0x40 @ now clear self refresh bit.
85 str r4, [r2] @ write to SDRC_POWER
86 ldr r4, A_SDRC0 @ make a clock happen
87 ldr r4, [r4] @ read A_SDRC0
H A Dsram34xx.S138 ldr r4, [sp, #52]
139 strtext r4, omap_sdrc_rfr_ctrl_0_val
140 ldr r4, [sp, #56]
141 strtext r4, omap_sdrc_actim_ctrl_a_0_val
142 ldr r4, [sp, #60]
143 strtext r4, omap_sdrc_actim_ctrl_b_0_val
144 ldr r4, [sp, #64]
145 strtext r4, omap_sdrc_mr_0_val
146 ldr r4, [sp, #68]
147 strtext r4, omap_sdrc_rfr_ctrl_1_val
148 cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
150 ldr r4, [sp, #72]
151 strtext r4, omap_sdrc_actim_ctrl_a_1_val
152 ldr r4, [sp, #76]
153 strtext r4, omap_sdrc_actim_ctrl_b_1_val
154 ldr r4, [sp, #80]
155 strtext r4, omap_sdrc_mr_1_val
/linux-4.1.27/arch/arm/kernel/
H A Dhead.S110 ldmia r3, {r4, r8}
111 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
112 add r8, r8, r4 @ PHYS_OFFSET
140 mov r8, r4 @ set TTBR1 to swapper_pg_dir
161 * r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h)
164 pgtbl r4, r8 @ page table address
169 mov r0, r4
184 mov r0, r4
185 add r3, r4, #0x1000 @ first PMD table address
201 add r4, r4, #0x1000 @ point to the PMD tables
203 add r4, r4, #4 @ we only write the bottom word
222 str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping
230 add r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
233 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
247 add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
251 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
266 addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
273 sub r4, r4, #4 @ Fixup page table pointer
289 add r0, r4, r3
317 add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
327 add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
330 add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
335 sub r4, r4, #0x1000 @ point to the PGD table
336 mov r4, r4, lsr #ARCH_PGD_SHIFT
381 adr r4, __secondary_data
382 ldmia r4, {r5, r7, r12} @ address to jump to after
383 sub lr, r4, r5 @ mmu has been enabled
384 ldr r4, [r7, lr] @ get secondary_data.pgdir
424 * r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h)
449 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
493 mov r4, #0x41000000
494 orr r4, r4, #0x0000b000
495 orr r4, r4, #0x00000020 @ val 0x4100b020
496 teq r3, r4 @ ARM 11MPCore?
506 mov r4, #0x41000000
507 orr r4, r4, #0x0000c000
508 orr r4, r4, #0x00000090
509 teq r3, r4 @ Check for ARM Cortex-A9
528 add r4, r4, r3
548 cmp r4, r5
550 ldmia r4!, {r0, r6}
563 stmfd sp!, {r4 - r6, lr}
564 mov r4, r0
568 ldmfd sp!, {r4 - r6, pc}
592 add r4, r4, r3 @ adjust table start address
652 2: cmp r4, r5
653 ldrcc r7, [r4], #4 @ use branch for delay slot
679 2: cmp r4, r5
680 ldrcc r7, [r4], #4 @ use branch for delay slot
690 stmfd sp!, {r4 - r7, lr}
692 mov r4, r0 @ r0 = table start
695 ldmfd sp!, {r4 - r7, pc}
H A Dhead-common.S84 ldmia r3!, {r4, r5, r6, r7}
85 cmp r4, r5 @ Copy data segment if needed
87 ldrne fp, [r4], #4
96 ARM( ldmia r3, {r4, r5, r6, r7, sp})
97 THUMB( ldmia r3, {r4, r5, r6, r7} )
99 str r9, [r4] @ Save processor ID
110 .long __data_loc @ r4
114 .long processor_id @ r4
129 stmfd sp!, {r4 - r6, r9, lr}
133 ldmfd sp!, {r4 - r6, r9, pc}
148 * r3, r4, r6 corrupted
154 ldmia r3, {r4 - r6}
155 sub r3, r3, r4 @ get offset between virt&phys
158 1: ldmia r5, {r3, r4} @ value, mask
159 and r4, r4, r9 @ mask wanted bits
160 teq r3, r4
H A Dentry-armv.S52 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
68 @ r4 - aborted context pc
129 ldmia r0, {r4 - r6}
132 str r4, [sp] @ save preserved r0
180 @ r4 - lr_<exception>, already fixed up for correct return/restart
265 ldr r0, [r4, #-4]
268 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
271 ldrh r9, [r4] @ bottom 16 bits
272 add r4, r4, #2
273 str r4, [sp, #S_PC]
277 mov r2, r4
391 @ r4 - lr_<exception>, already fixed up for correct return/restart
397 stmia r0, {r4 - r6}
428 cmp r4, #TASK_SIZE
461 mov r2, r4
481 sub r4, r2, #4 @ ARM instr at LR - 4
482 1: ldrt r0, [r4]
487 @ r4 = PC value for the faulting instruction
494 sub r4, r2, #2 @ First half of thumb instr at LR - 2
516 2: ldrht r5, [r4]
528 @ r4 = PC value for the first 16-bit Thumb instruction
550 4: str r4, [sp, #S_PC] @ retry current instruction
691 ldr r4, .LCfp
693 ldr pc, [r4] @ Call FP module USR entry point
764 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
765 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
768 ldr r4, [r2, #TI_TP_VALUE]
773 switch_tls r1, r4, r5, r3, r7
783 add r4, r2, #TI_CPU_SAVE
790 THUMB( mov ip, r4 )
792 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
793 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
859 stmfd sp!, {r4, r5, r6, r7}
860 ldrd r4, r5, [r0] @ load old val
864 eors r3, r0, r4 @ compare with oldval (1)
871 ldmfd sp!, {r4, r5, r6, r7}
884 stmfd sp!, {r4, r5, r6, lr}
885 ldmia r0, {r4, r5} @ load old val
888 eors r3, r0, r4 @ compare with oldval (1)
892 ldmfd sp!, {r4, r5, r6, pc}
897 @ r4 = address of interrupted insn (must be preserved).
900 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
903 subs r8, r4, r7
968 @ r4 = address of interrupted insn (must be preserved).
971 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
974 subs r8, r4, r7
H A Diwmmxt.S197 stmfd sp!, {r4, lr}
213 XSC(mrc p15, 0, r4, c15, c1, 0)
214 XSC(orr r4, r4, #0x3)
215 XSC(mcr p15, 0, r4, c15, c1, 0)
216 PJ4(mrc p15, 0, r4, c1, c0, 2)
217 PJ4(orr r4, r4, #0xf)
218 PJ4(mcr p15, 0, r4, c1, c0, 2)
227 XSC(bic r4, r4, #0x3)
228 XSC(mcr p15, 0, r4, c15, c1, 0)
229 PJ4(bic r4, r4, #0xf)
230 PJ4(mcr p15, 0, r4, c1, c0, 2)
236 ldmfd sp!, {r4, pc}
H A Drelocate_kernel.S26 /* Is it a destination page. Put destination address to r4 */
29 bic r4,r3,#1
52 str r5,[r4],#4
H A Dentry-v7m.S72 @ return. r4-r7 were not clobbered in v7m_exception_entry so for
103 stmia ip!, {r4 - r11} @ Store most regs on stack
107 add r4, r2, #TI_CPU_SAVE
111 mov ip, r4
113 ldmia ip!, {r4 - r11} @ Load all regs saved previously
H A Dsleep.S61 stmfd sp!, {r4 - r11, lr}
64 ldr r4, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
66 ldr r4, =cpu_suspend_size
69 add r4, r4, #12 @ Space for pgd, virt sp, phys resume fn
70 sub sp, sp, r4 @ allocate CPU state on stack
81 mov r1, r4 @ size of save block
94 ldmfd sp!, {r4 - r11, pc}
116 ldmfd sp!, {r4 - r11, pc}
137 ldmia r2, { r3-r6 } @ r3 = mpidr mask (r4,r5,r6) = l[0,1,2] shifts
138 compute_mpidr_hash r1, r4, r5, r6, r0, r3
/linux-4.1.27/arch/arm/mach-sa1100/
H A Dsleep.S37 ldr r4, [r6]
38 orr r4, r4, #MDREFR_K1DB2
51 str r4, [r6]
69 * r4 = MSC1 value
89 ldr r4, [r1]
90 bic r4, r4, #FMsk(MSC_RT)
91 bic r4, r4, #FMsk(MSC_RT)<<16
121 str r4, [r1]
/linux-4.1.27/arch/microblaze/kernel/
H A Dmisc.S78 lwi r4, r0, tlb_skip
79 mts rtlbx, r4 /* TLB slot 63 */
81 or r4,r5,r0
82 andi r4,r4,0xfffff000
83 ori r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G)
88 mts rtlblo,r4 /* Load the data portion of the entry */
H A Dhw_exception_handler.S44 * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore
92 lwi r4, r1, PT_R4; \
338 swi r4, r1, PT_R4
351 mfs r4, resr
357 andi r5, r4, 0x1000; /* Check ESR[DS] */
365 andi r5, r4, 0x1F; /* Extract ESR[EXC] */
416 andi r6, r4, 0x1F; /* Load ESR[EC] */
470 andi r6, r4, 0x1000 /* Check ESR[DS] */
479 andi r6, r4, 0x3E0; /* Mask and extract the register operand */
488 andi r6, r4, 0x400; /* Extract ESR[S] */
491 andi r6, r4, 0x800; /* Extract ESR[W] */
503 /* Get the destination register value into r4 */
504 lwi r4, r0, TOPHYS(ex_tmp_data_loc_0);
513 /* Get the destination register value into r4 */
514 lhui r4, r0, TOPHYS(ex_tmp_data_loc_0);
542 swi r4, r0, TOPHYS(ex_tmp_data_loc_0);
544 lbui r4, r0, TOPHYS(ex_tmp_data_loc_0);
545 sbi r4, r3, 0;
546 lbui r4, r0, TOPHYS(ex_tmp_data_loc_1);
547 sbi r4, r3, 1;
548 lbui r4, r0, TOPHYS(ex_tmp_data_loc_2);
549 sbi r4, r3, 2;
550 lbui r4, r0, TOPHYS(ex_tmp_data_loc_3);
551 sbi r4, r3, 3;
556 swi r4, r0, TOPHYS(ex_tmp_data_loc_0);
557 lbui r4, r0, TOPHYS(ex_tmp_data_loc_2);
558 sbi r4, r3, 0;
559 lbui r4, r0, TOPHYS(ex_tmp_data_loc_3);
560 sbi r4, r3, 1;
569 lwi r4, r1, PT_R4
610 andi r4, r4, ESR_DIZ /* ESR_Z - zone protection */
611 bnei r4, ex2
613 ori r4, r0, swapper_pg_dir
624 andi r4, r4, ESR_DIZ /* ESR_Z */
625 bnei r4, ex2
627 addi r4 ,CURRENT_TASK, TOPHYS(0);
628 lwi r4, r4, TASK_THREAD+PGDIR
630 tophys(r4,r4)
634 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
635 or r4, r4, r5
636 lwi r4, r4, 0 /* Get L1 entry */
637 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
644 lwi r4, r5, 0 /* Get Linux PTE */
646 andi r6, r4, _PAGE_RW /* Is it writeable? */
650 ori r4, r4, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
651 swi r4, r5, 0 /* Update Linux page table */
662 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
664 ori r4, r4, _PAGE_HWEXEC /* make it executable */
671 mts rtlblo, r4 /* Load TLB LO */
718 cmpu r4, r3, r6
719 bgti r4, ex5
720 ori r4, r0, swapper_pg_dir
728 addi r4 ,CURRENT_TASK, TOPHYS(0);
729 lwi r4, r4, TASK_THREAD+PGDIR
731 tophys(r4,r4)
735 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
736 or r4, r4, r5
737 lwi r4, r4, 0 /* Get L1 entry */
738 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
745 lwi r4, r5, 0 /* Get Linux PTE */
747 andi r6, r4, _PAGE_PRESENT
750 ori r4, r4, _PAGE_ACCESSED
751 swi r4, r5, 0
762 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
788 ori r4, r0, CONFIG_KERNEL_START
789 cmpu r4, r3, r4
790 bgti r4, ex8
791 ori r4, r0, swapper_pg_dir
799 addi r4 ,CURRENT_TASK, TOPHYS(0);
800 lwi r4, r4, TASK_THREAD+PGDIR
802 tophys(r4,r4)
806 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
807 or r4, r4, r5
808 lwi r4, r4, 0 /* Get L1 entry */
809 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
816 lwi r4, r5, 0 /* Get Linux PTE */
818 andi r6, r4, _PAGE_PRESENT
821 ori r4, r4, _PAGE_ACCESSED
822 swi r4, r5, 0
833 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
847 * r4 - TLB LO (info from Linux PTE)
877 ori r4, r4, _PAGE_HWEXEC /* make it executable */
880 mts rtlblo, r4 /* MS: save to TLB LO */
956 load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */
960 load2: lbui r5, r4, 1;
962 load3: lbui r5, r4, 2;
964 load4: lbui r5, r4, 3;
974 load5: lbui r5, r4, 1;
993 store1: sbi r3, r4, 0;
995 store2: sbi r3, r4, 1;
997 store3: sbi r3, r4, 2;
1000 store4: sbi r3, r4, 3; /* Delay slot */
1005 store5: sbi r3, r4, 0;
1008 store6: sbi r3, r4, 1; /* Delay slot */
1011 store5: sbi r3, r4, 0;
1014 store6: sbi r3, r4, 1; /* Delay slot */
H A Dhead.S101 ori r4, r0, TOPHYS(_fdt_start)
105 sw r12, r4, r11 /* addr[r4 + r11] = r12 */
120 ori r4, r0, cmd_line /* load address of command line */
121 tophys(r4,r4) /* convert to phys address */
127 sb r2, r4, r11 /* addr[r4+r6]= r2 */
131 addik r5, r4, 0 /* add new space for command line */
139 ori r4, r0, TOPHYS(_bram_load_start) /* save bram context */
143 sw r7, r4, r11 /* addr[r4 + r6] = r7 */
178 tophys(r4,r3) /* Load the kernel physical address */
233 andi r4,r4,0xfffffc00 /* Mask off the real page number */
234 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
265 mts rtlblo,r4 /* Load the data portion of the entry */
287 addk r4, r4, r9 /* previous addr + TLB0 size */
297 mts rtlblo,r4 /* Load the data portion of the entry */
313 ori r4,r0,(TLB_WR | TLB_EX)
316 mts rtlblo,r4 /* Load the data portion of the entry */
325 ori r4,r0,MSR_KERNEL_VMS
326 mts rmsr,r4
370 ori r4,r0,MSR_KERNEL
371 mts rmsr,r4
386 ori r4, r0, MSR_KERNEL_VMS
387 mts rmsr, r4
/linux-4.1.27/arch/powerpc/platforms/pseries/
H A DhvCall.S38 std r4,STK_PARAM(R4)(r1); \
46 addi r4,r1,STK_PARAM(FIRST_REG); \
50 ld r4,STACK_FRAME_OVERHEAD+STK_PARAM(R4)(r1); \
65 mr r4,r3; \
138 std r4,STK_PARAM(R4)(r1) /* Save ret buffer */
140 mr r4,r5
150 std r4, 0(r12)
164 std r4,STK_PARAM(R4)(r1)
165 mr r0,r4
167 mr r4,r5
177 std r4,0(r12)
202 std r4,STK_PARAM(R4)(r1) /* Save ret buffer */
204 mr r4,r5
214 std r4, 0(r12)
232 std r4,STK_PARAM(R4)(r1) /* Save ret buffer */
234 mr r4,r5
248 std r4, 0(r12)
267 std r4,STK_PARAM(R4)(r1)
268 mr r0,r4
270 mr r4,r5
284 std r4,0(r12)
309 std r4,STK_PARAM(R4)(r1) /* Save ret buffer */
311 mr r4,r5
325 std r4, 0(r12)
/linux-4.1.27/arch/arm/mach-shmobile/include/mach/
H A Dzboot_macros.h84 LDR r4, 1f variable
86 LDR r6, [r4]
88 STR r5, [r4]
97 LDR r4, 1f variable
99 LDR r6, [r4]
101 STR r5, [r4]
/linux-4.1.27/arch/powerpc/platforms/ps3/
H A Dhvcall.S62 std r4, 0(r11); \
75 stdu r4, -16(r1); \
82 std r4, 0(r11); \
97 std r4, -16(r1); \
105 std r4, 0(r11); \
122 std r4, -16(r1); \
134 std r4, 0(r11); \
158 stdu r4, -8(r1); \
165 std r4, 0(r11); \
177 std r4, -8(r1); \
185 std r4, 0(r11); \
199 std r4, -8(r1); \
208 std r4, 0(r11); \
224 std r4, -8(r1); \
234 std r4, 0(r11); \
252 std r4, -8(r1); \
263 std r4, 0(r11); \
283 std r4, -8(r1); \
295 std r4, 0(r11); \
317 std r4, -8(r1); \
330 std r4, 0(r11); \
361 std r4, 0(r11); \
381 std r4, 0(r11); \
404 std r4, 0(r11); \
430 std r4, 0(r11); \
459 std r4, 0(r11); \
486 std r4, 0(r11); \
506 std r4, 0(r11); \
529 std r4, 0(r11); \
552 std r4, 0(r11); \
572 std r4, 0(r11); \
595 std r4, 0(r11); \
618 std r4, 0(r11); \
638 std r4, 0(r11); \
661 std r4, 0(r11); \
684 std r4, 0(r11); \
704 std r4, 0(r11); \
726 std r4, 0(r11); \
749 std r4, 0(r11); \
767 std r4, 0(r11); \
793 std r4, 0(r11); \
/linux-4.1.27/arch/arm/kvm/
H A Dinterrupts_head.S30 VFPFMRX r4, FPINST
48 VFPFMXR FPINST, r4
66 mrs r4, SPSR_\mode
67 push {r2, r3, r4}
80 push {r4-r12} @ r0-r3 are always clobbered
93 mrs r4, r10_fiq
103 pop {r2, r3, r4}
106 msr SPSR_\mode, r4
117 msr r10_fiq, r4
132 pop {r4-r12}
144 * Clobbers r1, r2, r3, r4.
148 ldm r1, {r2, r3, r4}
151 msr SPSR_\mode, r4
171 msr r10_fiq, r4
199 * Clobbers r2, r3, r4, r5.
204 mrs r4, LR_\mode
206 stm r2, {r3, r4, r5}
215 * Clobbers r2, r3, r4, r5.
222 pop {r3, r4, r5} @ r0, r1, r2
223 stm r2, {r3, r4, r5}
253 mrc p15, 0, r4, c2, c0, 2 @ TTBCR
266 str r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
279 mrc p15, 0, r4, c13, c0, 3 @ TID_URO
294 str r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
306 mrrc p15, 0, r4, r5, c7 @ PAR
311 push {r2,r4-r7}
315 strd r4, r5, [r12]
330 pop {r2,r4-r7}
334 ldrd r4, r5, [r12]
340 mcrr p15, 0, r4, r5, c7 @ PAR
349 ldr r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
362 mcr p15, 0, r4, c13, c0, 3 @ TID_URO
377 ldr r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
390 mcr p15, 0, r4, c2, c0, 2 @ TTBCR
416 ldr r4, [r2, #GICH_VMCR]
424 ARM_BE8(rev r4, r4 )
433 str r4, [r11, #VGIC_V2_CPU_VMCR]
455 ldr r4, [r11, #VGIC_CPU_NR_LR]
459 subs r4, r4, #1
481 ldr r4, [r11, #VGIC_V2_CPU_VMCR]
484 ARM_BE8(rev r4, r4 )
488 str r4, [r2, #GICH_VMCR]
494 ldr r4, [r11, #VGIC_CPU_NR_LR]
498 subs r4, r4, #1
514 ldr r4, [vcpu, #VCPU_KVM]
515 ldr r2, [r4, #KVM_TIMER_ENABLED]
525 ldr r4, =VCPU_TIMER_CNTV_CVAL
526 add r5, vcpu, r4
558 ldr r4, [vcpu, #VCPU_KVM]
559 ldr r2, [r4, #KVM_TIMER_ENABLED]
563 ldr r2, [r4, #KVM_TIMER_CNTVOFF]
564 ldr r3, [r4, #(KVM_TIMER_CNTVOFF + 4)]
567 ldr r4, =VCPU_TIMER_CNTV_CVAL
568 add r5, vcpu, r4
/linux-4.1.27/arch/nios2/mm/
H A Duaccess.c17 " mov r3,r4\n"
19 " xor r2,r4,r5\n"
38 "4: andi r2,r4,1\n"
58 " addi r3,r4,1\n"
59 " stb r2,0(r4)\n"
75 " mov r3,r4\n"
77 " xor r2,r4,r5\n"
98 "4: andi r2,r4,1\n"
120 " addi r3,r4,1\n"
121 "12: stb r2,0(r4)\n"
/linux-4.1.27/arch/m32r/boot/compressed/
H A Dhead.S72 mv r4, r3 || ldi r1, #0
73 srli r4, #4 || addi r2, #-4
74 beqz r4, .Lendloop1
80 st r1, @+r2 || addi r4, #-1
83 st r1, @+r2 || cmpeq r1, r4 ; R4 = 0?
86 and3 r4, r3, #15
88 beqz r4, .Lendloop2
90 stb r1, @r2 || addi r4, #-1
92 bnez r4, .Lloop2
103 mv r4, r3
104 srli r4, #2 ; R4 = BSS size in longwords (rounded down)
107 beqz r4, .Lendloop1 ; any more to go?
110 addi r4, #-1 ; decrement count
111 bnez r4, .Lloop1 ; go do some more
/linux-4.1.27/arch/arm/boot/bootp/
H A Dinit.S25 ldmia r13!, {r4-r6} @ r5 = dest, r6 = length
26 add r4, r4, lr @ r4 = initrd_start + load addr
46 movne r4, #2 @ Size of this entry (2 words)
47 stmneia r9, {r4, r5, r10} @ Size, ATAG_CORE, terminator
64 * Move the block of memory length r6 from address r4 to address r5
66 move: ldmia r4!, {r7 - r10} @ move 32-bytes at a time
68 ldmia r4!, {r7 - r10}
/linux-4.1.27/arch/arm/vfp/
H A Dentry.S28 inc_preempt_count r10, r4
29 ldr r4, .LCvfp
32 ldr pc, [r4] @ call VFP entry point
36 dec_preempt_count_ti r10, r4
49 dec_preempt_count_ti r10, r4
/linux-4.1.27/arch/avr32/lib/
H A Dcsum_partial_copy_generic.S38 pushm r4-r7,lr
55 popm r4-r7,pc
59 mov r4, 32
63 sub r4, 8
68 lsl r5, r5, r4
/linux-4.1.27/arch/sh/include/asm/
H A Dtraps_32.h24 "mov r4, %0\n\t" \
45 asmlinkage void do_divide_error(unsigned long r4);
51 asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
/linux-4.1.27/arch/powerpc/include/asm/
H A Dfsl_hcalls.h129 register uintptr_t r4 __asm__("r4"); fh_partition_get_dtprop()
141 r4 = dtpath_addr >> 32; fh_partition_get_dtprop()
145 r4 = 0; fh_partition_get_dtprop()
156 "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7), fh_partition_get_dtprop()
161 *propvalue_len = r4; fh_partition_get_dtprop()
183 register uintptr_t r4 __asm__("r4"); fh_partition_set_dtprop()
195 r4 = dtpath_addr >> 32; fh_partition_set_dtprop()
199 r4 = 0; fh_partition_set_dtprop()
210 "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7), fh_partition_set_dtprop()
260 register uintptr_t r4 __asm__("r4"); fh_partition_get_status()
266 : "+r" (r11), "+r" (r3), "=r" (r4) fh_partition_get_status()
270 *status = r4; fh_partition_get_status()
290 register uintptr_t r4 __asm__("r4"); fh_partition_start()
295 r4 = entry_point; fh_partition_start()
299 : "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5) fh_partition_start()
362 register uintptr_t r4 __asm__("r4"); fh_partition_memcpy()
369 r4 = target; fh_partition_memcpy()
381 "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7) fh_partition_memcpy()
445 register uintptr_t r4 __asm__("r4"); fh_vmpic_get_msir()
451 : "+r" (r11), "+r" (r3), "=r" (r4) fh_vmpic_get_msir()
455 *msir_val = r4; fh_vmpic_get_msir()
488 * platform error data is returned in registers r4 - r11
497 register uintptr_t r4 __asm__("r4"); fh_err_get_info()
504 r4 = *bufsize; fh_err_get_info()
510 : "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), fh_err_get_info()
515 *bufsize = r4; fh_err_get_info()
539 register uintptr_t r4 __asm__("r4"); fh_get_core_state()
543 r4 = vcpu; fh_get_core_state()
546 : "+r" (r11), "+r" (r3), "+r" (r4) fh_get_core_state()
550 *state = r4; fh_get_core_state()
569 register uintptr_t r4 __asm__("r4"); fh_enter_nap()
573 r4 = vcpu; fh_enter_nap()
576 : "+r" (r11), "+r" (r3), "+r" (r4) fh_enter_nap()
594 register uintptr_t r4 __asm__("r4"); fh_exit_nap()
598 r4 = vcpu; fh_exit_nap()
601 : "+r" (r11), "+r" (r3), "+r" (r4) fh_exit_nap()
H A Depapr_hcalls.h103 #define EV_HCALL_CLOBBERS1 EV_HCALL_CLOBBERS2, "r4"
141 register uintptr_t r4 __asm__("r4"); ev_int_set_config()
147 r4 = config; ev_int_set_config()
152 : "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6) ev_int_set_config()
173 register uintptr_t r4 __asm__("r4"); ev_int_get_config()
181 : "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5), "=r" (r6) ev_int_get_config()
185 *config = r4; ev_int_get_config()
204 register uintptr_t r4 __asm__("r4"); ev_int_set_mask()
208 r4 = mask; ev_int_set_mask()
211 : "+r" (r11), "+r" (r3), "+r" (r4) ev_int_set_mask()
230 register uintptr_t r4 __asm__("r4"); ev_int_get_mask()
236 : "+r" (r11), "+r" (r3), "=r" (r4) ev_int_get_mask()
240 *mask = r4; ev_int_get_mask()
287 register uintptr_t r4 __asm__("r4"); ev_byte_channel_send()
296 r4 = *count; ev_byte_channel_send()
304 "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7), "+r" (r8) ev_byte_channel_send()
308 *count = r4; ev_byte_channel_send()
330 register uintptr_t r4 __asm__("r4"); ev_byte_channel_receive()
339 r4 = *count; ev_byte_channel_receive()
342 : "+r" (r11), "+r" (r3), "+r" (r4), ev_byte_channel_receive()
347 *count = r4; ev_byte_channel_receive()
373 register uintptr_t r4 __asm__("r4"); ev_byte_channel_poll()
380 : "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5) ev_byte_channel_poll()
384 *rx_count = r4; ev_byte_channel_poll()
407 register uintptr_t r4 __asm__("r4"); ev_int_iack()
413 : "+r" (r11), "+r" (r3), "=r" (r4) ev_int_iack()
417 *vector = r4; ev_int_iack()
471 unsigned long register r4 asm("r4") = in[1]; epapr_hypercall()
482 : "=r"(r0), "=r"(r3), "=r"(r4), "=r"(r5), "=r"(r6), epapr_hypercall()
485 : "r"(r3), "r"(r4), "r"(r5), "r"(r6), "r"(r7), "r"(r8), epapr_hypercall()
489 out[0] = r4; epapr_hypercall()
H A Dftrace.h15 stw r4, 16(r1); \
19 lwz r4, 52(r1); \
33 lwz r4, 16(r1); \
/linux-4.1.27/arch/sh/kernel/
H A Drelocate_kernel.S18 /* r4 = indirection_page */
53 mov.l r4, @-r15
68 mov.l r4, @-r15
74 mov.l r4, @-r15 /* save indirection page again */
86 mov.l @r15+, r4 /* restore r4 to get indirection page */
101 mov.l @r15+, r4
115 mov.l @r15+, r4
150 mov r4,r0 /* cmd = indirection_page */
152 mov.l @r4+,r0 /* cmd = *ind++ */
169 mov r2,r4
/linux-4.1.27/arch/tile/kernel/
H A Dhead_64.S74 moveli r4, hw1_last(swapper_pgprot - PAGE_OFFSET)
77 shl16insli r4, r4, hw0(swapper_pgprot - PAGE_OFFSET)
80 ld r1, r4 /* access_pte for hv_install_context */
89 finv r4
147 GET_SECOND_INT(r4, r0) /* r4 = y */
151 mul_lu_lu r4, r4, r5
154 add r4, r4, r6 /* r4 == cpu == y*width + x */
169 shl3add r5, r4, r5
205 shli r4, r4, CPU_SHIFT
206 bfins r4, sp, 0, CPU_SHIFT-1
207 mtspr SPR_SYSTEM_SAVE_K_0, r4 /* save ksp0 + cpu */
H A Dhead_32.S52 move r4, r0 /* use starting ASID of range for this page table */
82 mulll_uu r4, r1, r2 /* r1 == y, r2 == width */
83 add r4, r4, r0 /* r0 == x, so r4 == cpu == y*width + x */
96 s2a r5, r4, r5
127 or r4, sp, r4
128 mtspr SPR_SYSTEM_SAVE_K_0, r4 /* save ksp0 + cpu */
/linux-4.1.27/tools/perf/arch/s390/util/
H A Ddwarf-regs.c15 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
/linux-4.1.27/arch/arm/xen/
H A Dhypercall.S38 * in r4, differently from the procedure calling convention of using the
72 stmdb sp!, {r4} \
73 ldr r4, [sp, #4] \
76 ldm sp!, {r4} \
95 stmdb sp!, {r4}
101 ldr r4, [sp, #4]
103 ldm sp!, {r4}
/linux-4.1.27/firmware/av7110/
H A DBoot.S56 ldr r4, flag
58 str r0, [r4]
59 str r0, [r4, #4]
72 wait: ldrh r1, [r4] // wait for flag!=0
77 ldr r3, [r4,#4] // destaddr
79 ldrh r2, [r4,#2] // get segment length
83 strh r0, [r4] // that buffer is accepted by setting to 0
/linux-4.1.27/arch/unicore32/boot/compressed/
H A Dhead.S105 * r4 = final kernel address
110 * r4 >= r2 -> OK
111 * r4 + image length <= r5 -> OK
113 ldw r4, =KERNEL_IMAGE_START
114 csub.a r4, r2
116 add r0, r4, r6
136 mov r0, r4
156 ldw r4, =KERNEL_IMAGE_START
157 mov pc, r4 @ call kernel
/linux-4.1.27/drivers/block/paride/
H A Dfriq.c104 for (k=0;k<count-2;k++) buf[k] = r4(); friq_read_block_int()
106 buf[count-2] = r4(); friq_read_block_int()
107 buf[count-1] = r4(); friq_read_block_int()
114 buf[count-2] = r4(); friq_read_block_int()
115 buf[count-1] = r4(); friq_read_block_int()
121 buf[count-4] = r4(); friq_read_block_int()
122 buf[count-3] = r4(); friq_read_block_int()
124 buf[count-2] = r4(); friq_read_block_int()
125 buf[count-1] = r4(); friq_read_block_int()
/linux-4.1.27/kernel/bpf/
H A Dhelpers.c26 static u64 bpf_map_lookup_elem(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5) bpf_map_lookup_elem() argument
54 static u64 bpf_map_update_elem(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5) bpf_map_update_elem() argument
62 return map->ops->map_update_elem(map, key, value, r4); bpf_map_update_elem()
75 static u64 bpf_map_delete_elem(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5) bpf_map_delete_elem() argument
93 static u64 bpf_get_prandom_u32(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5) bpf_get_prandom_u32() argument
104 static u64 bpf_get_smp_processor_id(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5) bpf_get_smp_processor_id() argument
/linux-4.1.27/arch/s390/net/
H A Dbpf_jit.S26 * Work registers: %r2,%r4,%r5,%r14
31 * %r4 = pointer to temp buffer
38 * %r4 = length to copy
61 la %r4,STK_OFF_TMP(%r15); /* Arg3 = temp bufffer */ \
87 la %r4,STK_OFF_TMP(%r15) # Arg3 = pointer to temp buffer
100 lghi %r4,SIZE; /* Arg3 = size */ \
/linux-4.1.27/arch/m32r/include/asm/
H A Dcmpxchg.h47 DCACHE_CLEAR("%0", "r4", "%2") __xchg()
53 , "r4" __xchg()
120 DCACHE_CLEAR("%0", "r4", "%1") __cmpxchg_u32()
134 , "r4" __cmpxchg_u32()
151 DCACHE_CLEAR("%0", "r4", "%1") __cmpxchg_local_u32()
165 , "r4" __cmpxchg_local_u32()
/linux-4.1.27/arch/nios2/kernel/
H A Dentry.S151 mov r4, sp
184 ldw r4, PT_R4(sp)
253 ldw r4, PT_R4(sp)
304 mov r4, sp /* pt_regs */
311 ldw r4, PT_R4(sp) /* reload syscall arguments r4-r9 */
348 2: movi r4, %lo(-1) /* Start from bit position 0,
354 addi r4, r4, 1
370 ldw r4, TI_PREEMPT_COUNT(r1)
371 bne r4, r0, restore_all
372 ldw r4, TI_FLAGS(r1) /* ? Need resched set */
373 BTBZ r10, r4, TIF_NEED_RESCHED, restore_all
374 ldw r4, PT_ESTATUS(sp) /* ? Interrupts off */
375 andi r10, r4, ESTATUS_EPIE
403 mov r4, sp
473 * in r4, next (the new task) is in r5, don't change these
479 stw r7, TASK_THREAD + THREAD_KPSR(r4)
485 stw sp, TASK_THREAD + THREAD_KSP(r4)/* save kernel stack pointer */
502 mov r4,r17 /* arg */
537 * r4 pointer to exchange variable
542 ldw r2, 0(r4) /* load current value */
548 stw r6, 0(r4)
H A Dinsnemu.S36 ldw r4, PT_R4(sp)
131 stw r4, 16(sp)
168 roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */
169 roli r5, r4, 2 /* r5 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */
170 srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */
180 * r4 = IMM16 (sign extended)
204 /* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */
206 /* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */
207 srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */
208 andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */
214 * r4 = OPX (no longer can be muli)
222 andi r7, r4, 0x02 /* For R-type multiply instructions,
273 xori r7, r4, 0x25 /* OPX of div */
296 * r4 = 0x25 for div, 0x24 for divu
342 * r4 = 0x25 for div, 0x24 for divu
415 mov r5, r4 /* Field IMM16 is src2, not field B. */
416 movi r4, 0x27 /* OPX of mul is 0x27 */
499 * r4 = OPX
518 xori r7, r4, 0x27
525 xori r7, r4, 0x07
537 xori r7, r4, 0x17
562 ldw r4, 16(sp)
/linux-4.1.27/arch/unicore32/kernel/
H A Dsleep.S25 movc r4, p0.c2, #0 @ translation table base addr
54 stm.w (r4 - r15), [sp-] @ save registers on stack
61 cff r4, s31
62 stm.w (r4), [sp-]
175 movc p0.c2, r4, #0 @ translation table base addr
198 ldm.w (r4), [sp]+
199 ctf r4, s31
201 ldm.w (r4 - r15), [sp]+ @ restore registers from stack
/linux-4.1.27/arch/powerpc/sysdev/
H A D6xx-suspend.S20 mflr r4
51 mtlr r4
H A Ddcr-low.S38 mtdcr 0,r4; blr
43 mtdcr dcr,r4; blr
/linux-4.1.27/arch/powerpc/perf/
H A Dbhrb.S28 ld r4,bhrb_table@got(r2)
30 add r3,r4,r3
/linux-4.1.27/arch/avr32/kernel/
H A Dswitch_to.S21 stm --r11, r0,r1,r2,r3,r4,r5,r6,r7,sp,lr
34 ldm r10++, r0,r1,r2,r3,r4,r5,r6,r7,sp,pc
/linux-4.1.27/arch/m32r/boot/
H A Dsetup.S152 LDIMM (r4, _AP_RE)
156 and r4, r5
157 mvtc r4, cr5
159 seth r4, #high(M32R_ICU_IMASK_PORTL)
160 or3 r4, r4, #low(M32R_ICU_IMASK_PORTL)
162 st r5, @r4
163 ld r5, @r4
/linux-4.1.27/arch/arc/include/uapi/asm/
H A Dswab.h54 * 8051fda0: and r4,r3,0xff00
55 * 8051fda8: asl r4,r4,8 ; get 1st Byte
59 * 8051fdbc: or r2,r2,r4 ; combine 0,3 Bytes with 1st Byte
/linux-4.1.27/drivers/infiniband/hw/ehca/
H A Dhcp_if.c87 #define HCALL4_REGS_FORMAT "r4=%lx r5=%lx r6=%lx r7=%lx"
222 adapter_handle.handle, /* r4 */ hipz_h_alloc_resource_eq()
242 adapter_handle.handle, /* r4 */ hipz_h_reset_event()
257 adapter_handle.handle, /* r4 */ hipz_h_alloc_resource_cq()
274 adapter_handle.handle, /* r4 */ hipz_h_alloc_resource_cq()
331 adapter_handle.handle, /* r4 */ hipz_h_alloc_resource_qp()
361 adapter_handle.handle, /* r4 */ hipz_h_alloc_resource_qp()
387 adapter_handle.handle, /* r4 */ hipz_h_query_port()
412 adapter_handle.handle, /* r4 */ hipz_h_modify_port()
430 adapter_handle.handle, /* r4 */ hipz_h_query_hca()
443 adapter_handle.handle, /* r4 */ hipz_h_register_rpage()
476 adapter_handle.handle, /* r4 */ hipz_h_query_int_state()
535 adapter_handle.handle, /* r4 */ hipz_h_disable_and_get_wqe()
557 adapter_handle.handle, /* r4 */ hipz_h_modify_qp()
576 adapter_handle.handle, /* r4 */ hipz_h_query_qp()
594 adapter_handle.handle, /* r4 */ hipz_h_destroy_qp()
603 adapter_handle.handle, /* r4 */ hipz_h_destroy_qp()
619 adapter_handle.handle, /* r4 */ hipz_h_define_aqp0()
635 adapter_handle.handle, /* r4 */ hipz_h_define_aqp1()
657 adapter_handle.handle, /* r4 */ hipz_h_attach_mcqp()
677 adapter_handle.handle, /* r4 */ hipz_h_detach_mcqp()
698 adapter_handle.handle, /* r4 */ hipz_h_destroy_cq()
721 adapter_handle.handle, /* r4 */ hipz_h_destroy_eq()
743 adapter_handle.handle, /* r4 */ hipz_h_alloc_resource_mr()
804 adapter_handle.handle, /* r4 */ hipz_h_query_mr()
820 adapter_handle.handle, /* r4 */ hipz_h_free_resource_mr()
838 adapter_handle.handle, /* r4 */ hipz_h_reregister_pmr()
865 adapter_handle.handle, /* r4 */ hipz_h_register_smr()
887 adapter_handle.handle, /* r4 */ hipz_h_alloc_resource_mw()
905 adapter_handle.handle, /* r4 */ hipz_h_query_mw()
917 adapter_handle.handle, /* r4 */ hipz_h_free_resource_mw()
/linux-4.1.27/arch/powerpc/kernel/vdso64/
H A Ddatapage.S56 mr r4,r3
60 cmpli cr0,r4,0
64 stw r0,0(r4)
/linux-4.1.27/arch/sh/kernel/cpu/sh5/
H A Dentry.S263 st.q SP, SAVED_R4, r4
274 movi EVENT_FAULT_NOT_TLB, r4
306 st.q SP, SAVED_R4 , r4
316 gettr tr2, r4
321 st.q SP, TLB_SAVED_TR2 , r4
328 getcon TEA, r4
343 ld.q SP, TLB_SAVED_TR2, r4
350 ptabs r4, tr2
358 ld.q SP, SAVED_R4, r4
378 ld.q SP, TLB_SAVED_TR2, r4
387 ptabs/u r4, tr2
395 movi EVENT_FAULT_TLB, r4
425 st.q SP, SAVED_R4, r4
436 movi EVENT_INTERRUPT, r4
558 st.q SP, SAVED_R4, r4
569 movi EVENT_DEBUG, r4
591 st.q SP, SAVED_R4, r4
629 movi EVENT_FAULT_NOT_TLB, r4
652 * (r4) Event (0 = interrupt, 1 = TLB miss fault, 2 = Not TLB miss fault, 3=debug)
983 ld.q SP, FRAME_R(4), r4
1075 * (r4) Event (0 = interrupt, 1 = TLB miss fault, 2 = Not TLB miss fault)
1083 * (r4) Effective Address of fault
1094 getcon TEA, r4
1101 getcon TEA, r4
1107 beqi/u r4, EVENT_INTERRUPT, tr0
1112 getcon TEA, r4
1123 beqi/l r4, EVENT_INTERRUPT, tr0
1134 beqi/l r4, EVENT_INTERRUPT, tr0
1154 * (r4) Not used. Event (0=interrupt, 1=TLB miss fault, 2=Not TLB miss fault)
1184 or r5, ZERO, r4 /* TRA (=r5) -> r4 */
1185 shlri r4, 20, r4
1186 bnei r4, 1, tr0 /* unknown_trap if not 0x1yzzzz */
1195 movi NR_syscalls - 1, r4 /* Last valid */
1196 bgeu/l r4, r5, tr0
1257 ld.l r2, TI_FLAGS, r4
1259 and r6, r4, r6
1263 movi do_syscall_trace_enter, r4
1265 ptabs r4, tr0
1280 movi sys_call_table, r4
1282 ldx.l r4, r5, r5
1288 ld.q SP, FRAME_R(4), r4
1327 movi 255, r4
1328 shlli r4, 16, r4 /* r4 = mask to select ASID */
1329 and r0, r4, r3 /* r3 = shifted old ASID */
1332 andc r0, r4, r0 /* efface old ASID from SR */
1479 * (r4) size in bytes
1502 bge/u r0, r4, tr1
1508 st.q SP, 16, r4
1518 /* don't restore r2-r4, pointless */
1529 ld.q SP, 16, r4
1540 beq/u r4, r63, tr1 /* early exit for zero length copy */
1550 addi r4, -1, r4 /* No real fixup required */
1553 bne r4, ZERO, tr0
1556 or r4, ZERO, r2
1603 or r2, ZERO, r4
1608 st.b r4, 0, r5
1618 or r2, ZERO, r4
1623 st.w r4, 0, r5
1633 or r2, ZERO, r4
1638 st.l r4, 0, r5
1648 or r2, ZERO, r4
1653 st.q r4, 0, r5
1673 ld.b r2, 0, r4 /* r4 = data */
1677 st.b r3, 0, r4
1687 ld.w r2, 0, r4 /* r4 = data */
1691 st.w r3, 0, r4
1701 ld.l r2, 0, r4 /* r4 = data */
1705 st.l r3, 0, r4
1715 ld.q r2, 0, r4 /* r4 = data */
1719 st.q r3, 0, r4
1747 st.q r0, 0x020, r4
1829 getcon spc, r4
1844 st.q r0, 0x258, r4
1858 getcon EXPEVT,r4
/linux-4.1.27/arch/cris/arch-v10/lib/
H A Ddram_init.S104 1: clear.d $r4
105 move.b [$r2+], $r4
106 lslq 9, $r4 ; Command starts at bit 9
107 or.d $r1, $r4
108 move.d $r4, [R_SDRAM_TIMING]
/linux-4.1.27/arch/cris/arch-v32/mach-fs/
H A Ddram_init.S46 move.d 0x40, $r4 ; Assume 32 bits and CAS latency = 2
52 move.d 0x60, $r4
61 lslq 2, $r4 ; mrs_data starts at bit 2
62 lsrq 1, $r4 ; 16 bits. Shift down value.
86 or.d $r4, $r6 ; Add calculated mrs
/linux-4.1.27/arch/arm/mach-bcm/
H A Dbcm_kona_smc.c91 * Parameters to the "smc" request are passed in r4-r6 as follows:
92 * r4 service id
113 register u32 r4 asm("r4"); bcm_kona_do_smc()
117 r4 = service_id; bcm_kona_do_smc()
125 __asmeq("%2", "r4") bcm_kona_do_smc()
133 : "r" (r4), "r" (r5), "r" (r6) bcm_kona_do_smc()
/linux-4.1.27/arch/tile/lib/
H A Dmemcpy_32.S91 { sw sp, lr; move r23, r0; or r4, r0, r1 }
94 { bz r2, .Ldone; andi r4, r4, 3 }
101 { bnz r4, .Lcopy_unaligned_maybe_many; addli r4, r2, -256 }
105 { blzt r4, .Lcopy_8_check; slti_u r8, r2, 8 }
119 EX: { lw r4, r1; addi r1, r1, 4 }
121 EX: { sw r0, r4; addi r0, r0, 4; addi r2, r2, -4 }
123 { bzt r8, .Lcopy_8_loop; slti_u r4, r2, 4 }
126 { bnzt r4, .Lcheck_odd_stragglers }
157 EX: { lw r5, r3; addi r3, r3, 64; movei r4, 1 }
187 { bz r4, .Lcopy_8_check; slti_u r8, r2, 8 }
194 { bz r4, .Lcopy_8_check; slti_u r8, r2, 8 }
201 { bz r4, .Lcopy_8_check; slti_u r8, r2, 8 }
232 * - r4 is nonzero iff r2 >= 64.
271 EX: { lw r4, r1; addi r1, r1, 4; addi r20, r1, 16 } /* r4 = WORD_12 */
321 EX: { sw r0, r4; addi r0, r0, 4 } /* store(WORD_12) */
326 shri r4, r2, 7
346 { slti_u r8, r2, 20; sub r4, zero, r0 }
347 { bnzt r8, .Lcopy_unaligned_few; andi r4, r4, 3 }
348 { bz r4, .Ldest_is_word_aligned; add r18, r1, r2 }
358 EX: { lb_u r3, r1; addi r1, r1, 1; addi r4, r4, -1 }
360 { bnzt r4, .Lalign_dest_loop; andi r3, r1, 3 }
363 { bz r3, .Lcheck_aligned_copy_size; addli r4, r2, -256 }
/linux-4.1.27/arch/x86/crypto/sha-mb/
H A Dsha1_x8_avx2.S69 # TRANSPOSE8 r0, r1, r2, r3, r4, r5, r6, r7, t0, t1
71 # Input looks like: {r0 r1 r2 r3 r4 r5 r6 r7}
76 # r4 = {e7 e6 e5 e4 e3 e2 e1 e0}
81 # Output looks like: {r0 r1 r2 r3 r4 r5 r6 r7}
86 # r4 = {h4 g4 f4 e4 d4 c4 b4 a4}
92 .macro TRANSPOSE8 r0 r1 r2 r3 r4 r5 r6 r7 t0 t1
104 # process bottom half (r4..r7) {e...h}
105 vshufps $0x44, \r5, \r4, \r2 # r2 = {f5 f4 e5 e4 f1 f0 e1 e0}
106 vshufps $0xEE, \r5, \r4, \r4 # r4 = {f7 f6 e7 e6 f3 f2 e3 e2}
110 vshufps $0x88, \r6, \r4, \r5 # r5 = {h6 g6 f6 e6 h2 g2 f2 e2}
111 vshufps $0xDD, \r6, \r4, \r4 # r4 = {h7 g7 f7 e7 h3 g3 f3 e3}
118 vperm2f128 $0x13, \r0, \r4, \r7 # h7...a7
119 vperm2f128 $0x02, \r0, \r4, \r3 # h3...a3
120 vperm2f128 $0x13, \t0, \t1, \r4 # h4...a4

Completed in 2194 milliseconds

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