1/*
2 * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
3 * Dave Liu <daveliu@freescale.com>
4 * copy from idle_6xx.S and modify for e500 based processor,
5 * implement the power_save function in idle.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <linux/threads.h>
14#include <asm/reg.h>
15#include <asm/page.h>
16#include <asm/cputable.h>
17#include <asm/thread_info.h>
18#include <asm/ppc_asm.h>
19#include <asm/asm-offsets.h>
20
21	.text
22
23_GLOBAL(e500_idle)
24	CURRENT_THREAD_INFO(r3, r1)
25	lwz	r4,TI_LOCAL_FLAGS(r3)	/* set napping bit */
26	ori	r4,r4,_TLF_NAPPING	/* so when we take an exception */
27	stw	r4,TI_LOCAL_FLAGS(r3)	/* it will return to our caller */
28
29#ifdef CONFIG_PPC_E500MC
30	wrteei	1
311:	wait
32
33	/*
34	 * Guard against spurious wakeups (e.g. from a hypervisor) --
35	 * any real interrupt will cause us to return to LR due to
36	 * _TLF_NAPPING.
37	 */
38	b	1b
39#else
40	/* Check if we can nap or doze, put HID0 mask in r3 */
41	lis	r3,0
42BEGIN_FTR_SECTION
43	lis	r3,HID0_DOZE@h
44END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
45
46BEGIN_FTR_SECTION
47	/* Now check if user enabled NAP mode */
48	lis	r4,powersave_nap@ha
49	lwz	r4,powersave_nap@l(r4)
50	cmpwi	0,r4,0
51	beq	1f
52	stwu	r1,-16(r1)
53	mflr	r0
54	stw	r0,20(r1)
55	bl	flush_dcache_L1
56	lwz	r0,20(r1)
57	addi	r1,r1,16
58	mtlr	r0
59	lis	r3,HID0_NAP@h
60END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
61BEGIN_FTR_SECTION
62	msync
63	li	r7,L2CSR0_L2FL@l
64	mtspr	SPRN_L2CSR0,r7
652:
66	mfspr	r7,SPRN_L2CSR0
67	andi.	r4,r7,L2CSR0_L2FL@l
68	bne	2b
69END_FTR_SECTION_IFSET(CPU_FTR_L2CSR|CPU_FTR_CAN_NAP)
701:
71	/* Go to NAP or DOZE now */
72	mfspr	r4,SPRN_HID0
73	rlwinm	r4,r4,0,~(HID0_DOZE|HID0_NAP|HID0_SLEEP)
74	or	r4,r4,r3
75	isync
76	mtspr	SPRN_HID0,r4
77	isync
78
79	mfmsr	r7
80	oris	r7,r7,MSR_WE@h
81	ori	r7,r7,MSR_EE
82	msync
83	mtmsr	r7
84	isync
852:	b	2b
86#endif /* !E500MC */
87
88/*
89 * Return from NAP/DOZE mode, restore some CPU specific registers,
90 * r2 containing physical address of current.
91 * r11 points to the exception frame (physical address).
92 * We have to preserve r10.
93 */
94_GLOBAL(power_save_ppc32_restore)
95	lwz	r9,_LINK(r11)		/* interrupted in e500_idle */
96	stw	r9,_NIP(r11)		/* make it do a blr */
97
98#ifdef CONFIG_SMP
99	CURRENT_THREAD_INFO(r12, r1)
100	lwz	r11,TI_CPU(r12)		/* get cpu number * 4 */
101	slwi	r11,r11,2
102#else
103	li	r11,0
104#endif
105
106	b	transfer_to_handler_cont
107