1/*
2 *  arch/s390/kernel/base.S
3 *
4 *    Copyright IBM Corp. 2006, 2007
5 *    Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
6 *		 Michael Holzheu <holzheu@de.ibm.com>
7 */
8
9#include <linux/linkage.h>
10#include <asm/asm-offsets.h>
11#include <asm/ptrace.h>
12#include <asm/sigp.h>
13
14ENTRY(s390_base_mcck_handler)
15	basr	%r13,0
160:	lg	%r15,__LC_PANIC_STACK	# load panic stack
17	aghi	%r15,-STACK_FRAME_OVERHEAD
18	larl	%r1,s390_base_mcck_handler_fn
19	lg	%r1,0(%r1)
20	ltgr	%r1,%r1
21	jz	1f
22	basr	%r14,%r1
231:	la	%r1,4095
24	lmg	%r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)
25	lpswe	__LC_MCK_OLD_PSW
26
27	.section .bss
28	.align 8
29	.globl	s390_base_mcck_handler_fn
30s390_base_mcck_handler_fn:
31	.quad	0
32	.previous
33
34ENTRY(s390_base_ext_handler)
35	stmg	%r0,%r15,__LC_SAVE_AREA_ASYNC
36	basr	%r13,0
370:	aghi	%r15,-STACK_FRAME_OVERHEAD
38	larl	%r1,s390_base_ext_handler_fn
39	lg	%r1,0(%r1)
40	ltgr	%r1,%r1
41	jz	1f
42	basr	%r14,%r1
431:	lmg	%r0,%r15,__LC_SAVE_AREA_ASYNC
44	ni	__LC_EXT_OLD_PSW+1,0xfd	# clear wait state bit
45	lpswe	__LC_EXT_OLD_PSW
46
47	.section .bss
48	.align 8
49	.globl s390_base_ext_handler_fn
50s390_base_ext_handler_fn:
51	.quad	0
52	.previous
53
54ENTRY(s390_base_pgm_handler)
55	stmg	%r0,%r15,__LC_SAVE_AREA_SYNC
56	basr	%r13,0
570:	aghi	%r15,-STACK_FRAME_OVERHEAD
58	larl	%r1,s390_base_pgm_handler_fn
59	lg	%r1,0(%r1)
60	ltgr	%r1,%r1
61	jz	1f
62	basr	%r14,%r1
63	lmg	%r0,%r15,__LC_SAVE_AREA_SYNC
64	lpswe	__LC_PGM_OLD_PSW
651:	lpswe	disabled_wait_psw-0b(%r13)
66
67	.align	8
68disabled_wait_psw:
69	.quad	0x0002000180000000,0x0000000000000000 + s390_base_pgm_handler
70
71	.section .bss
72	.align 8
73	.globl s390_base_pgm_handler_fn
74s390_base_pgm_handler_fn:
75	.quad	0
76	.previous
77
78#
79# Calls diag 308 subcode 1 and continues execution
80#
81# The following conditions must be ensured before calling this function:
82# * Prefix register = 0
83# * Lowcore protection is disabled
84#
85ENTRY(diag308_reset)
86	larl	%r4,.Lctlregs		# Save control registers
87	stctg	%c0,%c15,0(%r4)
88	larl	%r4,.Lfpctl		# Floating point control register
89	stfpc	0(%r4)
90	larl	%r4,.Lcontinue_psw	# Save PSW flags
91	epsw	%r2,%r3
92	stm	%r2,%r3,0(%r4)
93	larl	%r4,.Lrestart_psw	# Setup restart PSW at absolute 0
94	lghi	%r3,0
95	lg	%r4,0(%r4)		# Save PSW
96	sturg	%r4,%r3			# Use sturg, because of large pages
97	lghi	%r1,1
98	lghi	%r0,0
99	diag	%r0,%r1,0x308
100.Lrestart_part2:
101	lhi	%r0,0			# Load r0 with zero
102	lhi	%r1,2			# Use mode 2 = ESAME (dump)
103	sigp	%r1,%r0,SIGP_SET_ARCHITECTURE	# Switch to ESAME mode
104	sam64				# Switch to 64 bit addressing mode
105	larl	%r4,.Lctlregs		# Restore control registers
106	lctlg	%c0,%c15,0(%r4)
107	larl	%r4,.Lfpctl		# Restore floating point ctl register
108	lfpc	0(%r4)
109	larl	%r4,.Lcontinue_psw	# Restore PSW flags
110	lpswe	0(%r4)
111.Lcontinue:
112	br	%r14
113.align 16
114.Lrestart_psw:
115	.long	0x00080000,0x80000000 + .Lrestart_part2
116
117	.section .data..nosave,"aw",@progbits
118.align 8
119.Lcontinue_psw:
120	.quad	0,.Lcontinue
121	.previous
122
123	.section .bss
124.align 8
125.Lctlregs:
126	.rept	16
127	.quad	0
128	.endr
129.Lfpctl:
130	.long	0
131	.previous
132