Lines Matching refs:r4
30 VFPFMRX r4, FPINST
48 VFPFMXR FPINST, r4
66 mrs r4, SPSR_\mode
67 push {r2, r3, r4}
80 push {r4-r12} @ r0-r3 are always clobbered
93 mrs r4, r10_fiq
103 pop {r2, r3, r4}
106 msr SPSR_\mode, r4
117 msr r10_fiq, r4
132 pop {r4-r12}
148 ldm r1, {r2, r3, r4}
151 msr SPSR_\mode, r4
171 msr r10_fiq, r4
204 mrs r4, LR_\mode
206 stm r2, {r3, r4, r5}
222 pop {r3, r4, r5} @ r0, r1, r2
223 stm r2, {r3, r4, r5}
253 mrc p15, 0, r4, c2, c0, 2 @ TTBCR
266 str r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
279 mrc p15, 0, r4, c13, c0, 3 @ TID_URO
294 str r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
306 mrrc p15, 0, r4, r5, c7 @ PAR
311 push {r2,r4-r7}
315 strd r4, r5, [r12]
330 pop {r2,r4-r7}
334 ldrd r4, r5, [r12]
340 mcrr p15, 0, r4, r5, c7 @ PAR
349 ldr r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
362 mcr p15, 0, r4, c13, c0, 3 @ TID_URO
377 ldr r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
390 mcr p15, 0, r4, c2, c0, 2 @ TTBCR
416 ldr r4, [r2, #GICH_VMCR]
424 ARM_BE8(rev r4, r4 )
433 str r4, [r11, #VGIC_V2_CPU_VMCR]
455 ldr r4, [r11, #VGIC_CPU_NR_LR]
459 subs r4, r4, #1
481 ldr r4, [r11, #VGIC_V2_CPU_VMCR]
484 ARM_BE8(rev r4, r4 )
488 str r4, [r2, #GICH_VMCR]
494 ldr r4, [r11, #VGIC_CPU_NR_LR]
498 subs r4, r4, #1
514 ldr r4, [vcpu, #VCPU_KVM]
515 ldr r2, [r4, #KVM_TIMER_ENABLED]
525 ldr r4, =VCPU_TIMER_CNTV_CVAL
526 add r5, vcpu, r4
558 ldr r4, [vcpu, #VCPU_KVM]
559 ldr r2, [r4, #KVM_TIMER_ENABLED]
563 ldr r2, [r4, #KVM_TIMER_CNTVOFF]
564 ldr r3, [r4, #(KVM_TIMER_CNTVOFF + 4)]
567 ldr r4, =VCPU_TIMER_CNTV_CVAL
568 add r5, vcpu, r4