Lines Matching refs:r4
53 DISABLE_INTERRUPTS(r3,r4) ;\
60 l.lwz r4,PT_GPR4(r1) ;\
326 l.addi r2,r4,0
331 l.srli r4,r3,26 /* Shift left to get the insn opcode */
333 l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */
335 l.sfeqi r4,0x01
337 l.sfeqi r4,0x03
339 l.sfeqi r4,0x04
341 l.sfeqi r4,0x11
343 l.sfeqi r4,0x12
350 l.slli r4,r3,6 /* Get the signed extended jump length */
351 l.srai r4,r4,4
355 l.add r5,r5,r4 /* Calculate jump target address */
358 l.srli r4,r3,26 /* Shift left to get the insn opcode */
361 l.slli r4,r3,9 /* Shift to get the reg nb */
362 l.andi r4,r4,0x7c
366 l.add r4,r4,r1 /* Load the jump register value from the stack */
367 l.lwz r5,0(r4)
369 l.srli r4,r3,26 /* Shift left to get the insn opcode */
376 l.sfeqi r4,0x26
378 l.sfeqi r4,0x25
380 l.sfeqi r4,0x22
382 l.sfeqi r4,0x21
384 l.sfeqi r4,0x37
386 l.sfeqi r4,0x35
397 l.srli r4,r3,19
398 l.andi r4,r4,0x7c
399 l.add r4,r4,r1
401 l.sw 0(r4),r5
407 l.srli r4,r3,19
408 l.andi r4,r4,0x7c
409 l.add r4,r4,r1
411 l.sw 0(r4),r5
423 l.srli r4,r3,19
424 l.andi r4,r4,0x7c
425 l.add r4,r4,r1
427 l.sw 0(r4),r5
439 l.srli r4,r3,19
440 l.andi r4,r4,0x7c
441 l.add r4,r4,r1
443 l.sw 0(r4),r5
446 l.srli r4,r3,9
447 l.andi r4,r4,0x7c
448 l.add r4,r4,r1
449 l.lwz r5,0(r4)
456 l.srli r4,r3,9
457 l.andi r4,r4,0x7c
458 l.add r4,r4,r1
459 l.lwz r5,0(r4)
488 l.lwz r4,PT_SR(r1) // were interrupts enabled ?
489 l.andi r4,r4,SPR_SR_IEE
490 l.sfeqi r4,0
499 l.sw 0x4(r1),r4
508 l.ori r4,r4,SPR_SR_IEE // fix the bug
561 l.lwz r4,PT_GPR4(r1)
700 l.lwz r4,PT_GPR4(r1)
746 l.lwz r4,PT_GPR4(r1)
857 DISABLE_INTERRUPTS(r3,r4)
858 l.lwz r4,TI_FLAGS(r10)
859 l.andi r13,r4,_TIF_WORK_MASK
888 l.lwz r4,PT_GPR4(r1)
902 l.lwz r4,PT_SR(r1)
903 l.andi r3,r4,SPR_SR_SM
1023 l.or r10,r4,r0 /* Set up new current_thread_info */
1124 l.lwz r29,0(r4)
1126 l.sw 0(r4),r27