Lines Matching refs:r4
50 neg r6,r4
55 lbz r0,0(r4)
56 addi r4,r4,1
61 lhz r0,0(r4)
62 addi r4,r4,2
67 lwz r0,0(r4)
68 addi r4,r4,4
95 ld r0,0(r4)
96 ld r6,8(r4)
97 ld r7,16(r4)
98 ld r8,24(r4)
99 ld r9,32(r4)
100 ld r10,40(r4)
101 ld r11,48(r4)
102 ld r12,56(r4)
103 ld r14,64(r4)
104 ld r15,72(r4)
105 ld r16,80(r4)
106 ld r17,88(r4)
107 ld r18,96(r4)
108 ld r19,104(r4)
109 ld r20,112(r4)
110 ld r21,120(r4)
111 addi r4,r4,128
149 ld r0,0(r4)
150 ld r6,8(r4)
151 ld r7,16(r4)
152 ld r8,24(r4)
153 ld r9,32(r4)
154 ld r10,40(r4)
155 ld r11,48(r4)
156 ld r12,56(r4)
157 addi r4,r4,64
170 ld r0,0(r4)
171 ld r6,8(r4)
172 ld r7,16(r4)
173 ld r8,24(r4)
174 addi r4,r4,32
183 ld r0,0(r4)
184 ld r6,8(r4)
185 addi r4,r4,16
196 lwz r0,0(r4) /* Less chance of a reject with word ops */
197 lwz r6,4(r4)
198 addi r4,r4,8
204 lwz r0,0(r4)
205 addi r4,r4,4
210 lhz r0,0(r4)
211 addi r4,r4,2
216 lbz r0,0(r4)
229 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
237 ld r4,STK_REG(R30)(r1)
246 clrrdi r6,r4,7
278 xor r6,r4,r3
288 lbz r0,0(r4)
289 addi r4,r4,1
294 lhz r0,0(r4)
295 addi r4,r4,2
300 lwz r0,0(r4)
301 addi r4,r4,4
306 ld r0,0(r4)
307 addi r4,r4,8
324 lvx v1,r0,r4
325 addi r4,r4,16
330 lvx v1,r0,r4
331 lvx v0,r4,r9
332 addi r4,r4,32
338 lvx v3,r0,r4
339 lvx v2,r4,r9
340 lvx v1,r4,r10
341 lvx v0,r4,r11
342 addi r4,r4,64
369 lvx v7,r0,r4
370 lvx v6,r4,r9
371 lvx v5,r4,r10
372 lvx v4,r4,r11
373 lvx v3,r4,r12
374 lvx v2,r4,r14
375 lvx v1,r4,r15
376 lvx v0,r4,r16
377 addi r4,r4,128
399 lvx v3,r0,r4
400 lvx v2,r4,r9
401 lvx v1,r4,r10
402 lvx v0,r4,r11
403 addi r4,r4,64
411 lvx v1,r0,r4
412 lvx v0,r4,r9
413 addi r4,r4,32
419 lvx v1,r0,r4
420 addi r4,r4,16
428 ld r0,0(r4)
429 addi r4,r4,8
434 lwz r0,0(r4)
435 addi r4,r4,4
440 lhz r0,0(r4)
441 addi r4,r4,2
446 lbz r0,0(r4)
460 lbz r0,0(r4)
461 addi r4,r4,1
466 lhz r0,0(r4)
467 addi r4,r4,2
472 lwz r0,0(r4)
473 addi r4,r4,4
478 lwz r0,0(r4) /* Less chance of a reject with word ops */
479 lwz r7,4(r4)
480 addi r4,r4,8
497 LVS(v16,0,r4) /* Setup permute control vector */
498 lvx v0,0,r4
499 addi r4,r4,16
502 lvx v1,r0,r4
504 addi r4,r4,16
510 lvx v1,r0,r4
512 lvx v0,r4,r9
514 addi r4,r4,32
520 lvx v3,r0,r4
522 lvx v2,r4,r9
524 lvx v1,r4,r10
526 lvx v0,r4,r11
528 addi r4,r4,64
555 lvx v7,r0,r4
557 lvx v6,r4,r9
559 lvx v5,r4,r10
561 lvx v4,r4,r11
563 lvx v3,r4,r12
565 lvx v2,r4,r14
567 lvx v1,r4,r15
569 lvx v0,r4,r16
571 addi r4,r4,128
593 lvx v3,r0,r4
595 lvx v2,r4,r9
597 lvx v1,r4,r10
599 lvx v0,r4,r11
601 addi r4,r4,64
609 lvx v1,r0,r4
611 lvx v0,r4,r9
613 addi r4,r4,32
619 lvx v1,r0,r4
621 addi r4,r4,16
627 addi r4,r4,-16 /* Unwind the +16 load offset */
630 lwz r0,0(r4) /* Less chance of a reject with word ops */
631 lwz r6,4(r4)
632 addi r4,r4,8
638 lwz r0,0(r4)
639 addi r4,r4,4
644 lhz r0,0(r4)
645 addi r4,r4,2
650 lbz r0,0(r4)